at91_ssc.h

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#ifndef _ARCH_ARM_AT91_SSC_H_
#define _ARCH_ARM_AT91_SSC_H_

/*
 * Copyright (C) 2006-2007 by egnite Software GmbH. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the name of the copyright holders nor the names of
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
 * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
 * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 * For additional information see http://www.ethernut.de/
 */


#define SSC_CR_OFF                  0x00000000  
#define SSC_CR      (SSC_BASE + SSC_CR_OFF)     
#define SSC_RXEN                    0x00000001  
#define SSC_RXDIS                   0x00000002  
#define SSC_TXEN                    0x00000100  
#define SSC_TXDIS                   0x00000200  
#define SSC_SWRST                   0x00008000  


#define SSC_CMR_OFF                 0x00000004  
#define SSC_CMR     (SSC_BASE + SSC_CMR_OFF)    
#define SSC_DIV_LSB                         0   
#define SSC_DIV                     0x00000FFF  


#define SSC_RCMR_OFF                0x00000010  
#define SSC_RCMR    (SSC_BASE + SSC_RCMR_OFF)   
#define SSC_TCMR_OFF                0x00000018  
#define SSC_TCMR    (SSC_BASE + SSC_TCMR_OFF)   
#define SSC_CKS                     0x00000003  
#define SSC_CKS_DIV                 0x00000000  
#define SSC_CKS_CLK                 0x00000001  
#define SSC_CKS_PIN                 0x00000002  
#define SSC_CKO                     0x0000001C  
#define SSC_CKO_NONE                0x00000000  
#define SSC_CKO_CONT                0x00000004  
#define SSC_CKO_TRAN                0x00000008  
#define SSC_CKI                     0x00000020  
#define SSC_CKG                     0x000000C0  
#define SSC_CKG_NONE                0x00000000  
#define SSC_CKG_RFL                 0x00000040  
#define SSC_CKG_RFH                 0x00000080  
#define SSC_START                   0x00000F00  
#define SSC_START_CONT              0x00000000  
#define SSC_START_TX                0x00000100  
#define SSC_START_LOW_RF            0x00000200  
#define SSC_START_HIGH_RF           0x00000300  
#define SSC_START_FALL_RF           0x00000400  
#define SSC_START_RISE_RF           0x00000500  
#define SSC_START_LEVEL_RF          0x00000600  
#define SSC_START_EDGE_RF           0x00000700  
#define SSC_START_COMP0             0x00000800  
#define SSC_STOP                    0x00001000  
#define SSC_STTDLY                  0x00FF0000  
#define SSC_STTDLY_LSB                      16  
#define SSC_PERIOD                  0xFF000000  
#define SSC_PERIOD_LSB                      24  


#define SSC_RFMR_OFF                0x00000014  
#define SSC_RFMR    (SSC_BASE + SSC_RFMR_OFF)   
#define SSC_TFMR_OFF                0x0000001C  
#define SSC_TFMR    (SSC_BASE + SSC_TFMR_OFF)   
#define SSC_DATLEN                  0x0000001F  
#define SSC_DATLEN_LSB                      0   
#define SSC_LOOP                    0x00000020  
#define SSC_DATDEF                  0x00000020  
#define SSC_MSBF                    0x00000080  
#define SSC_DATNB                   0x00000F00  
#define SSC_DATNB_LSB                       8   
#define SSC_FSLEN                   0x000F0000  
#define SSC_FSLEN_LSB                       16  
#define SSC_FSOS                    0x00700000  
#define SSC_FSOS_NONE               0x00000000  
#define SSC_FSOS_NEGATIVE           0x00100000  
#define SSC_FSOS_POSITIVE           0x00200000  
#define SSC_FSOS_LOW                0x00300000  
#define SSC_FSOS_HIGH               0x00400000  
#define SSC_FSOS_TOGGLE             0x00500000  
#define SSC_FSDEN                   0x00800000  
#define SSC_FSEDGE                  0x01000000  


#define SSC_RHR_OFF                 0x00000020  
#define SSC_RHR     (SSC_BASE + SSC_RHR_OFF)    


#define SSC_THR_OFF                 0x00000024  
#define SSC_THR     (SSC_BASE + SSC_THR_OFF)    


#define SSC_RSHR_OFF                0x00000030  
#define SSC_RSHR    (SSC_BASE + SSC_RSHR_OFF)   


#define SSC_TSHR_OFF                0x00000034  
#define SSC_TSHR    (SSC_BASE + SSC_TSHR_OFF)   


#define SSC_RC0R_OFF                0x00000038  
#define SSC_RC0R    (SSC_BASE + SSC_RC0R_OFF)   


#define SSC_RC1R_OFF                0x0000003C  
#define SSC_RC1R    (SSC_BASE + SSC_RC1R_OFF)   


#define SSC_SR_OFF                  0x00000040  
#define SSC_SR      (SSC_BASE + SSC_SR_OFF)     
#define SSC_TXRDY                   0x00000001  
#define SSC_TXEMPTY                 0x00000002  
#define SSC_ENDTX                   0x00000004  
#define SSC_TXBUFE                  0x00000008  
#define SSC_RXRDY                   0x00000010  
#define SSC_OVRUN                   0x00000020  
#define SSC_ENDRX                   0x00000040  
#define SSC_RXBUFF                  0x00000080  
#define SSC_CP0                     0x00000100  
#define SSC_CP1                     0x00000200  
#define SSC_TXSYN                   0x00000400  
#define SSC_RXSYN                   0x00000800  
#define SSC_TXENA                   0x00010000  
#define SSC_RXENA                   0x00020000  


#define SSC_IER_OFF                 0x00000044  
#define SSC_IER     (SSC_BASE + SSC_IER_OFF)    


#define SSC_IDR_OFF                 0x00000048  
#define SSC_IDR     (SSC_BASE + SSC_IDR_OFF)    


#define SSC_IMR_OFF                 0x0000004C  
#define SSC_IMR     (SSC_BASE + SSC_IMR_OFF)    

#if defined(SSC_HAS_PDC)

#define SSC_RPR    (SSC_BASE + PERIPH_RPR_OFF)  


#define SSC_RCR    (SSC_BASE + PERIPH_RCR_OFF)  


#define SSC_TPR    (SSC_BASE + PERIPH_TPR_OFF)  


#define SSC_TCR    (SSC_BASE + PERIPH_TCR_OFF)  


#define SSC_RNPR   (SSC_BASE + PERIPH_RNPR_OFF) 


#define SSC_RNCR   (SSC_BASE + PERIPH_RNCR_OFF) 


#define SSC_TNPR   (SSC_BASE + PERIPH_TNPR_OFF) 


#define SSC_TNCR   (SSC_BASE + PERIPH_TNCR_OFF) 


#define SSC_PTCR   (SSC_BASE + PERIPH_PTCR_OFF) 


#define SSC_PTSR   (SSC_BASE + PERIPH_PTSR_OFF) 

#endif

#endif                          /* _ARCH_ARM_AT91_SSC_H_ */