 |
Nut/OS
4.10.3
API Reference
|
|
|
Nut/OS
4.10.3
API Reference
|
|
00001 #ifndef _ARCH_ARM_AT91_TC_H_ 00002 #define _ARCH_ARM_AT91_TC_H_ 00003 00004 /* 00005 * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved. 00006 * 00007 * Redistribution and use in source and binary forms, with or without 00008 * modification, are permitted provided that the following conditions 00009 * are met: 00010 * 00011 * 1. Redistributions of source code must retain the above copyright 00012 * notice, this list of conditions and the following disclaimer. 00013 * 2. Redistributions in binary form must reproduce the above copyright 00014 * notice, this list of conditions and the following disclaimer in the 00015 * documentation and/or other materials provided with the distribution. 00016 * 3. Neither the name of the copyright holders nor the names of 00017 * contributors may be used to endorse or promote products derived 00018 * from this software without specific prior written permission. 00019 * 00020 * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS 00021 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 00022 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 00023 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE 00024 * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 00025 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 00026 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 00027 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 00028 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00029 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 00030 * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 00031 * SUCH DAMAGE. 00032 * 00033 * For additional information see http://www.ethernut.de/ 00034 */ 00035 00054 00057 #define TC0_BASE (TC_BASE + 0x00) 00058 #define TC1_BASE (TC_BASE + 0x40) 00059 #define TC2_BASE (TC_BASE + 0x80) 00060 #define TC3_BASE (TC_BLK1_BASE + 0x00) 00061 #define TC4_BASE (TC_BLK1_BASE + 0x40) 00062 #define TC5_BASE (TC_BLK1_BASE + 0x80) 00064 00065 00067 #define TC_CCR_OFF 0x00 00069 #define TC0_CCR (TC0_BASE + TC_CCR_OFF) 00070 #define TC1_CCR (TC1_BASE + TC_CCR_OFF) 00071 #define TC2_CCR (TC2_BASE + TC_CCR_OFF) 00072 #define TC3_CCR (TC3_BASE + TC_CCR_OFF) 00073 #define TC4_CCR (TC4_BASE + TC_CCR_OFF) 00074 #define TC5_CCR (TC5_BASE + TC_CCR_OFF) 00076 #define TC_CLKEN 0x00000001 00077 #define TC_CLKDIS 0x00000002 00078 #define TC_SWTRG 0x00000004 00080 00081 00083 #define TC_CMR_OFF 0x04 00085 #define TC0_CMR (TC0_BASE + TC_CMR_OFF) 00086 #define TC1_CMR (TC1_BASE + TC_CMR_OFF) 00087 #define TC2_CMR (TC2_BASE + TC_CMR_OFF) 00088 #define TC3_CMR (TC3_BASE + TC_CMR_OFF) 00089 #define TC4_CMR (TC4_BASE + TC_CMR_OFF) 00090 #define TC5_CMR (TC5_BASE + TC_CMR_OFF) 00092 #define TC_CLKS 0x00000007 00093 #define TC_CLKS_TIMER_CLOCK1 0x00000000 00094 #define TC_CLKS_MCK2 TC_CLKS_TIMER_CLOCK1 00095 #define TC_CLKS_TIMER_CLOCK2 0x00000001 00096 #define TC_CLKS_MCK8 TC_CLKS_TIMER_CLOCK2 00097 #define TC_CLKS_TIMER_CLOCK3 0x00000002 00098 #define TC_CLKS_MCK32 TC_CLKS_TIMER_CLOCK3 00099 #define TC_CLKS_TIMER_CLOCK4 0x00000003 00100 #define TC_CLKS_MCK128 TC_CLKS_TIMER_CLOCK4 00101 #define TC_CLKS_TIMER_CLOCK5 0x00000004 00102 #define TC_CLKS_MCK1024 TC_CLKS_TIMER_CLOCK5 00103 #define TC_CLKS_SLCK TC_CLKS_TIMER_CLOCK5 00104 #define TC_CLKS_XC0 0x00000005 00105 #define TC_CLKS_XC1 0x00000006 00106 #define TC_CLKS_XC2 0x00000007 00108 #define TC_CLKI 0x00000008 00110 #define TC_BURST 0x00000030 00111 #define TC_BURST_NONE 0x00000000 00112 #define TC_BUSRT_XC0 0x00000010 00113 #define TC_BURST_XC1 0x00000020 00114 #define TC_BURST_XC2 0x00000030 00116 #define TC_CPCTRG 0x00004000 00118 #define TC_WAVE 0x00008000 00119 #define TC_CAPT 0x00000000 00121 00122 00124 #define TC_LDBSTOP 0x00000040 00125 #define TC_LDBDIS 0x00000080 00127 #define TC_ETRGEDG 0x00000300 00128 #define TC_ETRGEDG_RISING_EDGE 0x00000100 00129 #define TC_ETRGEDG_FALLING_EDGE 0x00000200 00130 #define TC_ETRGEDG_BOTH_EDGE 0x00000300 00132 #define TC_ABETRG 0x00000400 00133 #define TC_ABETRG_TIOB 0x00000000 00134 #define TC_ABETRG_TIOA 0x00000400 00136 #define TC_LDRA 0x00030000 00137 #define TC_LDRA_RISING_EDGE 0x00010000 00138 #define TC_LDRA_FALLING_EDGE 0x00020000 00139 #define TC_LDRA_BOTH_EDGE 0x00030000 00141 #define TC_LDRB 0x000C0000 00142 #define TC_LDRB_RISING_EDGE 0x00040000 00143 #define TC_LDRB_FALLING_EDGE 0x00080000 00144 #define TC_LDRB_BOTH_EDGE 0x000C0000 00147 00148 00150 #define TC_CPCSTOP 0x00000040 00151 #define TC_CPCDIS 0x00000080 00153 #define TC_EEVTEDG 0x00000300 00154 #define TC_EEVTEDG_RISING_EDGE 0x00000100 00155 #define TC_EEVTEDG_FALLING_EDGE 0x00000200 00156 #define TC_EEVTEDG_BOTH_EDGE 0x00000300 00158 #define TC_EEVT 0x00000C00 00159 #define TC_EEVT_TIOB 0x00000000 00160 #define TC_EEVT_XC0 0x00000400 00161 #define TC_EEVT_XC1 0x00000800 00162 #define TC_EEVT_XC2 0x00000C00 00164 #define TC_ENETRG 0x00001000 00166 #define TC_WAVSEL_UPDOWN 0x00002000 00167 #define TC_WAVSEL_RCTRIG 0x00004000 00169 #define TC_ACPA 0x00030000 00170 #define TC_ACPA_SET_OUTPUT 0x00010000 00171 #define TC_ACPA_CLEAR_OUTPUT 0x00020000 00172 #define TC_ACPA_TOGGLE_OUTPUT 0x00030000 00174 #define TC_ACPC 0x000C0000 00175 #define TC_ACPC_SET_OUTPUT 0x00040000 00176 #define TC_ACPC_CLEAR_OUTPUT 0x00080000 00177 #define TC_ACPC_TOGGLE_OUTPUT 0x000C0000 00179 #define TC_AEEVT 0x00300000 00180 #define TC_AEEVT_SET_OUTPUT 0x00100000 00181 #define TC_AEEVT_CLEAR_OUTPUT 0x00200000 00182 #define TC_AEEVT_TOGGLE_OUTPUT 0x00300000 00184 #define TC_ASWTRG 0x00C00000 00185 #define TC_ASWTRG_SET_OUTPUT 0x00400000 00186 #define TC_ASWTRG_CLEAR_OUTPUT 0x00800000 00187 #define TC_ASWTRG_TOGGLE_OUTPUT 0x00C00000 00189 #define TC_BCPB 0x03000000 00190 #define TC_BCPB_SET_OUTPUT 0x01000000 00191 #define TC_BCPB_CLEAR_OUTPUT 0x02000000 00192 #define TC_BCPB_TOGGLE_OUTPUT 0x03000000 00194 #define TC_BCPC 0x0C000000 00195 #define TC_BCPC_SET_OUTPUT 0x04000000 00196 #define TC_BCPC_CLEAR_OUTPUT 0x08000000 00197 #define TC_BCPC_TOGGLE_OUTPUT 0x0C000000 00199 #define TC_BEEVT 0x30000000 00200 #define TC_BEEVT_SET_OUTPUT 0x10000000 00201 #define TC_BEEVT_CLEAR_OUTPUT 0x20000000 00202 #define TC_BEEVT_TOGGLE_OUTPUT 0x30000000 00204 #define TC_BSWTRG 0xC0000000 00205 #define TC_BSWTRG_SET_OUTPUT 0x40000000 00206 #define TC_BSWTRG_CLEAR_OUTPUT 0x80000000 00207 #define TC_BSWTRG_TOGGLE_OUTPUT 0xC0000000 00209 00210 00212 #define TC_CV_OFF 0x10 00214 #define TC0_CV (TC0_BASE + TC_CV_OFF) 00215 #define TC1_CV (TC1_BASE + TC_CV_OFF) 00216 #define TC2_CV (TC2_BASE + TC_CV_OFF) 00217 #define TC3_CV (TC3_BASE + TC_CV_OFF) 00218 #define TC4_CV (TC4_BASE + TC_CV_OFF) 00219 #define TC5_CV (TC5_BASE + TC_CV_OFF) 00221 00222 00224 #define TC_RA_OFF 0x14 00226 #define TC0_RA (TC0_BASE + TC_RA_OFF) 00227 #define TC1_RA (TC1_BASE + TC_RA_OFF) 00228 #define TC2_RA (TC2_BASE + TC_RA_OFF) 00229 #define TC3_RA (TC3_BASE + TC_RA_OFF) 00230 #define TC4_RA (TC4_BASE + TC_RA_OFF) 00231 #define TC5_RA (TC5_BASE + TC_RA_OFF) 00233 00234 00236 #define TC_RB_OFF 0x18 00238 #define TC0_RB (TC0_BASE + TC_RB_OFF) 00239 #define TC1_RB (TC1_BASE + TC_RB_OFF) 00240 #define TC2_RB (TC2_BASE + TC_RB_OFF) 00241 #define TC3_RB (TC3_BASE + TC_RB_OFF) 00242 #define TC4_RB (TC4_BASE + TC_RB_OFF) 00243 #define TC5_RB (TC5_BASE + TC_RB_OFF) 00245 00246 00248 #define TC_RC_OFF 0x1C 00250 #define TC0_RC (TC0_BASE + TC_RC_OFF) 00251 #define TC1_RC (TC1_BASE + TC_RC_OFF) 00252 #define TC2_RC (TC2_BASE + TC_RC_OFF) 00253 #define TC3_RC (TC3_BASE + TC_RC_OFF) 00254 #define TC4_RC (TC4_BASE + TC_RC_OFF) 00255 #define TC5_RC (TC5_BASE + TC_RC_OFF) 00257 00258 00261 #define TC_SR_OFF 0x20 00263 #define TC0_SR (TC0_BASE + TC_SR_OFF) 00264 #define TC1_SR (TC1_BASE + TC_SR_OFF) 00265 #define TC2_SR (TC2_BASE + TC_SR_OFF) 00266 #define TC3_SR (TC3_BASE + TC_SR_OFF) 00267 #define TC4_SR (TC4_BASE + TC_SR_OFF) 00268 #define TC5_SR (TC5_BASE + TC_SR_OFF) 00270 #define TC_IER_OFF 0x24 00272 #define TC0_IER (TC0_BASE + TC_IER_OFF) 00273 #define TC1_IER (TC1_BASE + TC_IER_OFF) 00274 #define TC2_IER (TC2_BASE + TC_IER_OFF) 00275 #define TC3_IER (TC3_BASE + TC_IER_OFF) 00276 #define TC4_IER (TC4_BASE + TC_IER_OFF) 00277 #define TC5_IER (TC5_BASE + TC_IER_OFF) 00279 #define TC_IDR_OFF 0x28 00281 #define TC0_IDR (TC0_BASE + TC_IDR_OFF) 00282 #define TC1_IDR (TC1_BASE + TC_IDR_OFF) 00283 #define TC2_IDR (TC2_BASE + TC_IDR_OFF) 00284 #define TC3_IDR (TC3_BASE + TC_IDR_OFF) 00285 #define TC4_IDR (TC4_BASE + TC_IDR_OFF) 00286 #define TC5_IDR (TC5_BASE + TC_IDR_OFF) 00288 #define TC_IMR_OFF 0x2C 00290 #define TC0_IMR (TC0_BASE + TC_IMR_OFF) 00291 #define TC1_IMR (TC1_BASE + TC_IMR_OFF) 00292 #define TC2_IMR (TC2_BASE + TC_IMR_OFF) 00293 #define TC3_IMR (TC3_BASE + TC_IMR_OFF) 00294 #define TC4_IMR (TC4_BASE + TC_IMR_OFF) 00295 #define TC5_IMR (TC5_BASE + TC_IMR_OFF) 00297 #define TC_COVFS 0x00000001 00298 #define TC_LOVRS 0x00000002 00299 #define TC_CPAS 0x00000004 00300 #define TC_CPBS 0x00000008 00301 #define TC_CPCS 0x00000010 00302 #define TC_LDRAS 0x00000020 00303 #define TC_LDRBS 0x00000040 00304 #define TC_ETRGS 0x00000080 00305 #define TC_CLKSTA 0x00010000 00306 #define TC_MTIOA 0x00020000 00307 #define TC_MTIOB 0x00040000 00309 00310 00312 #define TC_BCR_OFF 0xC0 00314 #define TC_BKL0_CR (TC_BASE + TC_BCR_OFF) 00315 #define TC_BCR TC_BKL0_CR 00316 #define TC_BKL1_CR (TC_BLK1_BASE + TC_BCR_OFF) 00318 #define TC_SYNC 0x00000001 00320 00321 00323 #define TC_BMR_OFF 0xC4 00325 #define TC_BLK0_MR (TC_BASE + TC_BMR_OFF) 00326 #define TC_BMR TC_BKL0_MR 00327 #define TC_BLK1_MR (TC_BLK1_BASE + TC_BMR_OFF) 00329 #define TC_TC0XC0S 0x00000003 00330 #define TC_TCLK0XC0 0x00000000 00331 #define TC_NONEXC0 0x00000001 00332 #define TC_TIOA1XC0 0x00000002 00333 #define TC_TIOA2XC0 0x00000003 00335 #define TC_TC1XC1S 0x0000000C 00336 #define TC_TCLK1XC1 0x00000000 00337 #define TC_NONEXC1 0x00000004 00338 #define TC_TIOA0XC1 0x00000008 00339 #define TC_TIOA2XC1 0x0000000C 00341 #define TC_TC2XC2S 0x00000030 00342 #define TC_TCLK2XC2 0x00000000 00343 #define TC_NONEXC2 0x00000010 00344 #define TC_TIOA0XC2 0x00000020 00345 #define TC_TIOA1XC2 0x00000030 00347 00348 00350 #endif /* _ARCH_ARM_AT91_TC_H_ */