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Nut/OS
4.10.3
API Reference
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Nut/OS
4.10.3
API Reference
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00001 #ifndef _ARCH_ARM_AT91_US_H_ 00002 #define _ARCH_ARM_AT91_US_H_ 00003 00004 /* 00005 * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved. 00006 * 00007 * Redistribution and use in source and binary forms, with or without 00008 * modification, are permitted provided that the following conditions 00009 * are met: 00010 * 00011 * 1. Redistributions of source code must retain the above copyright 00012 * notice, this list of conditions and the following disclaimer. 00013 * 2. Redistributions in binary form must reproduce the above copyright 00014 * notice, this list of conditions and the following disclaimer in the 00015 * documentation and/or other materials provided with the distribution. 00016 * 3. Neither the name of the copyright holders nor the names of 00017 * contributors may be used to endorse or promote products derived 00018 * from this software without specific prior written permission. 00019 * 00020 * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS 00021 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 00022 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 00023 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE 00024 * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 00025 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 00026 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 00027 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 00028 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00029 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 00030 * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 00031 * SUCH DAMAGE. 00032 * 00033 * For additional information see http://www.ethernut.de/ 00034 */ 00035 00066 00069 #define US_CR_OFF 0x00000000 00070 #define US0_CR (USART0_BASE + US_CR_OFF) 00071 #define US1_CR (USART1_BASE + US_CR_OFF) 00072 #define US_RSTRX 0x00000004 00073 #define US_RSTTX 0x00000008 00074 #define US_RXEN 0x00000010 00075 #define US_RXDIS 0x00000020 00076 #define US_TXEN 0x00000040 00077 #define US_TXDIS 0x00000080 00078 #define US_RSTSTA 0x00000100 00079 #define US_STTBRK 0x00000200 00080 #define US_STPBRK 0x00000400 00081 #define US_STTTO 0x00000800 00082 #define US_SENDA 0x00001000 00084 #if defined(USART_HAS_MODE) 00085 #define US_RSTIT 0x00002000 00086 #define US_RSTNACK 0x00004000 00087 #define US_RETTO 0x00008000 00088 #define US_DTREN 0x00010000 00089 #define US_DTRDIS 0x00020000 00090 #define US_RTSEN 0x00040000 00091 #define US_RTSDIS 0x00080000 00092 #endif /* USART_HAS_MODE */ 00093 00097 #define US_MR_OFF 0x00000004 00098 #define US0_MR (USART0_BASE + US_MR_OFF) 00099 #define US1_MR (USART1_BASE + US_MR_OFF) 00101 #if defined(USART_HAS_MODE) 00102 #define US_MODE 0x0000000F 00103 #define US_MODE_RS485 0x00000001 00104 #define US_MODE_HWHANDSHAKE 0x00000002 00105 #define US_MODE_MODEM 0x00000003 00106 #define US_MODE_ISO7816_T0 0x00000004 00107 #define US_MODE_ISO7816_T1 0x00000006 00108 #define US_MODE_IRDA 0x00000008 00109 #endif /* USART_HAS_MODE */ 00110 00111 #define US_CLKS 0x00000030 00112 #define US_CLKS_MCK 0x00000000 00113 #define US_CLKS_MCK8 0x00000010 00114 #define US_CLKS_SCK 0x00000020 00115 #define US_CLKS_SLCK 0x00000030 00117 #define US_CHRL 0x000000C0 00118 #define US_CHRL_5 0x00000000 00119 #define US_CHRL_6 0x00000040 00120 #define US_CHRL_7 0x00000080 00121 #define US_CHRL_8 0x000000C0 00123 #define US_SYNC 0x00000100 00125 #define US_PAR 0x00000E00 00126 #define US_PAR_EVEN 0x00000000 00127 #define US_PAR_ODD 0x00000200 00128 #define US_PAR_SPACE 0x00000400 00129 #define US_PAR_MARK 0x00000600 00130 #define US_PAR_NO 0x00000800 00131 #define US_PAR_MULTIDROP 0x00000C00 00133 #define US_NBSTOP 0x00003000 00134 #define US_NBSTOP_1 0x00000000 00135 #define US_NBSTOP_1_5 0x00001000 00136 #define US_NBSTOP_2 0x00002000 00138 #define US_CHMODE 0x0000C000 00139 #define US_CHMODE_NORMAL 0x00000000 00140 #define US_CHMODE_AUTOMATIC_ECHO 0x00004000 00141 #define US_CHMODE_LOCAL_LOOPBACK 0x00008000 00142 #define US_CHMODE_REMOTE_LOOPBACK 0x0000C000 00144 #define US_MODE9 0x00020000 00146 #define US_CLKO 0x00040000 00148 00149 00151 #define US_CSR_OFF 0x00000014 00152 #define US0_CSR (USART0_BASE + US_CSR_OFF) 00153 #define US1_CSR (USART1_BASE + US_CSR_OFF) 00155 #define US_IER_OFF 0x00000008 00156 #define US0_IER (USART0_BASE + US_IER_OFF) 00157 #define US1_IER (USART1_BASE + US_IER_OFF) 00159 #define US_IDR_OFF 0x0000000C 00160 #define US0_IDR (USART0_BASE + US_IDR_OFF) 00161 #define US1_IDR (USART1_BASE + US_IDR_OFF) 00163 #define US_IMR_OFF 0x00000010 00164 #define US0_IMR (USART0_BASE + US_IMR_OFF) 00165 #define US1_IMR (USART1_BASE + US_IMR_OFF) 00167 #define US_RXRDY 0x00000001 00168 #define US_TXRDY 0x00000002 00169 #define US_RXBRK 0x00000004 00170 #define US_ENDRX 0x00000008 00171 #define US_ENDTX 0x00000010 00172 #define US_OVRE 0x00000020 00173 #define US_FRAME 0x00000040 00174 #define US_PARE 0x00000080 00175 #define US_TIMEOUT 0x00000100 00176 #define US_TXEMPTY 0x00000200 00177 #define US_RXBUFF 0x00001000 00179 #if defined(USART_HAS_MODE) 00180 #define US_ITERATION 0x00000400 00181 #define US_NACK 0x00002000 00182 #define US_RIIC 0x00010000 00183 #define US_DSRIC 0x00020000 00184 #define US_DCDIC 0x00040000 00185 #define US_CTSIC 0x00080000 00186 #define US_RI 0x00100000 00187 #define US_DSR 0x00200000 00188 #define US_DCD 0x00400000 00189 #define US_CTS 0x00800000 00190 #endif /* USART_HAS_MODE */ 00191 00196 #define AT91_US_BAUD(baud) ((NUT_CPU_FREQ / (8 * (baud)) + 1) / 2) 00197 00201 #define US_RHR_OFF 0x00000018 00202 #define US0_RHR (USART0_BASE + US_RHR_OFF) 00203 #define US1_RHR (USART1_BASE + US_RHR_OFF) 00205 00206 00208 #define US_THR_OFF 0x0000001C 00209 #define US0_THR (USART0_BASE + US_THR_OFF) 00210 #define US1_THR (USART1_BASE + US_THR_OFF) 00212 00213 00215 #define US_BRGR_OFF 0x00000020 00216 #define US0_BRGR (USART0_BASE + US_BRGR_OFF) 00217 #define US1_BRGR (USART1_BASE + US_BRGR_OFF) 00219 00220 00222 #define US_RTOR_OFF 0x00000024 00223 #define US0_RTOR (USART0_BASE + US_RTOR_OFF) 00224 #define US1_RTOR (USART1_BASE + US_RTOR_OFF) 00226 00227 00229 #define US_TTGR_OFF 0x00000028 00230 #define US0_TTGR (USART0_BASE + US_TTGR_OFF) 00231 #define US1_TTGR (USART1_BASE + US_TTGR_OFF) 00233 00234 00236 #define US_FIDI_OFF 0x00000040 00237 #define US0_FIDI (USART0_BASE + US_FIDI_OFF) 00238 #define US1_FIDI (USART1_BASE + US_FIDI_OFF) 00240 00241 00243 #define US_NER_OFF 0x00000044 00244 #define US0_NER (USART0_BASE + US_NER_OFF) 00245 #define US1_NER (USART1_BASE + US_NER_OFF) 00247 00248 00250 #define US_IF_OFF 0x0000004C 00251 #define US0_IF (USART0_BASE + US_IF_OFF) 00252 #define US1_IF (USART1_BASE + US_IF_OFF) 00254 00255 #if defined(USART_HAS_PDC) 00256 00259 #define US0_RPR (USART0_BASE + PERIPH_RPR_OFF) 00260 #define US1_RPR (USART1_BASE + PERIPH_RPR_OFF) 00262 00263 00265 #define US0_RCR (USART0_BASE + PERIPH_RCR_OFF) 00266 #define US1_RCR (USART1_BASE + PERIPH_RCR_OFF) 00268 00269 00271 #define US0_TPR (USART0_BASE + PERIPH_TPR_OFF) 00272 #define US1_TPR (USART1_BASE + PERIPH_TPR_OFF) 00274 00275 00277 #define US0_TCR (USART0_BASE + PERIPH_TCR_OFF) 00278 #define US1_TCR (USART1_BASE + PERIPH_TCR_OFF) 00280 00281 #if defined(PERIPH_RNPR_OFF) && defined(PERIPH_RNCR_OFF) 00282 #define US0_RNPR (USART0_BASE + PERIPH_RNPR_OFF) 00283 #define US1_RNPR (USART1_BASE + PERIPH_RNPR_OFF) 00284 #define US0_RNCR (USART0_BASE + PERIPH_RNCR_OFF) 00285 #define US1_RNCR (USART1_BASE + PERIPH_RNCR_OFF) 00286 #endif 00287 00288 #if defined(PERIPH_TNPR_OFF) && defined(PERIPH_TNCR_OFF) 00289 #define US0_TNPR (USART0_BASE + PERIPH_TNPR_OFF) 00290 #define US1_TNPR (USART1_BASE + PERIPH_TNPR_OFF) 00291 #define US0_TNCR (USART0_BASE + PERIPH_TNCR_OFF) 00292 #define US1_TNCR (USART1_BASE + PERIPH_TNCR_OFF) 00293 #endif 00294 00295 #if defined(PERIPH_PTCR_OFF) 00296 #define US0_PTCR (USART0_BASE + PERIPH_PTCR_OFF) 00297 #define US1_PTCR (USART1_BASE + PERIPH_PTCR_OFF) 00298 #endif 00299 00300 #if defined(PERIPH_PTSR_OFF) 00301 #define US0_PTSR (USART0_BASE + PERIPH_PTSR_OFF) 00302 #define US1_PTSR (USART1_BASE + PERIPH_PTSR_OFF) 00303 #endif 00304 00305 #endif /* USART_HAS_PDC */ 00306 00310 #endif /* _ARCH_ARM_AT91_US_H_ */