Nut/OS  4.10.3
API Reference
ih_timer0_comp.c
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00001 /*
00002  * Copyright (C) 2001-2005 by egnite Software GmbH. All rights reserved.
00003  *
00004  * Redistribution and use in source and binary forms, with or without
00005  * modification, are permitted provided that the following conditions
00006  * are met:
00007  *
00008  * 1. Redistributions of source code must retain the above copyright
00009  *    notice, this list of conditions and the following disclaimer.
00010  * 2. Redistributions in binary form must reproduce the above copyright
00011  *    notice, this list of conditions and the following disclaimer in the
00012  *    documentation and/or other materials provided with the distribution.
00013  * 3. Neither the name of the copyright holders nor the names of
00014  *    contributors may be used to endorse or promote products derived
00015  *    from this software without specific prior written permission.
00016  *
00017  * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
00018  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00019  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00020  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
00021  * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
00022  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
00023  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
00024  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
00025  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00026  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
00027  * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
00028  * SUCH DAMAGE.
00029  *
00030  * For additional information see http://www.ethernut.de/
00031  *
00032  */
00033 
00088 #include <dev/irqreg.h>
00089 
00090 #if defined(MCU_AT90CAN128) || defined(MCU_ATMEGA2560) || defined(MCU_ATMEGA2561)
00091 #define INT_MASK_REG    TIMSK0
00092 #define INT_STATUS_REG  TIFR0
00093 #define INT_ENABLE_BIT  OCIE0A
00094 #define INT_STATUS_BIT  OCF0A
00095 #define INT_PRIORITY    15 /* MOVED IN CAN128 */
00096 #else
00097 #define INT_MASK_REG    TIMSK
00098 #define INT_STATUS_REG  TIFR
00099 #define INT_ENABLE_BIT  OCIE0
00100 #define INT_STATUS_BIT  OCF0
00101 #define INT_PRIORITY    14
00102 #endif
00103 
00108 
00109 static int AvrTimer0CompIrqCtl(int cmd, void *param);
00110 
00111 IRQ_HANDLER sig_OUTPUT_COMPARE0 = {
00112 #ifdef NUT_PERFMON
00113     0,                          /* Interrupt counter, ir_count. */
00114 #endif
00115     NULL,                       /* Passed argument, ir_arg. */
00116     NULL,                       /* Handler subroutine, ir_handler. */
00117     AvrTimer0CompIrqCtl         /* Interrupt control, ir_ctl. */
00118 };
00119 
00135 static int AvrTimer0CompIrqCtl(int cmd, void *param)
00136 {
00137     int rc = 0;
00138     unsigned int *ival = (unsigned int *) param;
00139     int_fast8_t enabled = bit_is_set(INT_MASK_REG, INT_ENABLE_BIT);
00140 
00141     /* Disable interrupt. */
00142     cbi(INT_MASK_REG, INT_ENABLE_BIT);
00143 
00144     switch (cmd) {
00145     case NUT_IRQCTL_INIT:
00146         enabled = 0;
00147     case NUT_IRQCTL_CLEAR:
00148         /* Clear any pending interrupt. */
00149         outb(INT_STATUS_REG, _BV(INT_STATUS_BIT));
00150         break;
00151     case NUT_IRQCTL_STATUS:
00152         if (bit_is_set(INT_STATUS_REG, INT_STATUS_BIT)) {
00153             *ival = 1;
00154         } else {
00155             *ival = 0;
00156         }
00157         if (enabled) {
00158             *ival |= 0x80;
00159         }
00160         break;
00161     case NUT_IRQCTL_ENABLE:
00162         enabled = 1;
00163         break;
00164     case NUT_IRQCTL_DISABLE:
00165         enabled = 0;
00166         break;
00167     case NUT_IRQCTL_GETPRIO:
00168         *ival = INT_PRIORITY;
00169         break;
00170 #ifdef NUT_PERFMON
00171     case NUT_IRQCTL_GETCOUNT:
00172         *ival = (unsigned int) sig_OUTPUT_COMPARE0.ir_count;
00173         sig_OUTPUT_COMPARE0.ir_count = 0;
00174         break;
00175 #endif
00176     default:
00177         rc = -1;
00178         break;
00179     }
00180 
00181     /* Enable interrupt. */
00182     if (enabled) {
00183         sbi(INT_MASK_REG, INT_ENABLE_BIT);
00184     }
00185     return rc;
00186 }
00187 
00191 #ifdef __IMAGECRAFT__
00192 #if defined( ATMega2560 ) || defined( ATMega2561 )
00193 #pragma interrupt_handler SIG_OUTPUT_COMPARE0:iv_TIMER0_COMPA
00194 #else
00195 #pragma interrupt_handler SIG_OUTPUT_COMPARE0:iv_TIMER0_COMP
00196 #endif
00197 NUTSIGNAL(SIG_OUTPUT_COMPARE0, sig_OUTPUT_COMPARE0)
00198 #else
00199 #if defined(MCU_ATMEGA2560) || defined(MCU_ATMEGA2561)
00200 NUTSIGNAL(SIG_OUTPUT_COMPARE0A, sig_OUTPUT_COMPARE0)
00201 #else
00202 NUTSIGNAL(SIG_OUTPUT_COMPARE0, sig_OUTPUT_COMPARE0)
00203 #endif
00204 #endif
00205 
00206