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00041 #include <arch/avr32.h>
00042 #include <dev/irqreg.h>
00043 #include <avr32/io.h>
00044
00045 #include <arch/avr32/ihndlr.h>
00046
00047 #ifndef NUT_IRQPRI_UART0
00048 #define NUT_IRQPRI_UART0 AVR32_INTC_INT3
00049 #endif
00050
00051 static int Uart0IrqCtl(int cmd, void *param);
00052
00053 IRQ_HANDLER sig_UART0 = {
00054 #ifdef NUT_PERFMON
00055 0,
00056 #endif
00057 NULL,
00058 NULL,
00059 Uart0IrqCtl
00060 };
00061
00065 SIGNAL(Uart0IrqEntry)
00066 {
00067 IRQ_ENTRY();
00068 #ifdef NUT_PERFMON
00069 sig_UART0.ir_count++;
00070 #endif
00071 if (sig_UART0.ir_handler) {
00072 (sig_UART0.ir_handler) (sig_UART0.ir_arg);
00073 }
00074 IRQ_EXIT();
00075 }
00076
00091 static int Uart0IrqCtl(int cmd, void *param)
00092 {
00093 int rc = 0;
00094 unsigned int *ival = (unsigned int *) param;
00095 ureg_t imr = AVR32_USART0.imr;
00096 static ureg_t enabledIMR = 0;
00097 int_fast8_t enabled = imr;
00098
00099
00100 if (enabled) {
00101 AVR32_USART0.idr = 0xFFFFFFFF;
00102 AVR32_USART0.csr;
00103 enabledIMR = imr;
00104 }
00105
00106 switch (cmd) {
00107 case NUT_IRQCTL_INIT:
00108
00109 register_interrupt(Uart0IrqEntry, AVR32_USART0_IRQ, NUT_IRQPRI_UART0);
00110
00111 break;
00112 case NUT_IRQCTL_STATUS:
00113 if (enabled) {
00114 *ival |= 1;
00115 } else {
00116 *ival &= ~1;
00117 }
00118 break;
00119 case NUT_IRQCTL_ENABLE:
00120 enabled = 1;
00121 if (*ival)
00122 imr = *ival;
00123 break;
00124 case NUT_IRQCTL_DISABLE:
00125 enabled = 0;
00126 break;
00127 case NUT_IRQCTL_GETPRIO:
00128 *ival = NUT_IRQPRI_UART0;
00129 break;
00130 #ifdef NUT_PERFMON
00131 case NUT_IRQCTL_GETCOUNT:
00132 *ival = (unsigned int) sig_UART0.ir_count;
00133 sig_UART0.ir_count = 0;
00134 break;
00135 #endif
00136 default:
00137 rc = -1;
00138 break;
00139 }
00140
00141
00142 if (enabled) {
00143 AVR32_USART0.ier = enabledIMR;
00144 AVR32_USART0.csr;
00145 }
00146 return rc;
00147 }