rtlregs.h

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#ifndef _DEV_RTLREGS_H_
#define _DEV_RTLREGS_H_

/*
 * Copyright (C) 2001-2003 by egnite Software GmbH. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the name of the copyright holders nor the names of
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
 * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
 * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 * For additional information see http://www.ethernut.de/
 *
 */

/*
 * $Log$
 * Revision 1.1  2005/07/26 18:02:40  haraldkipp
 * Moved from dev.
 *
 * Revision 1.1.1.1  2003/05/09 14:40:49  haraldkipp
 * Initial using 3.2.1
 *
 * Revision 1.7  2003/02/04 17:50:54  harald
 * Version 3 released
 *
 * Revision 1.6  2002/10/29 15:27:36  harald
 * *** empty log message ***
 *
 * Revision 1.5  2002/06/26 17:29:08  harald
 * First pre-release with 2.4 stack
 *
 */


/*
 * Register offset applicable to all register pages.
 */
#define NIC_CR 0x00        
#define NIC_IOPORT 0x10    
#define NIC_RESET 0x1f     
/*
 * Page 0 register offsets.
 */
#define NIC_PG0_CLDA0 0x01    
#define NIC_PG0_PSTART 0x01   
#define NIC_PG0_CLDA1 0x02    
#define NIC_PG0_PSTOP 0x02    
#define NIC_PG0_BNRY 0x03     
#define NIC_PG0_TSR 0x04      
#define NIC_PG0_TPSR 0x04     
#define NIC_PG0_NCR 0x05      
#define NIC_PG0_TBCR0 0x05    
#define NIC_PG0_FIFO 0x06     
#define NIC_PG0_TBCR1 0x06    
#define NIC_PG0_ISR 0x07      
#define NIC_PG0_CRDA0 0x08    
#define NIC_PG0_RSAR0 0x08    
#define NIC_PG0_CRDA1 0x09    
#define NIC_PG0_RSAR1 0x09    
#define NIC_PG0_RBCR0 0x0a    
#define NIC_PG0_RBCR1 0x0b    
#define NIC_PG0_RSR 0x0c      
#define NIC_PG0_RCR 0x0c      
#define NIC_PG0_CNTR0 0x0d    
#define NIC_PG0_TCR 0x0d      
#define NIC_PG0_CNTR1 0x0e    
#define NIC_PG0_DCR 0x0e      
#define NIC_PG0_CNTR2 0x0f    
#define NIC_PG0_IMR 0x0f      
/*
 * Page 1 register offsets.
 */
#define NIC_PG1_PAR0 0x01     
#define NIC_PG1_PAR1 0x02     
#define NIC_PG1_PAR2 0x03     
#define NIC_PG1_PAR3 0x04     
#define NIC_PG1_PAR4 0x05     
#define NIC_PG1_PAR5 0x06     
#define NIC_PG1_CURR 0x07     
#define NIC_PG1_MAR0 0x08     
#define NIC_PG1_MAR1 0x09     
#define NIC_PG1_MAR2 0x0a     
#define NIC_PG1_MAR3 0x0b     
#define NIC_PG1_MAR4 0x0c     
#define NIC_PG1_MAR5 0x0d     
#define NIC_PG1_MAR6 0x0e     
#define NIC_PG1_MAR7 0x0f     
/*
 * Page 2 register offsets.
 */
#define NIC_PG2_PSTART 0x01   
#define NIC_PG2_CLDA0 0x01    
#define NIC_PG2_PSTOP 0x02    
#define NIC_PG2_CLDA1 0x02    
#define NIC_PG2_RNP 0x03      
#define NIC_PG2_TSPR 0x04     
#define NIC_PG2_LNP 0x05      
#define NIC_PG2_ACU 0x06      
#define NIC_PG2_ACL 0x07      
#define NIC_PG2_RCR 0x0c      
#define NIC_PG2_TCR 0x0d      
#define NIC_PG2_DCR 0x0e      
#define NIC_PG2_IMR 0x0f      
/*
 * Page 3 register offsets.
 */
#define NIC_PG3_EECR     0x01    
#define NIC_PG3_BPAGE    0x02    
#define NIC_PG3_CONFIG0  0x03    
#define NIC_PG3_CONFIG1  0x04    
#define NIC_PG3_CONFIG2  0x05    
#define NIC_PG3_CONFIG3  0x06    
#define NIC_PG3_CSNSAV   0x08    
#define NIC_PG3_HLTCLK   0x09    
#define NIC_PG3_INTR     0x0b    
/*
 * Command register bits.
 */
#define NIC_CR_STP 0x01    
#define NIC_CR_STA 0x02    
#define NIC_CR_TXP 0x04    
#define NIC_CR_RD0 0x08    
#define NIC_CR_RD1 0x10    
#define NIC_CR_RD2 0x20    
#define NIC_CR_PS0 0x40    
#define NIC_CR_PS1 0x80    
/*
 * Interrupt status register bits.
 */
#define NIC_ISR_PRX 0x01      
#define NIC_ISR_PTX 0x02      
#define NIC_ISR_RXE 0x04      
#define NIC_ISR_TXE 0x08      
#define NIC_ISR_OVW 0x10      
#define NIC_ISR_CNT 0x20      
#define NIC_ISR_RDC 0x40      
#define NIC_ISR_RST 0x80      
/*
 * Interrupt mask register bits.
 */
#define NIC_IMR_PRXE 0x01     
#define NIC_IMR_PTXE 0x02     
#define NIC_IMR_RXEE 0x04     
#define NIC_IMR_TXEE 0x08     
#define NIC_IMR_OVWE 0x10     
#define NIC_IMR_CNTE 0x20     
#define NIC_IMR_RCDE 0x40     
/*
 * Data configuration register bits.
 */
#define NIC_DCR_WTS 0x01      
#define NIC_DCR_BOS 0x02      
#define NIC_DCR_LAS 0x04      
#define NIC_DCR_LS 0x08       
#define NIC_DCR_AR 0x10       
#define NIC_DCR_FT0 0x20      
#define NIC_DCR_FT1 0x40      
/*
 * Transmit configuration register bits.
 */
#define NIC_TCR_CRC 0x01      
#define NIC_TCR_LB0 0x02      
#define NIC_TCR_LB1 0x04      
#define NIC_TCR_ATD 0x08      
#define NIC_TCR_OFST 0x10     
/*
 * Transmit status register bits.
 */
#define NIC_TSR_PTX 0x01      
#define NIC_TSR_COL 0x04      
#define NIC_TSR_ABT 0x08      
#define NIC_TSR_CRS 0x10      
#define NIC_TSR_FU 0x20       
#define NIC_TSR_CDH 0x40      
#define NIC_TSR_OWC 0x80      
/*
 * Receive configuration register bits.
 */
#define NIC_RCR_SEP 0x01      
#define NIC_RCR_AR 0x02       
#define NIC_RCR_AB 0x04       
#define NIC_RCR_AM 0x08       
#define NIC_RCR_PRO 0x10      
#define NIC_RCR_MON 0x20      
/*
 * Receive status register bits.
 */
#define NIC_RSR_PRX 0x01      
#define NIC_RSR_CRC 0x02      
#define NIC_RSR_FAE 0x04      
#define NIC_RSR_FO 0x08       
#define NIC_RSR_MPA 0x10      
#define NIC_RSR_PHY 0x20      
#define NIC_RSR_DIS 0x40      
#define NIC_RSR_DFR 0x80      
/*
 * EEPROM command register bits.
 */
#define NIC_EECR_EEM1  0x80    
#define NIC_EECR_EEM0  0x40    
#define NIC_EECR_EECS  0x08    
#define NIC_EECR_EESK  0x04    
#define NIC_EECR_EEDI  0x02    
#define NIC_EECR_EEDO  0x01    
/*
 * Configuration register 2 bits.
 */
#define NIC_CONFIG2_PL1   0x80 
#define NIC_CONFIG2_PL0   0x40 
#define NIC_CONFIG2_BSELB 0x20 
#define NIC_CONFIG2_BS4   0x10 
#define NIC_CONFIG2_BS3   0x08
#define NIC_CONFIG2_BS2   0x04
#define NIC_CONFIG2_BS1   0x02
#define NIC_CONFIG2_BS0   0x01

/*
 * Configuration register 3 bits
 */
#define NIC_CONFIG3_PNP     0x80 
#define NIC_CONFIG3_FUDUP   0x40 
#define NIC_CONFIG3_LEDS1   0x20 
#define NIC_CONFIG3_LEDS0   0x10 
#define NIC_CONFIG3_SLEEP   0x04 
#define NIC_CONFIG3_PWRDN   0x02 
#define NIC_CONFIG3_ACTIVEB 0x01 


#define nic_read(reg) *(base + (reg))

#define nic_write(reg, data) *(base + (reg)) = data

#endif