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Nut/OS
4.10.3
API Reference
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Nut/OS
4.10.3
API Reference
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00001 #ifndef _DEV_SBBI2F_H_ 00002 #define _DEV_SBBI2F_H_ 00003 /* 00004 * Copyright (C) 2007 by egnite Software GmbH. All rights reserved. 00005 * 00006 * Redistribution and use in source and binary forms, with or without 00007 * modification, are permitted provided that the following conditions 00008 * are met: 00009 * 00010 * 1. Redistributions of source code must retain the above copyright 00011 * notice, this list of conditions and the following disclaimer. 00012 * 2. Redistributions in binary form must reproduce the above copyright 00013 * notice, this list of conditions and the following disclaimer in the 00014 * documentation and/or other materials provided with the distribution. 00015 * 3. Neither the name of the copyright holders nor the names of 00016 * contributors may be used to endorse or promote products derived 00017 * from this software without specific prior written permission. 00018 * 00019 * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS 00020 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 00021 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 00022 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE 00023 * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 00024 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 00025 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 00026 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 00027 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00028 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 00029 * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 00030 * SUCH DAMAGE. 00031 * 00032 * For additional information see http://www.ethernut.de/ 00033 */ 00034 00055 #include <cfg/arch/gpio.h> 00056 00060 #ifndef SBBI2_MAX_DEVICES 00061 #define SBBI2_MAX_DEVICES 4 00062 #endif 00063 00064 #if defined(__AVR__) /* MCU */ 00065 /* 00066 * AVR implementation. 00067 * ====================================== 00068 */ 00069 00070 #ifdef SBBI2_CS0_BIT 00071 00072 #if (SBBI2_CS0_PORT == AVRPORTB) 00073 #define SBBI2_CS0_SOD_REG PORTB 00074 #define SBBI2_CS0_OE_REG DDRB 00075 #elif (SBBI2_CS0_PORT == AVRPORTD) 00076 #define SBBI2_CS0_SOD_REG PORTD 00077 #define SBBI2_CS0_OE_REG DDRD 00078 #elif (SBBI2_CS0_PORT == AVRPORTE) 00079 #define SBBI2_CS0_SOD_REG PORTE 00080 #define SBBI2_CS0_OE_REG DDRE 00081 #elif (SBBI2_CS0_PORT == AVRPORTF) 00082 #define SBBI2_CS0_SOD_REG PORTF 00083 #define SBBI2_CS0_OE_REG DDRF 00084 #elif (SBBI2_CS0_PORT == AVRPORTG) 00085 #define SBBI2_CS0_SOD_REG PORTG 00086 #define SBBI2_CS0_OE_REG DDRG 00087 #elif (SBBI2_CS0_PORT == AVRPORTH) 00088 #define SBBI2_CS0_SOD_REG PORTH 00089 #define SBBI2_CS0_OE_REG DDRH 00090 #endif 00091 00093 #define SBBI2_CS0_ENA() sbi(SBBI2_CS0_OE_REG, SBBI2_CS0_BIT) 00094 00095 #define SBBI2_CS0_CLR() cbi(SBBI2_CS0_SOD_REG, SBBI2_CS0_BIT) 00096 00097 #define SBBI2_CS0_SET() sbi(SBBI2_CS0_SOD_REG, SBBI2_CS0_BIT) 00098 00099 #endif /* SBBI2_CS0_BIT */ 00100 00101 #ifdef SBBI2_CS1_BIT 00102 00103 #if (SBBI2_CS1_PORT == AVRPORTB) 00104 #define SBBI2_CS1_SOD_REG PORTB 00105 #define SBBI2_CS1_OE_REG DDRB 00106 #elif (SBBI2_CS1_PORT == AVRPORTD) 00107 #define SBBI2_CS1_SOD_REG PORTD 00108 #define SBBI2_CS1_OE_REG DDRD 00109 #elif (SBBI2_CS1_PORT == AVRPORTE) 00110 #define SBBI2_CS1_SOD_REG PORTE 00111 #define SBBI2_CS1_OE_REG DDRE 00112 #elif (SBBI2_CS1_PORT == AVRPORTF) 00113 #define SBBI2_CS1_SOD_REG PORTF 00114 #define SBBI2_CS1_OE_REG DDRF 00115 #elif (SBBI2_CS1_PORT == AVRPORTG) 00116 #define SBBI2_CS1_SOD_REG PORTG 00117 #define SBBI2_CS1_OE_REG DDRG 00118 #elif (SBBI2_CS1_PORT == AVRPORTH) 00119 #define SBBI2_CS1_SOD_REG PORTH 00120 #define SBBI2_CS1_OE_REG DDRH 00121 #endif 00122 00124 #define SBBI2_CS1_ENA() sbi(SBBI2_CS1_OE_REG, SBBI2_CS1_BIT) 00125 00126 #define SBBI2_CS1_CLR() cbi(SBBI2_CS1_SOD_REG, SBBI2_CS1_BIT) 00127 00128 #define SBBI2_CS1_SET() sbi(SBBI2_CS1_SOD_REG, SBBI2_CS1_BIT) 00129 00130 #endif /* SBBI2_CS1_BIT */ 00131 00132 #ifdef SBBI2_CS2_BIT 00133 00134 #if (SBBI2_CS2_PORT == AVRPORTB) 00135 #define SBBI2_CS2_SOD_REG PORTB 00136 #define SBBI2_CS2_OE_REG DDRB 00137 #elif (SBBI2_CS2_PORT == AVRPORTD) 00138 #define SBBI2_CS2_SOD_REG PORTD 00139 #define SBBI2_CS2_OE_REG DDRD 00140 #elif (SBBI2_CS2_PORT == AVRPORTE) 00141 #define SBBI2_CS2_SOD_REG PORTE 00142 #define SBBI2_CS2_OE_REG DDRE 00143 #elif (SBBI2_CS2_PORT == AVRPORTF) 00144 #define SBBI2_CS2_SOD_REG PORTF 00145 #define SBBI2_CS2_OE_REG DDRF 00146 #elif (SBBI2_CS2_PORT == AVRPORTG) 00147 #define SBBI2_CS2_SOD_REG PORTG 00148 #define SBBI2_CS2_OE_REG DDRG 00149 #elif (SBBI2_CS2_PORT == AVRPORTH) 00150 #define SBBI2_CS2_SOD_REG PORTH 00151 #define SBBI2_CS2_OE_REG DDRH 00152 #endif 00153 00155 #define SBBI2_CS2_ENA() sbi(SBBI2_CS2_OE_REG, SBBI2_CS2_BIT) 00156 00157 #define SBBI2_CS2_CLR() cbi(SBBI2_CS2_SOD_REG, SBBI2_CS2_BIT) 00158 00159 #define SBBI2_CS2_SET() sbi(SBBI2_CS2_SOD_REG, SBBI2_CS2_BIT) 00160 00161 #endif /* SBBI2_CS2_BIT */ 00162 00163 #ifdef SBBI2_CS3_BIT 00164 00165 #if (SBBI2_CS3_PORT == AVRPORTB) 00166 #define SBBI2_CS3_SOD_REG PORTB 00167 #define SBBI2_CS3_OE_REG DDRB 00168 #elif (SBBI2_CS3_PORT == AVRPORTD) 00169 #define SBBI2_CS3_SOD_REG PORTD 00170 #define SBBI2_CS3_OE_REG DDRD 00171 #elif (SBBI2_CS3_PORT == AVRPORTE) 00172 #define SBBI2_CS3_SOD_REG PORTE 00173 #define SBBI2_CS3_OE_REG DDRE 00174 #elif (SBBI2_CS3_PORT == AVRPORTF) 00175 #define SBBI2_CS3_SOD_REG PORTF 00176 #define SBBI2_CS3_OE_REG DDRF 00177 #elif (SBBI2_CS3_PORT == AVRPORTG) 00178 #define SBBI2_CS3_SOD_REG PORTG 00179 #define SBBI2_CS3_OE_REG DDRG 00180 #elif (SBBI2_CS3_PORT == AVRPORTH) 00181 #define SBBI2_CS3_SOD_REG PORTH 00182 #define SBBI2_CS3_OE_REG DDRH 00183 #endif 00184 00186 #define SBBI2_CS3_ENA() sbi(SBBI2_CS3_OE_REG, SBBI2_CS3_BIT) 00187 00188 #define SBBI2_CS3_CLR() cbi(SBBI2_CS3_SOD_REG, SBBI2_CS3_BIT) 00189 00190 #define SBBI2_CS3_SET() sbi(SBBI2_CS3_SOD_REG, SBBI2_CS3_BIT) 00191 00192 #endif /* SBBI2_CS3_BIT */ 00193 00194 #ifdef SBBI2_RST0_BIT 00195 00196 #if (SBBI2_RST0_PORT == AVRPORTB) 00197 #define SBBI2_RST0_SOD_REG PORTB 00198 #define SBBI2_RST0_OE_REG DDRB 00199 #elif (SBBI2_RST0_PORT == AVRPORTD) 00200 #define SBBI2_RST0_SOD_REG PORTD 00201 #define SBBI2_RST0_OE_REG DDRD 00202 #elif (SBBI2_RST0_PORT == AVRPORTE) 00203 #define SBBI2_RST0_SOD_REG PORTE 00204 #define SBBI2_RST0_OE_REG DDRE 00205 #elif (SBBI2_RST0_PORT == AVRPORTF) 00206 #define SBBI2_RST0_SOD_REG PORTF 00207 #define SBBI2_RST0_OE_REG DDRF 00208 #elif (SBBI2_RST0_PORT == AVRPORTG) 00209 #define SBBI2_RST0_SOD_REG PORTG 00210 #define SBBI2_RST0_OE_REG DDRG 00211 #elif (SBBI2_RST0_PORT == AVRPORTH) 00212 #define SBBI2_RST0_SOD_REG PORTH 00213 #define SBBI2_RST0_OE_REG DDRH 00214 #endif 00215 00217 #define SBBI2_RST0_ENA() sbi(SBBI2_RST0_OE_REG, SBBI2_RST0_BIT) 00218 00219 #define SBBI2_RST0_CLR() cbi(SBBI2_RST0_SOD_REG, SBBI2_RST0_BIT) 00220 00221 #define SBBI2_RST0_SET() sbi(SBBI2_RST0_SOD_REG, SBBI2_RST0_BIT) 00222 00223 #endif /* SBBI2_RST0_BIT */ 00224 00225 #ifdef SBBI2_RST1_BIT 00226 00227 #if (SBBI2_RST1_PORT == AVRPORTB) 00228 #define SBBI2_RST1_SOD_REG PORTB 00229 #define SBBI2_RST1_OE_REG DDRB 00230 #elif (SBBI2_RST1_PORT == AVRPORTD) 00231 #define SBBI2_RST1_SOD_REG PORTD 00232 #define SBBI2_RST1_OE_REG DDRD 00233 #elif (SBBI2_RST1_PORT == AVRPORTE) 00234 #define SBBI2_RST1_SOD_REG PORTE 00235 #define SBBI2_RST1_OE_REG DDRE 00236 #elif (SBBI2_RST1_PORT == AVRPORTF) 00237 #define SBBI2_RST1_SOD_REG PORTF 00238 #define SBBI2_RST1_OE_REG DDRF 00239 #elif (SBBI2_RST1_PORT == AVRPORTG) 00240 #define SBBI2_RST1_SOD_REG PORTG 00241 #define SBBI2_RST1_OE_REG DDRG 00242 #elif (SBBI2_RST1_PORT == AVRPORTH) 00243 #define SBBI2_RST1_SOD_REG PORTH 00244 #define SBBI2_RST1_OE_REG DDRH 00245 #endif 00246 00248 #define SBBI2_RST1_ENA() sbi(SBBI2_RST1_OE_REG, SBBI2_RST1_BIT) 00249 00250 #define SBBI2_RST1_CLR() cbi(SBBI2_RST1_SOD_REG, SBBI2_RST1_BIT) 00251 00252 #define SBBI2_RST1_SET() sbi(SBBI2_RST1_SOD_REG, SBBI2_RST1_BIT) 00253 00254 #endif /* SBBI2_RST1_BIT */ 00255 00256 #ifdef SBBI2_RST2_BIT 00257 00258 #if (SBBI2_RST2_PORT == AVRPORTB) 00259 #define SBBI2_RST2_SOD_REG PORTB 00260 #define SBBI2_RST2_OE_REG DDRB 00261 #elif (SBBI2_RST2_PORT == AVRPORTD) 00262 #define SBBI2_RST2_SOD_REG PORTD 00263 #define SBBI2_RST2_OE_REG DDRD 00264 #elif (SBBI2_RST2_PORT == AVRPORTE) 00265 #define SBBI2_RST2_SOD_REG PORTE 00266 #define SBBI2_RST2_OE_REG DDRE 00267 #elif (SBBI2_RST2_PORT == AVRPORTF) 00268 #define SBBI2_RST2_SOD_REG PORTF 00269 #define SBBI2_RST2_OE_REG DDRF 00270 #elif (SBBI2_RST2_PORT == AVRPORTG) 00271 #define SBBI2_RST2_SOD_REG PORTG 00272 #define SBBI2_RST2_OE_REG DDRG 00273 #elif (SBBI2_RST2_PORT == AVRPORTH) 00274 #define SBBI2_RST2_SOD_REG PORTH 00275 #define SBBI2_RST2_OE_REG DDRH 00276 #endif 00277 00279 #define SBBI2_RST2_ENA() sbi(SBBI2_RST2_OE_REG, SBBI2_RST2_BIT) 00280 00281 #define SBBI2_RST2_CLR() cbi(SBBI2_RST2_SOD_REG, SBBI2_RST2_BIT) 00282 00283 #define SBBI2_RST2_SET() sbi(SBBI2_RST2_SOD_REG, SBBI2_RST2_BIT) 00284 00285 #endif /* SBBI2_RST2_BIT */ 00286 00287 #ifdef SBBI2_RST3_BIT 00288 00289 #if (SBBI2_RST3_PORT == AVRPORTB) 00290 #define SBBI2_RST3_SOD_REG PORTB 00291 #define SBBI2_RST3_OE_REG DDRB 00292 #elif (SBBI2_RST3_PORT == AVRPORTD) 00293 #define SBBI2_RST3_SOD_REG PORTD 00294 #define SBBI2_RST3_OE_REG DDRD 00295 #elif (SBBI2_RST3_PORT == AVRPORTE) 00296 #define SBBI2_RST3_SOD_REG PORTE 00297 #define SBBI2_RST3_OE_REG DDRE 00298 #elif (SBBI2_RST3_PORT == AVRPORTF) 00299 #define SBBI2_RST3_SOD_REG PORTF 00300 #define SBBI2_RST3_OE_REG DDRF 00301 #elif (SBBI2_RST3_PORT == AVRPORTG) 00302 #define SBBI2_RST3_SOD_REG PORTG 00303 #define SBBI2_RST3_OE_REG DDRG 00304 #elif (SBBI2_RST3_PORT == AVRPORTH) 00305 #define SBBI2_RST3_SOD_REG PORTH 00306 #define SBBI2_RST3_OE_REG DDRH 00307 #endif 00308 00310 #define SBBI2_RST3_ENA() sbi(SBBI2_RST3_OE_REG, SBBI2_RST3_BIT) 00311 00312 #define SBBI2_RST3_CLR() cbi(SBBI2_RST3_SOD_REG, SBBI2_RST3_BIT) 00313 00314 #define SBBI2_RST3_SET() sbi(SBBI2_RST3_SOD_REG, SBBI2_RST3_BIT) 00315 00316 #endif /* SBBI2_RST3_BIT */ 00317 00318 #ifdef SBBI2_SCK_BIT 00319 00320 #if (SBBI2_SCK_PORT == AVRPORTB) 00321 #define SBBI2_SCK_SOD_REG PORTB 00322 #define SBBI2_SCK_OE_REG DDRB 00323 #elif (SBBI2_SCK_PORT == AVRPORTD) 00324 #define SBBI2_SCK_SOD_REG PORTD 00325 #define SBBI2_SCK_OE_REG DDRD 00326 #elif (SBBI2_SCK_PORT == AVRPORTE) 00327 #define SBBI2_SCK_SOD_REG PORTE 00328 #define SBBI2_SCK_OE_REG DDRE 00329 #elif (SBBI2_SCK_PORT == AVRPORTF) 00330 #define SBBI2_SCK_SOD_REG PORTF 00331 #define SBBI2_SCK_OE_REG DDRF 00332 #elif (SBBI2_SCK_PORT == AVRPORTG) 00333 #define SBBI2_SCK_SOD_REG PORTG 00334 #define SBBI2_SCK_OE_REG DDRG 00335 #elif (SBBI2_SCK_PORT == AVRPORTH) 00336 #define SBBI2_SCK_SOD_REG PORTH 00337 #define SBBI2_SCK_OE_REG DDRH 00338 #endif 00339 00341 #define SBBI2_SCK_ENA() sbi(SBBI2_SCK_OE_REG, SBBI2_SCK_BIT) 00342 00343 #define SBBI2_SCK_CLR() cbi(SBBI2_SCK_SOD_REG, SBBI2_SCK_BIT) 00344 00345 #define SBBI2_SCK_SET() sbi(SBBI2_SCK_SOD_REG, SBBI2_SCK_BIT) 00346 00347 #if defined(SBBI2_MOSI_BIT) 00348 00349 #if (SBBI2_MOSI_PORT == AVRPORTB) 00350 #define SBBI2_MOSI_SOD_REG PORTB 00351 #define SBBI2_MOSI_OE_REG DDRB 00352 #elif (SBBI2_MOSI_PORT == AVRPORTD) 00353 #define SBBI2_MOSI_SOD_REG PORTD 00354 #define SBBI2_MOSI_OE_REG DDRD 00355 #elif (SBBI2_MOSI_PORT == AVRPORTE) 00356 #define SBBI2_MOSI_SOD_REG PORTE 00357 #define SBBI2_MOSI_OE_REG DDRE 00358 #elif (SBBI2_MOSI_PORT == AVRPORTF) 00359 #define SBBI2_MOSI_SOD_REG PORTF 00360 #define SBBI2_MOSI_OE_REG DDRF 00361 #elif (SBBI2_MOSI_PORT == AVRPORTG) 00362 #define SBBI2_MOSI_SOD_REG PORTG 00363 #define SBBI2_MOSI_OE_REG DDRG 00364 #elif (SBBI2_MOSI_PORT == AVRPORTH) 00365 #define SBBI2_MOSI_SOD_REG PORTH 00366 #define SBBI2_MOSI_OE_REG DDRH 00367 #endif 00368 00370 #define SBBI2_MOSI_ENA() sbi(SBBI2_MOSI_OE_REG, SBBI2_MOSI_BIT) 00371 00372 #define SBBI2_MOSI_CLR() cbi(SBBI2_MOSI_SOD_REG, SBBI2_MOSI_BIT) 00373 00374 #define SBBI2_MOSI_SET() sbi(SBBI2_MOSI_SOD_REG, SBBI2_MOSI_BIT) 00375 00376 #else /* SBBI2_MOSI_BIT */ 00377 00378 #define SBBI2_MOSI_ENA() 00379 #define SBBI2_MOSI_CLR() 00380 #define SBBI2_MOSI_SET() 00381 00382 #endif /* SBBI2_MOSI_BIT */ 00383 00384 #if defined(SBBI2_MISO_BIT) 00385 00386 #if (SBBI2_MISO_PORT == AVRPORTB) 00387 #define SBBI2_MISO_PDS_REG PINB 00388 #define SBBI2_MISO_PUE_REG PORTB 00389 #define SBBI2_MISO_OE_REG DDRB 00390 #elif (SBBI2_MISO_PORT == AVRPORTD) 00391 #define SBBI2_MISO_PDS_REG PIND 00392 #define SBBI2_MISO_PUE_REG PORTD 00393 #define SBBI2_MISO_OE_REG DDRD 00394 #elif (SBBI2_MISO_PORT == AVRPORTE) 00395 #define SBBI2_MISO_PDS_REG PINE 00396 #define SBBI2_MISO_PUE_REG PORTE 00397 #define SBBI2_MISO_OE_REG DDRE 00398 #elif (SBBI2_MISO_PORT == AVRPORTF) 00399 #define SBBI2_MISO_PDS_REG PINF 00400 #define SBBI2_MISO_PUE_REG PORTF 00401 #define SBBI2_MISO_OE_REG DDRF 00402 #elif (SBBI2_MISO_PORT == AVRPORTG) 00403 #define SBBI2_MISO_PDS_REG PING 00404 #define SBBI2_MISO_PUE_REG PORTG 00405 #define SBBI2_MISO_OE_REG DDRG 00406 #elif (SBBI2_MISO_PORT == AVRPORTH) 00407 #define SBBI2_MISO_PDS_REG PINH 00408 #define SBBI2_MISO_PUE_REG PORTH 00409 #define SBBI2_MISO_OE_REG DDRH 00410 #endif 00411 00413 #define SBBI2_MISO_ENA() \ 00414 cbi(SBBI2_MISO_OE_REG, SBBI2_MISO_BIT); \ 00415 sbi(SBBI2_MISO_PUE_REG, SBBI2_MISO_BIT) 00416 00417 #define SBBI2_MISO_TST() ((inb(SBBI2_MISO_PDS_REG) & _BV(SBBI2_MISO_BIT)) == _BV(SBBI2_MISO_BIT)) 00418 00419 #else /* SBBI2_MISO_BIT */ 00420 00421 #define SBBI2_MISO_ENA() 00422 #define SBBI2_MISO_TST() 0 00423 00424 #endif /* SBBI2_MISO_BIT */ 00425 00426 #endif /* SBBI2_SCK_BIT */ 00427 00428 #else /* MCU */ 00429 /* 00430 * AT91 implementation. 00431 * ====================================== 00432 */ 00433 00434 #ifdef SBBI2_CS0_BIT 00435 00436 #if !defined(SBBI2_CS0_PORT) 00437 #define SBBI2_CS0_PE_REG PIO_PER 00438 #define SBBI2_CS0_OE_REG PIO_OER 00439 #define SBBI2_CS0_COD_REG PIO_CODR 00440 #define SBBI2_CS0_SOD_REG PIO_SODR 00441 #elif SBBI2_CS0_PORT == PIOA_ID 00442 #define SBBI2_CS0_PE_REG PIOA_PER 00443 #define SBBI2_CS0_OE_REG PIOA_OER 00444 #define SBBI2_CS0_COD_REG PIOA_CODR 00445 #define SBBI2_CS0_SOD_REG PIOA_SODR 00446 #elif SBBI2_CS0_PORT == PIOB_ID 00447 #define SBBI2_CS0_PE_REG PIOB_PER 00448 #define SBBI2_CS0_OE_REG PIOB_OER 00449 #define SBBI2_CS0_COD_REG PIOB_CODR 00450 #define SBBI2_CS0_SOD_REG PIOB_SODR 00451 #elif SBBI2_CS0_PORT == PIOC_ID 00452 #define SBBI2_CS0_PE_REG PIOC_PER 00453 #define SBBI2_CS0_OE_REG PIOC_OER 00454 #define SBBI2_CS0_COD_REG PIOC_CODR 00455 #define SBBI2_CS0_SOD_REG PIOC_SODR 00456 #endif 00457 00459 #define SBBI2_CS0_ENA() \ 00460 outr(SBBI2_CS0_PE_REG, _BV(SBBI2_CS0_BIT)); \ 00461 outr(SBBI2_CS0_OE_REG, _BV(SBBI2_CS0_BIT)) 00462 00463 #define SBBI2_CS0_CLR() outr(SBBI2_CS0_COD_REG, _BV(SBBI2_CS0_BIT)) 00464 00465 #define SBBI2_CS0_SET() outr(SBBI2_CS0_SOD_REG, _BV(SBBI2_CS0_BIT)) 00466 00467 #endif /* SBBI2_CS0_BIT */ 00468 00469 #ifdef SBBI2_CS1_BIT 00470 00471 #if !defined(SBBI2_CS1_PORT) 00472 #define SBBI2_CS1_PE_REG PIO_PER 00473 #define SBBI2_CS1_OE_REG PIO_OER 00474 #define SBBI2_CS1_COD_REG PIO_CODR 00475 #define SBBI2_CS1_SOD_REG PIO_SODR 00476 #elif SBBI2_CS1_PORT == PIOA_ID 00477 #define SBBI2_CS1_PE_REG PIOA_PER 00478 #define SBBI2_CS1_OE_REG PIOA_OER 00479 #define SBBI2_CS1_COD_REG PIOA_CODR 00480 #define SBBI2_CS1_SOD_REG PIOA_SODR 00481 #elif SBBI2_CS1_PORT == PIOB_ID 00482 #define SBBI2_CS1_PE_REG PIOB_PER 00483 #define SBBI2_CS1_OE_REG PIOB_OER 00484 #define SBBI2_CS1_COD_REG PIOB_CODR 00485 #define SBBI2_CS1_SOD_REG PIOB_SODR 00486 #elif SBBI2_CS1_PORT == PIOC_ID 00487 #define SBBI2_CS1_PE_REG PIOC_PER 00488 #define SBBI2_CS1_OE_REG PIOC_OER 00489 #define SBBI2_CS1_COD_REG PIOC_CODR 00490 #define SBBI2_CS1_SOD_REG PIOC_SODR 00491 #endif 00492 00494 #define SBBI2_CS1_ENA() \ 00495 outr(SBBI2_CS1_PE_REG, _BV(SBBI2_CS1_BIT)); \ 00496 outr(SBBI2_CS1_OE_REG, _BV(SBBI2_CS1_BIT)) 00497 00498 #define SBBI2_CS1_CLR() outr(SBBI2_CS1_COD_REG, _BV(SBBI2_CS1_BIT)) 00499 00500 #define SBBI2_CS1_SET() outr(SBBI2_CS1_SOD_REG, _BV(SBBI2_CS1_BIT)) 00501 00502 #endif /* SBBI2_CS1_BIT */ 00503 00504 #ifdef SBBI2_CS2_BIT 00505 00506 #if !defined(SBBI2_CS2_PORT) 00507 #define SBBI2_CS2_PE_REG PIO_PER 00508 #define SBBI2_CS2_OE_REG PIO_OER 00509 #define SBBI2_CS2_COD_REG PIO_CODR 00510 #define SBBI2_CS2_SOD_REG PIO_SODR 00511 #elif SBBI2_CS2_PORT == PIOA_ID 00512 #define SBBI2_CS2_PE_REG PIOA_PER 00513 #define SBBI2_CS2_OE_REG PIOA_OER 00514 #define SBBI2_CS2_COD_REG PIOA_CODR 00515 #define SBBI2_CS2_SOD_REG PIOA_SODR 00516 #elif SBBI2_CS2_PORT == PIOB_ID 00517 #define SBBI2_CS2_PE_REG PIOB_PER 00518 #define SBBI2_CS2_OE_REG PIOB_OER 00519 #define SBBI2_CS2_COD_REG PIOB_CODR 00520 #define SBBI2_CS2_SOD_REG PIOB_SODR 00521 #elif SBBI2_CS2_PORT == PIOC_ID 00522 #define SBBI2_CS2_PE_REG PIOC_PER 00523 #define SBBI2_CS2_OE_REG PIOC_OER 00524 #define SBBI2_CS2_COD_REG PIOC_CODR 00525 #define SBBI2_CS2_SOD_REG PIOC_SODR 00526 #endif 00527 00529 #define SBBI2_CS2_ENA() \ 00530 outr(SBBI2_CS2_PE_REG, _BV(SBBI2_CS2_BIT)); \ 00531 outr(SBBI2_CS2_OE_REG, _BV(SBBI2_CS2_BIT)) 00532 00533 #define SBBI2_CS2_CLR() outr(SBBI2_CS2_COD_REG, _BV(SBBI2_CS2_BIT)) 00534 00535 #define SBBI2_CS2_SET() outr(SBBI2_CS2_SOD_REG, _BV(SBBI2_CS2_BIT)) 00536 00537 #endif /* SBBI2_CS2_BIT */ 00538 00539 #ifdef SBBI2_CS3_BIT 00540 00541 #if !defined(SBBI2_CS3_PORT) 00542 #define SBBI2_CS3_PE_REG PIO_PER 00543 #define SBBI2_CS3_OE_REG PIO_OER 00544 #define SBBI2_CS3_COD_REG PIO_CODR 00545 #define SBBI2_CS3_SOD_REG PIO_SODR 00546 #elif SBBI2_CS3_PORT == PIOA_ID 00547 #define SBBI2_CS3_PE_REG PIOA_PER 00548 #define SBBI2_CS3_OE_REG PIOA_OER 00549 #define SBBI2_CS3_COD_REG PIOA_CODR 00550 #define SBBI2_CS3_SOD_REG PIOA_SODR 00551 #elif SBBI2_CS3_PORT == PIOB_ID 00552 #define SBBI2_CS3_PE_REG PIOB_PER 00553 #define SBBI2_CS3_OE_REG PIOB_OER 00554 #define SBBI2_CS3_COD_REG PIOB_CODR 00555 #define SBBI2_CS3_SOD_REG PIOB_SODR 00556 #elif SBBI2_CS3_PORT == PIOC_ID 00557 #define SBBI2_CS3_PE_REG PIOC_PER 00558 #define SBBI2_CS3_OE_REG PIOC_OER 00559 #define SBBI2_CS3_COD_REG PIOC_CODR 00560 #define SBBI2_CS3_SOD_REG PIOC_SODR 00561 #endif 00562 00564 #define SBBI2_CS3_ENA() \ 00565 outr(SBBI2_CS3_PE_REG, _BV(SBBI2_CS3_BIT)); \ 00566 outr(SBBI2_CS3_OE_REG, _BV(SBBI2_CS3_BIT)) 00567 00568 #define SBBI2_CS3_CLR() outr(SBBI2_CS3_COD_REG, _BV(SBBI2_CS3_BIT)) 00569 00570 #define SBBI2_CS3_SET() outr(SBBI2_CS3_SOD_REG, _BV(SBBI2_CS3_BIT)) 00571 00572 #endif /* SBBI2_CS3_BIT */ 00573 00574 #ifdef SBBI2_RST0_BIT 00575 00576 #if !defined(SBBI2_RST0_PORT) 00577 #define SBBI2_RST0_PE_REG PIO_PER 00578 #define SBBI2_RST0_OE_REG PIO_OER 00579 #define SBBI2_RST0_COD_REG PIO_CODR 00580 #define SBBI2_RST0_SOD_REG PIO_SODR 00581 #elif SBBI2_RST0_PORT == PIOA_ID 00582 #define SBBI2_RST0_PE_REG PIOA_PER 00583 #define SBBI2_RST0_OE_REG PIOA_OER 00584 #define SBBI2_RST0_COD_REG PIOA_CODR 00585 #define SBBI2_RST0_SOD_REG PIOA_SODR 00586 #elif SBBI2_RST0_PORT == PIOB_ID 00587 #define SBBI2_RST0_PE_REG PIOB_PER 00588 #define SBBI2_RST0_OE_REG PIOB_OER 00589 #define SBBI2_RST0_COD_REG PIOB_CODR 00590 #define SBBI2_RST0_SOD_REG PIOB_SODR 00591 #elif SBBI2_RST0_PORT == PIOC_ID 00592 #define SBBI2_RST0_PE_REG PIOC_PER 00593 #define SBBI2_RST0_OE_REG PIOC_OER 00594 #define SBBI2_RST0_COD_REG PIOC_CODR 00595 #define SBBI2_RST0_SOD_REG PIOC_SODR 00596 #endif 00597 00599 #define SBBI2_RST0_ENA() \ 00600 outr(SBBI2_RST0_PE_REG, _BV(SBBI2_RST0_BIT)); \ 00601 outr(SBBI2_RST0_OE_REG, _BV(SBBI2_RST0_BIT)) 00602 00603 #define SBBI2_RST0_CLR() outr(SBBI2_RST0_COD_REG, _BV(SBBI2_RST0_BIT)) 00604 00605 #define SBBI2_RST0_SET() outr(SBBI2_RST0_SOD_REG, _BV(SBBI2_RST0_BIT)) 00606 00607 #endif /* SBBI2_RST0_BIT */ 00608 00609 #ifdef SBBI2_RST1_BIT 00610 00611 #if !defined(SBBI2_RST1_PORT) 00612 #define SBBI2_RST1_PE_REG PIO_PER 00613 #define SBBI2_RST1_OE_REG PIO_OER 00614 #define SBBI2_RST1_COD_REG PIO_CODR 00615 #define SBBI2_RST1_SOD_REG PIO_SODR 00616 #elif SBBI2_RST1_PORT == PIOA_ID 00617 #define SBBI2_RST1_PE_REG PIOA_PER 00618 #define SBBI2_RST1_OE_REG PIOA_OER 00619 #define SBBI2_RST1_COD_REG PIOA_CODR 00620 #define SBBI2_RST1_SOD_REG PIOA_SODR 00621 #elif SBBI2_RST1_PORT == PIOB_ID 00622 #define SBBI2_RST1_PE_REG PIOB_PER 00623 #define SBBI2_RST1_OE_REG PIOB_OER 00624 #define SBBI2_RST1_COD_REG PIOB_CODR 00625 #define SBBI2_RST1_SOD_REG PIOB_SODR 00626 #elif SBBI2_RST1_PORT == PIOC_ID 00627 #define SBBI2_RST1_PE_REG PIOC_PER 00628 #define SBBI2_RST1_OE_REG PIOC_OER 00629 #define SBBI2_RST1_COD_REG PIOC_CODR 00630 #define SBBI2_RST1_SOD_REG PIOC_SODR 00631 #endif 00632 00634 #define SBBI2_RST1_ENA() \ 00635 outr(SBBI2_RST1_PE_REG, _BV(SBBI2_RST1_BIT)); \ 00636 outr(SBBI2_RST1_OE_REG, _BV(SBBI2_RST1_BIT)) 00637 00638 #define SBBI2_RST1_CLR() outr(SBBI2_RST1_COD_REG, _BV(SBBI2_RST1_BIT)) 00639 00640 #define SBBI2_RST1_SET() outr(SBBI2_RST1_SOD_REG, _BV(SBBI2_RST1_BIT)) 00641 00642 #endif /* SBBI2_RST1_BIT */ 00643 00644 #ifdef SBBI2_RST2_BIT 00645 00646 #if !defined(SBBI2_RST2_PORT) 00647 #define SBBI2_RST2_PE_REG PIO_PER 00648 #define SBBI2_RST2_OE_REG PIO_OER 00649 #define SBBI2_RST2_COD_REG PIO_CODR 00650 #define SBBI2_RST2_SOD_REG PIO_SODR 00651 #elif SBBI2_RST2_PORT == PIOA_ID 00652 #define SBBI2_RST2_PE_REG PIOA_PER 00653 #define SBBI2_RST2_OE_REG PIOA_OER 00654 #define SBBI2_RST2_COD_REG PIOA_CODR 00655 #define SBBI2_RST2_SOD_REG PIOA_SODR 00656 #elif SBBI2_RST2_PORT == PIOB_ID 00657 #define SBBI2_RST2_PE_REG PIOB_PER 00658 #define SBBI2_RST2_OE_REG PIOB_OER 00659 #define SBBI2_RST2_COD_REG PIOB_CODR 00660 #define SBBI2_RST2_SOD_REG PIOB_SODR 00661 #elif SBBI2_RST2_PORT == PIOC_ID 00662 #define SBBI2_RST2_PE_REG PIOC_PER 00663 #define SBBI2_RST2_OE_REG PIOC_OER 00664 #define SBBI2_RST2_COD_REG PIOC_CODR 00665 #define SBBI2_RST2_SOD_REG PIOC_SODR 00666 #endif 00667 00669 #define SBBI2_RST2_ENA() \ 00670 outr(SBBI2_RST2_PE_REG, _BV(SBBI2_RST2_BIT)); \ 00671 outr(SBBI2_RST2_OE_REG, _BV(SBBI2_RST2_BIT)) 00672 00673 #define SBBI2_RST2_CLR() outr(SBBI2_RST2_COD_REG, _BV(SBBI2_RST2_BIT)) 00674 00675 #define SBBI2_RST2_SET() outr(SBBI2_RST2_SOD_REG, _BV(SBBI2_RST2_BIT)) 00676 00677 #endif /* SBBI2_RST2_BIT */ 00678 00679 #ifdef SBBI2_RST3_BIT 00680 00681 #if !defined(SBBI2_RST3_PORT) 00682 #define SBBI2_RST3_PE_REG PIO_PER 00683 #define SBBI2_RST3_OE_REG PIO_OER 00684 #define SBBI2_RST3_COD_REG PIO_CODR 00685 #define SBBI2_RST3_SOD_REG PIO_SODR 00686 #elif SBBI2_RST3_PORT == PIOA_ID 00687 #define SBBI2_RST3_PE_REG PIOA_PER 00688 #define SBBI2_RST3_OE_REG PIOA_OER 00689 #define SBBI2_RST3_COD_REG PIOA_CODR 00690 #define SBBI2_RST3_SOD_REG PIOA_SODR 00691 #elif SBBI2_RST3_PORT == PIOB_ID 00692 #define SBBI2_RST3_PE_REG PIOB_PER 00693 #define SBBI2_RST3_OE_REG PIOB_OER 00694 #define SBBI2_RST3_COD_REG PIOB_CODR 00695 #define SBBI2_RST3_SOD_REG PIOB_SODR 00696 #elif SBBI2_RST3_PORT == PIOC_ID 00697 #define SBBI2_RST3_PE_REG PIOC_PER 00698 #define SBBI2_RST3_OE_REG PIOC_OER 00699 #define SBBI2_RST3_COD_REG PIOC_CODR 00700 #define SBBI2_RST3_SOD_REG PIOC_SODR 00701 #endif 00702 00704 #define SBBI2_RST3_ENA() \ 00705 outr(SBBI2_RST3_PE_REG, _BV(SBBI2_RST3_BIT)); \ 00706 outr(SBBI2_RST3_OE_REG, _BV(SBBI2_RST3_BIT)) 00707 00708 #define SBBI2_RST3_CLR() outr(SBBI2_RST3_COD_REG, _BV(SBBI2_RST3_BIT)) 00709 00710 #define SBBI2_RST3_SET() outr(SBBI2_RST3_SOD_REG, _BV(SBBI2_RST3_BIT)) 00711 00712 #endif /* SBBI2_RST3_BIT */ 00713 00714 #ifdef SBBI2_SCK_BIT 00715 00716 #if !defined(SBBI2_SCK_PORT) 00717 #define SBBI2_SCK_PE_REG PIO_PER 00718 #define SBBI2_SCK_OE_REG PIO_OER 00719 #define SBBI2_SCK_COD_REG PIO_CODR 00720 #define SBBI2_SCK_SOD_REG PIO_SODR 00721 #elif SBBI2_SCK_PORT == PIOA_ID 00722 #define SBBI2_SCK_PE_REG PIOA_PER 00723 #define SBBI2_SCK_OE_REG PIOA_OER 00724 #define SBBI2_SCK_COD_REG PIOA_CODR 00725 #define SBBI2_SCK_SOD_REG PIOA_SODR 00726 #elif SBBI2_SCK_PORT == PIOB_ID 00727 #define SBBI2_SCK_PE_REG PIOB_PER 00728 #define SBBI2_SCK_OE_REG PIOB_OER 00729 #define SBBI2_SCK_COD_REG PIOB_CODR 00730 #define SBBI2_SCK_SOD_REG PIOB_SODR 00731 #elif SBBI2_SCK_PORT == PIOC_ID 00732 #define SBBI2_SCK_PE_REG PIOC_PER 00733 #define SBBI2_SCK_OE_REG PIOC_OER 00734 #define SBBI2_SCK_COD_REG PIOC_CODR 00735 #define SBBI2_SCK_SOD_REG PIOC_SODR 00736 #endif 00737 00739 #define SBBI2_SCK_ENA() \ 00740 outr(SBBI2_SCK_PE_REG, _BV(SBBI2_SCK_BIT)); \ 00741 outr(SBBI2_SCK_OE_REG, _BV(SBBI2_SCK_BIT)) 00742 00743 #define SBBI2_SCK_CLR() outr(SBBI2_SCK_COD_REG, _BV(SBBI2_SCK_BIT)) 00744 00745 #define SBBI2_SCK_SET() outr(SBBI2_SCK_SOD_REG, _BV(SBBI2_SCK_BIT)) 00746 00747 #ifdef SBBI2_MOSI_BIT 00748 00749 #if !defined(SBBI2_MOSI_PORT) 00750 #define SBBI2_MOSI_PE_REG PIO_PER 00751 #define SBBI2_MOSI_OE_REG PIO_OER 00752 #define SBBI2_MOSI_COD_REG PIO_CODR 00753 #define SBBI2_MOSI_SOD_REG PIO_SODR 00754 #elif SBBI2_MOSI_PORT == PIOA_ID 00755 #define SBBI2_MOSI_PE_REG PIOA_PER 00756 #define SBBI2_MOSI_OE_REG PIOA_OER 00757 #define SBBI2_MOSI_COD_REG PIOA_CODR 00758 #define SBBI2_MOSI_SOD_REG PIOA_SODR 00759 #elif SBBI2_MOSI_PORT == PIOB_ID 00760 #define SBBI2_MOSI_PE_REG PIOB_PER 00761 #define SBBI2_MOSI_OE_REG PIOB_OER 00762 #define SBBI2_MOSI_COD_REG PIOB_CODR 00763 #define SBBI2_MOSI_SOD_REG PIOB_SODR 00764 #elif SBBI2_MOSI_PORT == PIOC_ID 00765 #define SBBI2_MOSI_PE_REG PIOC_PER 00766 #define SBBI2_MOSI_OE_REG PIOC_OER 00767 #define SBBI2_MOSI_COD_REG PIOC_CODR 00768 #define SBBI2_MOSI_SOD_REG PIOC_SODR 00769 #endif 00770 00772 #define SBBI2_MOSI_ENA() \ 00773 outr(SBBI2_MOSI_PE_REG, _BV(SBBI2_MOSI_BIT)); \ 00774 outr(SBBI2_MOSI_OE_REG, _BV(SBBI2_MOSI_BIT)) 00775 00776 #define SBBI2_MOSI_CLR() outr(SBBI2_MOSI_COD_REG, _BV(SBBI2_MOSI_BIT)) 00777 00778 #define SBBI2_MOSI_SET() outr(SBBI2_MOSI_SOD_REG, _BV(SBBI2_MOSI_BIT)) 00779 00780 #else /* SBBI2_MOSI_BIT */ 00781 00782 #define SBBI2_MOSI_ENA() 00783 #define SBBI2_MOSI_CLR() 00784 #define SBBI2_MOSI_SET() 00785 00786 #endif /* SBBI2_MOSI_BIT */ 00787 00788 #ifdef SBBI2_MISO_BIT 00789 00790 #if !defined(SBBI2_MISO_PORT) 00791 #define SBBI2_MISO_PE_REG PIO_PER 00792 #define SBBI2_MISO_OD_REG PIO_ODR 00793 #define SBBI2_MISO_PDS_REG PIO_PDSR 00794 #elif SBBI2_MISO_PORT == PIOA_ID 00795 #define SBBI2_MISO_PE_REG PIOA_PER 00796 #define SBBI2_MISO_OD_REG PIOA_ODR 00797 #define SBBI2_MISO_PDS_REG PIOA_PDSR 00798 #elif SBBI2_MISO_PORT == PIOB_ID 00799 #define SBBI2_MISO_PE_REG PIOB_PER 00800 #define SBBI2_MISO_OD_REG PIOB_ODR 00801 #define SBBI2_MISO_PDS_REG PIOB_PDSR 00802 #elif SBBI2_MISO_PORT == PIOC_ID 00803 #define SBBI2_MISO_PE_REG PIOC_PER 00804 #define SBBI2_MISO_OD_REG PIOC_ODR 00805 #define SBBI2_MISO_PDS_REG PIOC_PDSR 00806 #endif 00807 00809 #define SBBI2_MISO_ENA() \ 00810 outr(SBBI2_MISO_PE_REG, _BV(SBBI2_MISO_BIT)); \ 00811 outr(SBBI2_MISO_OD_REG, _BV(SBBI2_MISO_BIT)) 00812 00813 #define SBBI2_MISO_TST() ((inr(SBBI2_MISO_PDS_REG) & _BV(SBBI2_MISO_BIT)) == _BV(SBBI2_MISO_BIT)) 00814 00815 #else /* SBBI2_MISO_BIT */ 00816 00817 #define SBBI2_MISO_ENA() 00818 #define SBBI2_MISO_TST() 0 00819 00820 #endif /* SBBI2_MISO_BIT */ 00821 00822 #endif /* SBBI2_SCK_BIT */ 00823 00824 #endif /* MCU */ 00825 00826 #define SBBI2_INIT() \ 00827 { \ 00828 SBBI2_SCK_CLR(); \ 00829 SBBI2_SCK_ENA(); \ 00830 SBBI2_MOSI_CLR(); \ 00831 SBBI2_MOSI_ENA(); \ 00832 SBBI2_MISO_ENA(); \ 00833 } 00834 00835 #endif