spibus0.c

Go to the documentation of this file.

#include <cfg/spi.h>

#include <arch/avr32.h>
#include <arch/avr32/gpio.h>

#include <dev/spibus_avr32.h>
#include <dev/irqreg.h>
#include <dev/gpio.h>
#include <sys/event.h>
#include <sys/nutdebug.h>

#include <stdlib.h>
#include <errno.h>

#include <avr32/io.h>

#ifndef AVR32_SPI0_ADDRESS
#define AVR32_SPI0_ADDRESS AVR32_SPI_ADDRESS
#endif

#ifndef AVR32_SPI0
#define AVR32_SPI0 AVR32_SPI
#endif

#if defined(AVR32_SPI0_SCK_0_0_PIN)
#define AVR32_SPI0_SCK_PIN          AVR32_SPI0_SCK_0_0_PIN
#define AVR32_SPI0_SCK_FUNCTION     AVR32_SPI0_SCK_0_0_FUNCTION
#define AVR32_SPI0_MISO_PIN         AVR32_SPI0_MISO_0_0_PIN
#define AVR32_SPI0_MISO_FUNCTION    AVR32_SPI0_MISO_0_0_FUNCTION
#define AVR32_SPI0_MOSI_PIN         AVR32_SPI0_MOSI_0_0_PIN
#define AVR32_SPI0_MOSI_FUNCTION    AVR32_SPI0_MOSI_0_0_FUNCTION
#define AVR32_SPI0_NPCS_PIN         AVR32_SPI0_NPCS_0_0_PIN
#define AVR32_SPI0_NPCS_FUNCTION    AVR32_SPI0_NPCS_0_0_FUNCTION
#elif defined(AVR32_SPI0_SCK_0_PIN)
#define AVR32_SPI0_SCK_PIN          AVR32_SPI0_SCK_0_PIN
#define AVR32_SPI0_SCK_FUNCTION     AVR32_SPI0_SCK_0_FUNCTION
#define AVR32_SPI0_MISO_PIN         AVR32_SPI0_MISO_0_PIN
#define AVR32_SPI0_MISO_FUNCTION    AVR32_SPI0_MISO_0_FUNCTION
#define AVR32_SPI0_MOSI_PIN         AVR32_SPI0_MOSI_0_PIN
#define AVR32_SPI0_MOSI_FUNCTION    AVR32_SPI0_MOSI_0_FUNCTION
#define AVR32_SPI0_NPCS_PIN         AVR32_SPI0_NPCS_0_PIN
#define AVR32_SPI0_NPCS_FUNCTION    AVR32_SPI0_NPCS_0_FUNCTION
#elif defined(AVR32_SPI_SCK_0_0_PIN)
#define AVR32_SPI0_SCK_PIN          AVR32_SPI_SCK_0_0_PIN
#define AVR32_SPI0_SCK_FUNCTION     AVR32_SPI_SCK_0_0_FUNCTION
#define AVR32_SPI0_MISO_PIN         AVR32_SPI_MISO_0_0_PIN
#define AVR32_SPI0_MISO_FUNCTION    AVR32_SPI_MISO_0_0_FUNCTION
#define AVR32_SPI0_MOSI_PIN         AVR32_SPI_MOSI_0_0_PIN
#define AVR32_SPI0_MOSI_FUNCTION    AVR32_SPI_MOSI_0_0_FUNCTION
#define AVR32_SPI0_NPCS_PIN         AVR32_SPI_NPCS_0_0_PIN
#define AVR32_SPI0_NPCS_FUNCTION    AVR32_SPI_NPCS_0_0_FUNCTION
#endif

#if defined(SPI0_CS0_PIO_BIT)
#if defined(SPI0_CS0_PIO_ID)
#undef GPIO_ID
#define GPIO_ID SPI0_CS0_PIO_ID
#include <cfg/arch/porttran.h>
static INLINE void SPI0_CS0_LO(void)
{
    GPIO_SET_LO(SPI0_CS0_PIO_BIT);
}

static INLINE void SPI0_CS0_HI(void)
{
    GPIO_SET_HI(SPI0_CS0_PIO_BIT);
}

static INLINE void SPI0_CS0_SO(void)
{
    GPIO_ENABLE(SPI0_CS0_PIO_BIT);
    GPIO_OUTPUT(SPI0_CS0_PIO_BIT);
}
#else
#define SPI0_CS0_LO()
#define SPI0_CS0_HI()
#define SPI0_CS0_SO()
#endif
#endif

#if defined(SPI0_CS1_PIO_BIT)
#if defined(SPI0_CS1_PIO_ID)
#undef GPIO_ID
#define GPIO_ID SPI0_CS1_PIO_ID
#include <cfg/arch/porttran.h>
static INLINE void SPI0_CS1_LO(void)
{
    GPIO_SET_LO(SPI0_CS1_PIO_BIT);
}

static INLINE void SPI0_CS1_HI(void)
{
    GPIO_SET_HI(SPI0_CS1_PIO_BIT);
}

static INLINE void SPI0_CS1_SO(void)
{
    GPIO_ENABLE(SPI0_CS1_PIO_BIT);
    GPIO_OUTPUT(SPI0_CS1_PIO_BIT);
}
#else
#define SPI0_CS1_LO()
#define SPI0_CS1_HI()
#define SPI0_CS1_SO()
#endif
#endif

#if defined(SPI0_CS2_PIO_BIT)
#if defined(SPI0_CS2_PIO_ID)
#undef GPIO_ID
#define GPIO_ID SPI0_CS2_PIO_ID
#include <cfg/arch/porttran.h>
static INLINE void SPI0_CS2_LO(void)
{
    GPIO_SET_LO(SPI0_CS2_PIO_BIT);
}

static INLINE void SPI0_CS2_HI(void)
{
    GPIO_SET_HI(SPI0_CS2_PIO_BIT);
}

static INLINE void SPI0_CS2_SO(void)
{
    GPIO_ENABLE(SPI0_CS2_PIO_BIT);
    GPIO_OUTPUT(SPI0_CS2_PIO_BIT);
}
#else
#define SPI0_CS2_LO()
#define SPI0_CS2_HI()
#define SPI0_CS2_SO()
#endif
#endif

#if defined(SPI0_CS3_PIO_BIT)
#if defined(SPI0_CS3_PIO_ID)
#undef GPIO_ID
#define GPIO_ID SPI0_CS3_PIO_ID
#include <cfg/arch/porttran.h>
static INLINE void SPI0_CS3_LO(void)
{
    GPIO_SET_LO(SPI0_CS3_PIO_BIT);
}

static INLINE void SPI0_CS3_HI(void)
{
    GPIO_SET_HI(SPI0_CS3_PIO_BIT);
}

static INLINE void SPI0_CS3_SO(void)
{
    GPIO_ENABLE(SPI0_CS3_PIO_BIT);
    GPIO_OUTPUT(SPI0_CS3_PIO_BIT);
}
#else
#define SPI0_CS3_LO()
#define SPI0_CS3_HI()
#define SPI0_CS3_SO()
#endif
#endif

int Avr32Spi0ChipSelect(uint_fast8_t cs, uint_fast8_t hi)
{
    int rc = 0;

    switch (cs) {
#if defined(SPI0_CS0_PIO_BIT)
    case 0:
        if (hi) {
            SPI0_CS0_HI();
        } else {
            SPI0_CS0_LO();
        }
        SPI0_CS0_SO();
        break;
#endif
#if defined(SPI0_CS1_PIO_BIT)
    case 1:
        if (hi) {
            SPI0_CS1_HI();
        } else {
            SPI0_CS1_LO();
        }
        SPI0_CS1_SO();
        break;
#endif
#if defined(SPI0_CS2_PIO_BIT)
    case 2:
        if (hi) {
            SPI0_CS2_HI();
        } else {
            SPI0_CS2_LO();
        }
        SPI0_CS2_SO();
        break;
#endif
#if defined(SPI0_CS3_PIO_BIT)
    case 3:
        if (hi) {
            SPI0_CS3_HI();
        } else {
            SPI0_CS3_LO();
        }
        SPI0_CS3_SO();
        break;
#endif
    default:
        errno = EIO;
        rc = -1;
        break;
    }
    return rc;
}

int Avr32SpiBus0Select(NUTSPINODE * node, uint32_t tmo)
{
    int rc;

    /* Sanity check. */
    NUTASSERT(node != NULL);
    NUTASSERT(node->node_bus != NULL);
    NUTASSERT(node->node_stat != NULL);

    /* Allocate the bus. */
    rc = NutEventWait(&node->node_bus->bus_mutex, tmo);
    if (rc) {
        errno = EIO;
    } else {
        AVR32SPIREG *spireg = node->node_stat;

        /* Enable SPI peripherals and clock. */
        gpio_enable_module_pin(AVR32_SPI0_SCK_PIN, AVR32_SPI0_SCK_FUNCTION);
        gpio_enable_module_pin(AVR32_SPI0_MISO_PIN, AVR32_SPI0_MISO_FUNCTION);
        gpio_enable_module_pin(AVR32_SPI0_MOSI_PIN, AVR32_SPI0_MOSI_FUNCTION);
        gpio_enable_module_pin(AVR32_SPI0_NPCS_PIN, AVR32_SPI0_NPCS_FUNCTION);

        /* If the mode update bit is set, then update our registers. */
        if (node->node_mode & SPI_MODE_UPDATE) {
            Avr32SpiSetup(node);
        }

        /* Set SPI mode. */
        outr(AVR32_SPI0_ADDRESS + AVR32_SPI_MR, spireg->mr);
        //outr(AVR32_SPI0_ADDRESS + AVR32_SPI_CSR0 + (node->node_cs * (AVR32_SPI_CSR0 - AVR32_SPI_CSR0)), spireg->csr);
        outr(AVR32_SPI0_ADDRESS + AVR32_SPI_CSR0, spireg->csr);

        /* Enable SPI. */
        AVR32_SPI0.cr |= AVR32_SPI_CR_SPIEN_MASK;

        /* Finally activate the node's chip select. */
        rc = Avr32Spi0ChipSelect(node->node_cs, (node->node_mode & SPI_MODE_CSHIGH) != 0);
        if (rc) {
            /* Release the bus in case of an error. */
            NutEventPost(&node->node_bus->bus_mutex);
        }
    }
    return rc;
}

int Avr32SpiBus0Deselect(NUTSPINODE * node)
{
    /* Sanity check. */
    NUTASSERT(node != NULL);
    NUTASSERT(node->node_bus != NULL);

#ifdef SPIBUS0_DOUBLE_BUFFER
    Avr32SpiBusWait(node, NUT_WAIT_INFINITE);
#endif
    /* Deactivate the node's chip select. */
    Avr32Spi0ChipSelect(node->node_cs, (node->node_mode & SPI_MODE_CSHIGH) == 0);

    /* Release the bus. */
    NutEventPost(&node->node_bus->bus_mutex);

    return 0;
}

#if !defined(SPIBUS0_POLLING_MODE) || !defined(SPIBUS0_DOUBLE_BUFFER)

static uint8_t *volatile spi0_txp;
static uint8_t *volatile spi0_rxp;
static volatile size_t spi0_xc;

void Avr32SpiBus0Interrupt(void *arg)
{
    uint8_t b;

    /* Get the received byte. */
    b = (uint8_t) inr(AVR32_SPI0_ADDRESS + AVR32_SPI_RDR) >> AVR32_SPI_RDR_RD_OFFSET;
    if (spi0_xc) {
        if (spi0_rxp) {
            *spi0_rxp++ = b;
        }
        spi0_xc--;
    }
    if (spi0_xc) {
        if (spi0_txp) {
            b = *spi0_txp++;
        }
        outr(AVR32_SPI0_ADDRESS + AVR32_SPI_TDR, (b << AVR32_SPI_TDR_TD_OFFSET));
    } else {
        NutEventPostFromIrq((void **) arg);
    }
}

int Avr32SpiBus0Transfer(NUTSPINODE * node, CONST void *txbuf, void *rxbuf, int xlen)
{
    uint8_t b = 0xff;
    uintptr_t base;

    /* Sanity check. */
    NUTASSERT(node != NULL);
    NUTASSERT(node->node_bus != NULL);
    NUTASSERT(node->node_bus->bus_base != 0);
    base = node->node_bus->bus_base;

    if (xlen) {
        spi0_txp = (uint8_t *) txbuf;
        spi0_rxp = (uint8_t *) rxbuf;
        spi0_xc = (size_t) xlen;
        if (spi0_txp) {
            b = *spi0_txp++;
        }
        /* Enable and kick interrupts. */
        outr(base + AVR32_SPI_IER, AVR32_SPI_IER_RDRF_MASK);
        outr(base + AVR32_SPI_TDR, (b << AVR32_SPI_TDR_TD_OFFSET));
        /* Wait until transfer has finished. */
        NutEventWait(&node->node_bus->bus_ready, NUT_WAIT_INFINITE);
        outr(base + AVR32_SPI_IDR, (unsigned int) -1);
    }
    return 0;
}
#endif

NUTSPIBUS spiBus0Avr32 = {
    NULL,                       
    NULL,                       
    AVR32_SPI0_ADDRESS,         
    &sig_SPI0,                  
    Avr32SpiBusNodeInit,        
    Avr32SpiBus0Select,         
    Avr32SpiBus0Deselect,       
#if defined(SPIBUS0_POLLING_MODE)
    Avr32SpiBusPollTransfer,    
#elif defined(SPIBUS0_DOUBLE_BUFFER)
    Avr32SpiBusDblBufTransfer,
#else
    Avr32SpiBus0Transfer,
#endif
#ifdef SPIBUS0_DOUBLE_BUFFER
    Avr32SpiBusWait,
#else
    NutSpiBusWait,              
#endif
    NutSpiBusSetMode,           
    NutSpiBusSetRate,           
    NutSpiBusSetBits            
};