sppif0.c

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/*
 * Copyright (C) 2007 by egnite Software GmbH. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the name of the copyright holders nor the names of
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
 * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
 * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 * For additional information see http://www.ethernut.de/
 *
 */

/*
 * $Log$
 * Revision 1.2  2008/08/11 06:59:17  haraldkipp
 * BSD types replaced by stdint types (feature request #1282721).
 *
 * Revision 1.1  2007/04/12 09:07:54  haraldkipp
 * Configurable SPI added.
 *
 */

#include <cfg/arch/avr.h>
#include <sys/timer.h>
#include <dev/sppif0.h>

/* SPI control shadow registers. */
static uint8_t sppi0_spcr[SPPI0_MAX_DEVICES];

/* SPI status shadow registers. Used to configure the double speed bit. */
#ifdef SPI2X
static uint8_t sppi0_spsr[SPPI0_MAX_DEVICES];
#endif

int Sppi0SetMode(uint8_t ix, uint8_t mode)
{
    if (ix >= SPPI0_MAX_DEVICES || mode > 3) {
        return -1;
    }

    /* A bit obfuscated, but compact. A simple shift 
       correctly sets CPHA and CPOL. */
    sppi0_spcr[ix] = _BV(SPE) | _BV(MSTR) | (mode << 2) | _BV(SPR1) | _BV(SPR0);
#if defined(SPI2X)
    sppi0_spsr[ix] = 0;
#endif

    return 0;
}

void Sppi0SetSpeed(uint8_t ix, uint32_t rate)
{
    uint32_t fosc;
    uint8_t i;

    fosc = NutGetCpuClock();

    sppi0_spcr[ix] &= ~(_BV(SPR1) | _BV(SPR0));
    /* Find the frequency that is below or equal the requested 
       one, using the double speed bit if available. */
#if defined(SPI2X)
    for (i = 0; i < 7; i++) {
        fosc >>= 1;
        if (fosc <= rate) {
            break;
        }
    }
    sppi0_spcr[ix] |= (i >> 1);
    if (i < 6) {
        sppi0_spsr[ix] = ~i & 1;
    }
#else
    for (i = 0; i < 3; i++) {
        fosc >>= 2;
        if (fosc <= rate) {
            break;
        }
    }
    sppi0_spcr[ix] |= i;
#endif
}

void Sppi0Enable(uint8_t ix)
{
    /*
     * When configured as SPI master, MOSI (PB2) and SCK (PB1) 
     * lines are not automatically switched to output.
     */
    if (sppi0_spcr[ix] & _BV(CPOL)) {
        cbi(PORTB, 1);
    } else {
        sbi(PORTB, 1);
    }
    sbi(DDRB, 1);
    cbi(PORTB, 2);
    sbi(DDRB, 2);

    /* Enable MISO pull-up to avoid floating. */
    sbi(PORTB, 3);

    /*
     * When SS (PB0) is configured as input, we will be forced
     * into slave mode if this pin goes low. Enable the pull-up.
     */
    if (bit_is_clear(DDRB, 0)) {
        sbi(PORTB, 0);
    }

    /* Set SPI mode and optionally the double speed bit. */
    outb(SPCR, sppi0_spcr[ix]);
#if defined(SPI2X)
    outb(SPSR, sppi0_spsr[ix]);
#endif

    /* Clean-up the status. */
    ix = inb(SPSR);
    ix = inb(SPDR);
}

void Sppi0ChipReset(uint8_t ix, uint8_t hi)
{
#if defined(SPPI0_RST0_BIT)
    if (ix == 0) {
        if (hi) {
            SPPI0_RST0_SET();
        } else {
            SPPI0_RST0_CLR();
        }
        SPPI0_RST0_ENA();
    }
#endif
#if defined(SPPI0_RST1_BIT)
    if (ix == 1) {
        if (hi) {
            SPPI0_RST1_SET();
        } else {
            SPPI0_RST1_CLR();
        }
        SPPI0_RST1_ENA();
    }
#endif
#if defined(SPPI0_RST2_BIT)
    if (ix == 2) {
        if (hi) {
            SPPI0_RST2_SET();
        } else {
            SPPI0_RST2_CLR();
        }
        SPPI0_RST2_ENA();
    }
#endif
#if defined(SPPI0_RST3_BIT)
    if (ix == 3) {
        if (hi) {
            SPPI0_RST3_SET();
        } else {
            SPPI0_RST3_CLR();
        }
        SPPI0_RST3_ENA();
    }
#endif
}

void Sppi0ChipSelect(uint8_t ix, uint8_t hi)
{
#if defined(SPPI0_CS0_BIT)
    if (ix == 0) {
        if (hi) {
            SPPI0_CS0_SET();
        } else {
            SPPI0_CS0_CLR();
        }
        SPPI0_CS0_ENA();
    }
#endif
#if defined(SPPI0_CS1_BIT)
    if (ix == 1) {
        if (hi) {
            SPPI0_CS1_SET();
        } else {
            SPPI0_CS1_CLR();
        }
        SPPI0_CS1_ENA();
    }
#endif
#if defined(SPPI0_CS2_BIT)
    if (ix == 2) {
        if (hi) {
            SPPI0_CS2_SET();
        } else {
            SPPI0_CS2_CLR();
        }
        SPPI0_CS2_ENA();
    }
#endif
#if defined(SPPI0_CS3_BIT)
    if (ix == 3) {
        if (hi) {
            SPPI0_CS3_SET();
        } else {
            SPPI0_CS3_CLR();
        }
        SPPI0_CS3_ENA();
    }
#endif
}

void Sppi0SelectDevice(uint8_t ix)
{
    Sppi0Enable(ix);
    Sppi0ChipSelect(ix, 1);
}

void Sppi0DeselectDevice(uint8_t ix)
{
    Sppi0ChipSelect(ix, 0);
}

void Sppi0NegSelectDevice(uint8_t ix)
{
    Sppi0Enable(ix);
    Sppi0ChipSelect(ix, 0);
}

void Sppi0NegDeselectDevice(uint8_t ix)
{
    Sppi0ChipSelect(ix, 1);
}

uint8_t Sppi0Byte(uint8_t data)
{
    outb(SPDR, data);
    loop_until_bit_is_set(SPSR, SPIF);

    return inb(SPDR);
}

void Sppi0Transact(CONST void *wdata, void *rdata, size_t len)
{
    CONST uint8_t *wp = (CONST uint8_t *)wdata;

    if (rdata) {
        uint8_t *rp = (uint8_t *)rdata;

        while(len--) {
            *rp++ = Sppi0Byte(*wp);
            wp++;
        }
    } else {
        while(len--) {
            Sppi0Byte(*wp);
            wp++;
        }
    }
}