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Nut/OS
4.10.3
API Reference
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Nut/OS
4.10.3
API Reference
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00001 #ifndef _DEV_SPPIF0_H_ 00002 #define _DEV_SPPIF0_H_ 00003 /* 00004 * Copyright (C) 2007 by egnite Software GmbH. All rights reserved. 00005 * 00006 * Redistribution and use in source and binary forms, with or without 00007 * modification, are permitted provided that the following conditions 00008 * are met: 00009 * 00010 * 1. Redistributions of source code must retain the above copyright 00011 * notice, this list of conditions and the following disclaimer. 00012 * 2. Redistributions in binary form must reproduce the above copyright 00013 * notice, this list of conditions and the following disclaimer in the 00014 * documentation and/or other materials provided with the distribution. 00015 * 3. Neither the name of the copyright holders nor the names of 00016 * contributors may be used to endorse or promote products derived 00017 * from this software without specific prior written permission. 00018 * 00019 * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS 00020 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 00021 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 00022 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE 00023 * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 00024 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 00025 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 00026 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 00027 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00028 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 00029 * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 00030 * SUCH DAMAGE. 00031 * 00032 * For additional information see http://www.ethernut.de/ 00033 */ 00034 00052 #include <cfg/arch/gpio.h> 00053 #include <stdint.h> 00054 00058 #ifndef SPPI0_MAX_DEVICES 00059 #define SPPI0_MAX_DEVICES 4 00060 #endif 00061 00062 #if defined(__AVR__) /* MCU */ 00063 /* 00064 * AVR implementation. 00065 * ====================================== 00066 */ 00067 00068 #ifdef SPPI0_CS0_BIT 00069 00070 #if (SPPI0_CS0_AVRPORT == AVRPORTB) 00071 #define SPPI0_CS0_SOD_REG PORTB 00072 #define SPPI0_CS0_OE_REG DDRB 00073 #elif (SPPI0_CS0_AVRPORT == AVRPORTD) 00074 #define SPPI0_CS0_SOD_REG PORTD 00075 #define SPPI0_CS0_OE_REG DDRD 00076 #elif (SPPI0_CS0_AVRPORT == AVRPORTE) 00077 #define SPPI0_CS0_SOD_REG PORTE 00078 #define SPPI0_CS0_OE_REG DDRE 00079 #elif (SPPI0_CS0_AVRPORT == AVRPORTF) 00080 #define SPPI0_CS0_SOD_REG PORTF 00081 #define SPPI0_CS0_OE_REG DDRF 00082 #elif (SPPI0_CS0_AVRPORT == AVRPORTG) 00083 #define SPPI0_CS0_SOD_REG PORTG 00084 #define SPPI0_CS0_OE_REG DDRG 00085 #elif (SPPI0_CS0_AVRPORT == AVRPORTH) 00086 #define SPPI0_CS0_SOD_REG PORTH 00087 #define SPPI0_CS0_OE_REG DDRH 00088 #endif 00089 00091 #define SPPI0_CS0_ENA() sbi(SPPI0_CS0_OE_REG, SPPI0_CS0_BIT) 00092 00093 #define SPPI0_CS0_CLR() cbi(SPPI0_CS0_SOD_REG, SPPI0_CS0_BIT) 00094 00095 #define SPPI0_CS0_SET() sbi(SPPI0_CS0_SOD_REG, SPPI0_CS0_BIT) 00096 00097 #endif /* SPPI0_CS0_BIT */ 00098 00099 #ifdef SPPI0_CS1_BIT 00100 00101 #if (SPPI0_CS1_AVRPORT == AVRPORTB) 00102 #define SPPI0_CS1_SOD_REG PORTB 00103 #define SPPI0_CS1_OE_REG DDRB 00104 #elif (SPPI0_CS1_AVRPORT == AVRPORTD) 00105 #define SPPI0_CS1_SOD_REG PORTD 00106 #define SPPI0_CS1_OE_REG DDRD 00107 #elif (SPPI0_CS1_AVRPORT == AVRPORTE) 00108 #define SPPI0_CS1_SOD_REG PORTE 00109 #define SPPI0_CS1_OE_REG DDRE 00110 #elif (SPPI0_CS1_AVRPORT == AVRPORTF) 00111 #define SPPI0_CS1_SOD_REG PORTF 00112 #define SPPI0_CS1_OE_REG DDRF 00113 #elif (SPPI0_CS1_AVRPORT == AVRPORTG) 00114 #define SPPI0_CS1_SOD_REG PORTG 00115 #define SPPI0_CS1_OE_REG DDRG 00116 #elif (SPPI0_CS1_AVRPORT == AVRPORTH) 00117 #define SPPI0_CS1_SOD_REG PORTH 00118 #define SPPI0_CS1_OE_REG DDRH 00119 #endif 00120 00122 #define SPPI0_CS1_ENA() sbi(SPPI0_CS1_OE_REG, SPPI0_CS1_BIT) 00123 00124 #define SPPI0_CS1_CLR() cbi(SPPI0_CS1_SOD_REG, SPPI0_CS1_BIT) 00125 00126 #define SPPI0_CS1_SET() sbi(SPPI0_CS1_SOD_REG, SPPI0_CS1_BIT) 00127 00128 #endif /* SPPI0_CS1_BIT */ 00129 00130 #ifdef SPPI0_CS2_BIT 00131 00132 #if (SPPI0_CS2_AVRPORT == AVRPORTB) 00133 #define SPPI0_CS2_SOD_REG PORTB 00134 #define SPPI0_CS2_OE_REG DDRB 00135 #elif (SPPI0_CS2_AVRPORT == AVRPORTD) 00136 #define SPPI0_CS2_SOD_REG PORTD 00137 #define SPPI0_CS2_OE_REG DDRD 00138 #elif (SPPI0_CS2_AVRPORT == AVRPORTE) 00139 #define SPPI0_CS2_SOD_REG PORTE 00140 #define SPPI0_CS2_OE_REG DDRE 00141 #elif (SPPI0_CS2_AVRPORT == AVRPORTF) 00142 #define SPPI0_CS2_SOD_REG PORTF 00143 #define SPPI0_CS2_OE_REG DDRF 00144 #elif (SPPI0_CS2_AVRPORT == AVRPORTG) 00145 #define SPPI0_CS2_SOD_REG PORTG 00146 #define SPPI0_CS2_OE_REG DDRG 00147 #elif (SPPI0_CS2_AVRPORT == AVRPORTH) 00148 #define SPPI0_CS2_SOD_REG PORTH 00149 #define SPPI0_CS2_OE_REG DDRH 00150 #endif 00151 00153 #define SPPI0_CS2_ENA() sbi(SPPI0_CS2_OE_REG, SPPI0_CS2_BIT) 00154 00155 #define SPPI0_CS2_CLR() cbi(SPPI0_CS2_SOD_REG, SPPI0_CS2_BIT) 00156 00157 #define SPPI0_CS2_SET() sbi(SPPI0_CS2_SOD_REG, SPPI0_CS2_BIT) 00158 00159 #endif /* SPPI0_CS2_BIT */ 00160 00161 #ifdef SPPI0_CS3_BIT 00162 00163 #if (SPPI0_CS3_AVRPORT == AVRPORTB) 00164 #define SPPI0_CS3_SOD_REG PORTB 00165 #define SPPI0_CS3_OE_REG DDRB 00166 #elif (SPPI0_CS3_AVRPORT == AVRPORTD) 00167 #define SPPI0_CS3_SOD_REG PORTD 00168 #define SPPI0_CS3_OE_REG DDRD 00169 #elif (SPPI0_CS3_AVRPORT == AVRPORTE) 00170 #define SPPI0_CS3_SOD_REG PORTE 00171 #define SPPI0_CS3_OE_REG DDRE 00172 #elif (SPPI0_CS3_AVRPORT == AVRPORTF) 00173 #define SPPI0_CS3_SOD_REG PORTF 00174 #define SPPI0_CS3_OE_REG DDRF 00175 #elif (SPPI0_CS3_AVRPORT == AVRPORTG) 00176 #define SPPI0_CS3_SOD_REG PORTG 00177 #define SPPI0_CS3_OE_REG DDRG 00178 #elif (SPPI0_CS3_AVRPORT == AVRPORTH) 00179 #define SPPI0_CS3_SOD_REG PORTH 00180 #define SPPI0_CS3_OE_REG DDRH 00181 #endif 00182 00184 #define SPPI0_CS3_ENA() sbi(SPPI0_CS3_OE_REG, SPPI0_CS3_BIT) 00185 00186 #define SPPI0_CS3_CLR() cbi(SPPI0_CS3_SOD_REG, SPPI0_CS3_BIT) 00187 00188 #define SPPI0_CS3_SET() sbi(SPPI0_CS3_SOD_REG, SPPI0_CS3_BIT) 00189 00190 #endif /* SPPI0_CS3_BIT */ 00191 00192 #ifdef SPPI0_RST0_BIT 00193 00194 #if (SPPI0_RST0_AVRPORT == AVRPORTB) 00195 #define SPPI0_RST0_SOD_REG PORTB 00196 #define SPPI0_RST0_OE_REG DDRB 00197 #elif (SPPI0_RST0_AVRPORT == AVRPORTD) 00198 #define SPPI0_RST0_SOD_REG PORTD 00199 #define SPPI0_RST0_OE_REG DDRD 00200 #elif (SPPI0_RST0_AVRPORT == AVRPORTE) 00201 #define SPPI0_RST0_SOD_REG PORTE 00202 #define SPPI0_RST0_OE_REG DDRE 00203 #elif (SPPI0_RST0_AVRPORT == AVRPORTF) 00204 #define SPPI0_RST0_SOD_REG PORTF 00205 #define SPPI0_RST0_OE_REG DDRF 00206 #elif (SPPI0_RST0_AVRPORT == AVRPORTG) 00207 #define SPPI0_RST0_SOD_REG PORTG 00208 #define SPPI0_RST0_OE_REG DDRG 00209 #elif (SPPI0_RST0_AVRPORT == AVRPORTH) 00210 #define SPPI0_RST0_SOD_REG PORTH 00211 #define SPPI0_RST0_OE_REG DDRH 00212 #endif 00213 00215 #define SPPI0_RST0_ENA() sbi(SPPI0_RST0_OE_REG, SPPI0_RST0_BIT) 00216 00217 #define SPPI0_RST0_CLR() cbi(SPPI0_RST0_SOD_REG, SPPI0_RST0_BIT) 00218 00219 #define SPPI0_RST0_SET() sbi(SPPI0_RST0_SOD_REG, SPPI0_RST0_BIT) 00220 00221 #endif /* SPPI0_RST0_BIT */ 00222 00223 #ifdef SPPI0_RST1_BIT 00224 00225 #if (SPPI0_RST1_AVRPORT == AVRPORTB) 00226 #define SPPI0_RST1_SOD_REG PORTB 00227 #define SPPI0_RST1_OE_REG DDRB 00228 #elif (SPPI0_RST1_AVRPORT == AVRPORTD) 00229 #define SPPI0_RST1_SOD_REG PORTD 00230 #define SPPI0_RST1_OE_REG DDRD 00231 #elif (SPPI0_RST1_AVRPORT == AVRPORTE) 00232 #define SPPI0_RST1_SOD_REG PORTE 00233 #define SPPI0_RST1_OE_REG DDRE 00234 #elif (SPPI0_RST1_AVRPORT == AVRPORTF) 00235 #define SPPI0_RST1_SOD_REG PORTF 00236 #define SPPI0_RST1_OE_REG DDRF 00237 #elif (SPPI0_RST1_AVRPORT == AVRPORTG) 00238 #define SPPI0_RST1_SOD_REG PORTG 00239 #define SPPI0_RST1_OE_REG DDRG 00240 #elif (SPPI0_RST1_AVRPORT == AVRPORTH) 00241 #define SPPI0_RST1_SOD_REG PORTH 00242 #define SPPI0_RST1_OE_REG DDRH 00243 #endif 00244 00246 #define SPPI0_RST1_ENA() sbi(SPPI0_RST1_OE_REG, SPPI0_RST1_BIT) 00247 00248 #define SPPI0_RST1_CLR() cbi(SPPI0_RST1_SOD_REG, SPPI0_RST1_BIT) 00249 00250 #define SPPI0_RST1_SET() sbi(SPPI0_RST1_SOD_REG, SPPI0_RST1_BIT) 00251 00252 #endif /* SPPI0_RST1_BIT */ 00253 00254 #ifdef SPPI0_RST2_BIT 00255 00256 #if (SPPI0_RST2_AVRPORT == AVRPORTB) 00257 #define SPPI0_RST2_SOD_REG PORTB 00258 #define SPPI0_RST2_OE_REG DDRB 00259 #elif (SPPI0_RST2_AVRPORT == AVRPORTD) 00260 #define SPPI0_RST2_SOD_REG PORTD 00261 #define SPPI0_RST2_OE_REG DDRD 00262 #elif (SPPI0_RST2_AVRPORT == AVRPORTE) 00263 #define SPPI0_RST2_SOD_REG PORTE 00264 #define SPPI0_RST2_OE_REG DDRE 00265 #elif (SPPI0_RST2_AVRPORT == AVRPORTF) 00266 #define SPPI0_RST2_SOD_REG PORTF 00267 #define SPPI0_RST2_OE_REG DDRF 00268 #elif (SPPI0_RST2_AVRPORT == AVRPORTG) 00269 #define SPPI0_RST2_SOD_REG PORTG 00270 #define SPPI0_RST2_OE_REG DDRG 00271 #elif (SPPI0_RST2_AVRPORT == AVRPORTH) 00272 #define SPPI0_RST2_SOD_REG PORTH 00273 #define SPPI0_RST2_OE_REG DDRH 00274 #endif 00275 00277 #define SPPI0_RST2_ENA() sbi(SPPI0_RST2_OE_REG, SPPI0_RST2_BIT) 00278 00279 #define SPPI0_RST2_CLR() cbi(SPPI0_RST2_SOD_REG, SPPI0_RST2_BIT) 00280 00281 #define SPPI0_RST2_SET() sbi(SPPI0_RST2_SOD_REG, SPPI0_RST2_BIT) 00282 00283 #endif /* SPPI0_RST2_BIT */ 00284 00285 #ifdef SPPI0_RST3_BIT 00286 00287 #if (SPPI0_RST3_AVRPORT == AVRPORTB) 00288 #define SPPI0_RST3_SOD_REG PORTB 00289 #define SPPI0_RST3_OE_REG DDRB 00290 #elif (SPPI0_RST3_AVRPORT == AVRPORTD) 00291 #define SPPI0_RST3_SOD_REG PORTD 00292 #define SPPI0_RST3_OE_REG DDRD 00293 #elif (SPPI0_RST3_AVRPORT == AVRPORTE) 00294 #define SPPI0_RST3_SOD_REG PORTE 00295 #define SPPI0_RST3_OE_REG DDRE 00296 #elif (SPPI0_RST3_AVRPORT == AVRPORTF) 00297 #define SPPI0_RST3_SOD_REG PORTF 00298 #define SPPI0_RST3_OE_REG DDRF 00299 #elif (SPPI0_RST3_AVRPORT == AVRPORTG) 00300 #define SPPI0_RST3_SOD_REG PORTG 00301 #define SPPI0_RST3_OE_REG DDRG 00302 #elif (SPPI0_RST3_AVRPORT == AVRPORTH) 00303 #define SPPI0_RST3_SOD_REG PORTH 00304 #define SPPI0_RST3_OE_REG DDRH 00305 #endif 00306 00308 #define SPPI0_RST3_ENA() sbi(SPPI0_RST3_OE_REG, SPPI0_RST3_BIT) 00309 00310 #define SPPI0_RST3_CLR() cbi(SPPI0_RST3_SOD_REG, SPPI0_RST3_BIT) 00311 00312 #define SPPI0_RST3_SET() sbi(SPPI0_RST3_SOD_REG, SPPI0_RST3_BIT) 00313 00314 #endif /* SPPI0_RST3_BIT */ 00315 00316 00317 #else /* MCU */ 00318 /* 00319 * AT91 implementation. 00320 * ====================================== 00321 */ 00322 00323 #ifdef SPPI0_CS0_BIT 00324 00325 #if !defined(SPPI0_CS0_PIO_ID) 00326 #define SPPI0_CS0_PE_REG PIO_PER 00327 #define SPPI0_CS0_OE_REG PIO_OER 00328 #define SPPI0_CS0_COD_REG PIO_CODR 00329 #define SPPI0_CS0_SOD_REG PIO_SODR 00330 #elif SPPI0_CS0_PIO_ID == PIO_ID 00331 #define SPPI0_CS0_PE_REG PIO_PER 00332 #define SPPI0_CS0_OE_REG PIO_OER 00333 #define SPPI0_CS0_COD_REG PIO_CODR 00334 #define SPPI0_CS0_SOD_REG PIO_SODR 00335 #elif SPPI0_CS0_PIO_ID == PIOA_ID 00336 #define SPPI0_CS0_PE_REG PIOA_PER 00337 #define SPPI0_CS0_OE_REG PIOA_OER 00338 #define SPPI0_CS0_COD_REG PIOA_CODR 00339 #define SPPI0_CS0_SOD_REG PIOA_SODR 00340 #elif SPPI0_CS0_PIO_ID == PIOB_ID 00341 #define SPPI0_CS0_PE_REG PIOB_PER 00342 #define SPPI0_CS0_OE_REG PIOB_OER 00343 #define SPPI0_CS0_COD_REG PIOB_CODR 00344 #define SPPI0_CS0_SOD_REG PIOB_SODR 00345 #elif SPPI0_CS0_PIO_ID == PIOC_ID 00346 #define SPPI0_CS0_PE_REG PIOC_PER 00347 #define SPPI0_CS0_OE_REG PIOC_OER 00348 #define SPPI0_CS0_COD_REG PIOC_CODR 00349 #define SPPI0_CS0_SOD_REG PIOC_SODR 00350 #endif 00351 00353 #define SPPI0_CS0_ENA() \ 00354 outr(SPPI0_CS0_PE_REG, _BV(SPPI0_CS0_BIT)); \ 00355 outr(SPPI0_CS0_OE_REG, _BV(SPPI0_CS0_BIT)) 00356 00357 #define SPPI0_CS0_CLR() outr(SPPI0_CS0_COD_REG, _BV(SPPI0_CS0_BIT)) 00358 00359 #define SPPI0_CS0_SET() outr(SPPI0_CS0_SOD_REG, _BV(SPPI0_CS0_BIT)) 00360 00361 #endif /* SPPI0_CS0_BIT */ 00362 00363 #ifdef SPPI0_CS1_BIT 00364 00365 #if !defined(SPPI0_CS1_PIO_ID) 00366 #define SPPI0_CS1_PE_REG PIO_PER 00367 #define SPPI0_CS1_OE_REG PIO_OER 00368 #define SPPI0_CS1_COD_REG PIO_CODR 00369 #define SPPI0_CS1_SOD_REG PIO_SODR 00370 #elif SPPI0_CS1_PIO_ID == PIO_ID 00371 #define SPPI0_CS1_PE_REG PIO_PER 00372 #define SPPI0_CS1_OE_REG PIO_OER 00373 #define SPPI0_CS1_COD_REG PIO_CODR 00374 #define SPPI0_CS1_SOD_REG PIO_SODR 00375 #elif SPPI0_CS1_PIO_ID == PIOA_ID 00376 #define SPPI0_CS1_PE_REG PIOA_PER 00377 #define SPPI0_CS1_OE_REG PIOA_OER 00378 #define SPPI0_CS1_COD_REG PIOA_CODR 00379 #define SPPI0_CS1_SOD_REG PIOA_SODR 00380 #elif SPPI0_CS1_PIO_ID == PIOB_ID 00381 #define SPPI0_CS1_PE_REG PIOB_PER 00382 #define SPPI0_CS1_OE_REG PIOB_OER 00383 #define SPPI0_CS1_COD_REG PIOB_CODR 00384 #define SPPI0_CS1_SOD_REG PIOB_SODR 00385 #elif SPPI0_CS1_PIO_ID == PIOC_ID 00386 #define SPPI0_CS1_PE_REG PIOC_PER 00387 #define SPPI0_CS1_OE_REG PIOC_OER 00388 #define SPPI0_CS1_COD_REG PIOC_CODR 00389 #define SPPI0_CS1_SOD_REG PIOC_SODR 00390 #endif 00391 00393 #define SPPI0_CS1_ENA() \ 00394 outr(SPPI0_CS1_PE_REG, _BV(SPPI0_CS1_BIT)); \ 00395 outr(SPPI0_CS1_OE_REG, _BV(SPPI0_CS1_BIT)) 00396 00397 #define SPPI0_CS1_CLR() outr(SPPI0_CS1_COD_REG, _BV(SPPI0_CS1_BIT)) 00398 00399 #define SPPI0_CS1_SET() outr(SPPI0_CS1_SOD_REG, _BV(SPPI0_CS1_BIT)) 00400 00401 #endif /* SPPI0_CS1_BIT */ 00402 00403 #ifdef SPPI0_CS2_BIT 00404 00405 #if !defined(SPPI0_CS2_PIO_ID) 00406 #define SPPI0_CS2_PE_REG PIO_PER 00407 #define SPPI0_CS2_OE_REG PIO_OER 00408 #define SPPI0_CS2_COD_REG PIO_CODR 00409 #define SPPI0_CS2_SOD_REG PIO_SODR 00410 #elif SPPI0_CS2_PIO_ID == PIO_ID 00411 #define SPPI0_CS2_PE_REG PIO_PER 00412 #define SPPI0_CS2_OE_REG PIO_OER 00413 #define SPPI0_CS2_COD_REG PIO_CODR 00414 #define SPPI0_CS2_SOD_REG PIO_SODR 00415 #elif SPPI0_CS2_PIO_ID == PIOA_ID 00416 #define SPPI0_CS2_PE_REG PIOA_PER 00417 #define SPPI0_CS2_OE_REG PIOA_OER 00418 #define SPPI0_CS2_COD_REG PIOA_CODR 00419 #define SPPI0_CS2_SOD_REG PIOA_SODR 00420 #elif SPPI0_CS2_PIO_ID == PIOB_ID 00421 #define SPPI0_CS2_PE_REG PIOB_PER 00422 #define SPPI0_CS2_OE_REG PIOB_OER 00423 #define SPPI0_CS2_COD_REG PIOB_CODR 00424 #define SPPI0_CS2_SOD_REG PIOB_SODR 00425 #elif SPPI0_CS2_PIO_ID == PIOC_ID 00426 #define SPPI0_CS2_PE_REG PIOC_PER 00427 #define SPPI0_CS2_OE_REG PIOC_OER 00428 #define SPPI0_CS2_COD_REG PIOC_CODR 00429 #define SPPI0_CS2_SOD_REG PIOC_SODR 00430 #endif 00431 00433 #define SPPI0_CS2_ENA() \ 00434 outr(SPPI0_CS2_PE_REG, _BV(SPPI0_CS2_BIT)); \ 00435 outr(SPPI0_CS2_OE_REG, _BV(SPPI0_CS2_BIT)) 00436 00437 #define SPPI0_CS2_CLR() outr(SPPI0_CS2_COD_REG, _BV(SPPI0_CS2_BIT)) 00438 00439 #define SPPI0_CS2_SET() outr(SPPI0_CS2_SOD_REG, _BV(SPPI0_CS2_BIT)) 00440 00441 #endif /* SPPI0_CS2_BIT */ 00442 00443 #ifdef SPPI0_CS3_BIT 00444 00445 #if !defined(SPPI0_CS3_PIO_ID) 00446 #define SPPI0_CS3_PE_REG PIO_PER 00447 #define SPPI0_CS3_OE_REG PIO_OER 00448 #define SPPI0_CS3_COD_REG PIO_CODR 00449 #define SPPI0_CS3_SOD_REG PIO_SODR 00450 #elif SPPI0_CS3_PIO_ID == PIO_ID 00451 #define SPPI0_CS3_PE_REG PIO_PER 00452 #define SPPI0_CS3_OE_REG PIO_OER 00453 #define SPPI0_CS3_COD_REG PIO_CODR 00454 #define SPPI0_CS3_SOD_REG PIO_SODR 00455 #elif SPPI0_CS3_PIO_ID == PIOA_ID 00456 #define SPPI0_CS3_PE_REG PIOA_PER 00457 #define SPPI0_CS3_OE_REG PIOA_OER 00458 #define SPPI0_CS3_COD_REG PIOA_CODR 00459 #define SPPI0_CS3_SOD_REG PIOA_SODR 00460 #elif SPPI0_CS3_PIO_ID == PIOB_ID 00461 #define SPPI0_CS3_PE_REG PIOB_PER 00462 #define SPPI0_CS3_OE_REG PIOB_OER 00463 #define SPPI0_CS3_COD_REG PIOB_CODR 00464 #define SPPI0_CS3_SOD_REG PIOB_SODR 00465 #elif SPPI0_CS3_PIO_ID == PIOC_ID 00466 #define SPPI0_CS3_PE_REG PIOC_PER 00467 #define SPPI0_CS3_OE_REG PIOC_OER 00468 #define SPPI0_CS3_COD_REG PIOC_CODR 00469 #define SPPI0_CS3_SOD_REG PIOC_SODR 00470 #endif 00471 00473 #define SPPI0_CS3_ENA() \ 00474 outr(SPPI0_CS3_PE_REG, _BV(SPPI0_CS3_BIT)); \ 00475 outr(SPPI0_CS3_OE_REG, _BV(SPPI0_CS3_BIT)) 00476 00477 #define SPPI0_CS3_CLR() outr(SPPI0_CS3_COD_REG, _BV(SPPI0_CS3_BIT)) 00478 00479 #define SPPI0_CS3_SET() outr(SPPI0_CS3_SOD_REG, _BV(SPPI0_CS3_BIT)) 00480 00481 #endif /* SPPI0_CS3_BIT */ 00482 00483 #ifdef SPPI0_RST0_BIT 00484 00485 #if !defined(SPPI0_RST0_PIO_ID) 00486 #define SPPI0_RST0_PE_REG PIO_PER 00487 #define SPPI0_RST0_OE_REG PIO_OER 00488 #define SPPI0_RST0_COD_REG PIO_CODR 00489 #define SPPI0_RST0_SOD_REG PIO_SODR 00490 #elif SPPI0_RST0_PIO_ID == PIO_ID 00491 #define SPPI0_RST0_PE_REG PIO_PER 00492 #define SPPI0_RST0_OE_REG PIO_OER 00493 #define SPPI0_RST0_COD_REG PIO_CODR 00494 #define SPPI0_RST0_SOD_REG PIO_SODR 00495 #elif SPPI0_RST0_PIO_ID == PIOA_ID 00496 #define SPPI0_RST0_PE_REG PIOA_PER 00497 #define SPPI0_RST0_OE_REG PIOA_OER 00498 #define SPPI0_RST0_COD_REG PIOA_CODR 00499 #define SPPI0_RST0_SOD_REG PIOA_SODR 00500 #elif SPPI0_RST0_PIO_ID == PIOB_ID 00501 #define SPPI0_RST0_PE_REG PIOB_PER 00502 #define SPPI0_RST0_OE_REG PIOB_OER 00503 #define SPPI0_RST0_COD_REG PIOB_CODR 00504 #define SPPI0_RST0_SOD_REG PIOB_SODR 00505 #elif SPPI0_RST0_PIO_ID == PIOC_ID 00506 #define SPPI0_RST0_PE_REG PIOC_PER 00507 #define SPPI0_RST0_OE_REG PIOC_OER 00508 #define SPPI0_RST0_COD_REG PIOC_CODR 00509 #define SPPI0_RST0_SOD_REG PIOC_SODR 00510 #endif 00511 00513 #define SPPI0_RST0_ENA() \ 00514 outr(SPPI0_RST0_PE_REG, _BV(SPPI0_RST0_BIT)); \ 00515 outr(SPPI0_RST0_OE_REG, _BV(SPPI0_RST0_BIT)) 00516 00517 #define SPPI0_RST0_CLR() outr(SPPI0_RST0_COD_REG, _BV(SPPI0_RST0_BIT)) 00518 00519 #define SPPI0_RST0_SET() outr(SPPI0_RST0_SOD_REG, _BV(SPPI0_RST0_BIT)) 00520 00521 #endif /* SPPI0_RST0_BIT */ 00522 00523 #ifdef SPPI0_RST1_BIT 00524 00525 #if !defined(SPPI0_RST1_PIO_ID) 00526 #define SPPI0_RST1_PE_REG PIO_PER 00527 #define SPPI0_RST1_OE_REG PIO_OER 00528 #define SPPI0_RST1_COD_REG PIO_CODR 00529 #define SPPI0_RST1_SOD_REG PIO_SODR 00530 #elif SPPI0_RST1_PIO_ID == PIO_ID 00531 #define SPPI0_RST1_PE_REG PIO_PER 00532 #define SPPI0_RST1_OE_REG PIO_OER 00533 #define SPPI0_RST1_COD_REG PIO_CODR 00534 #define SPPI0_RST1_SOD_REG PIO_SODR 00535 #elif SPPI0_RST1_PIO_ID == PIOA_ID 00536 #define SPPI0_RST1_PE_REG PIOA_PER 00537 #define SPPI0_RST1_OE_REG PIOA_OER 00538 #define SPPI0_RST1_COD_REG PIOA_CODR 00539 #define SPPI0_RST1_SOD_REG PIOA_SODR 00540 #elif SPPI0_RST1_PIO_ID == PIOB_ID 00541 #define SPPI0_RST1_PE_REG PIOB_PER 00542 #define SPPI0_RST1_OE_REG PIOB_OER 00543 #define SPPI0_RST1_COD_REG PIOB_CODR 00544 #define SPPI0_RST1_SOD_REG PIOB_SODR 00545 #elif SPPI0_RST1_PIO_ID == PIOC_ID 00546 #define SPPI0_RST1_PE_REG PIOC_PER 00547 #define SPPI0_RST1_OE_REG PIOC_OER 00548 #define SPPI0_RST1_COD_REG PIOC_CODR 00549 #define SPPI0_RST1_SOD_REG PIOC_SODR 00550 #endif 00551 00553 #define SPPI0_RST1_ENA() \ 00554 outr(SPPI0_RST1_PE_REG, _BV(SPPI0_RST1_BIT)); \ 00555 outr(SPPI0_RST1_OE_REG, _BV(SPPI0_RST1_BIT)) 00556 00557 #define SPPI0_RST1_CLR() outr(SPPI0_RST1_COD_REG, _BV(SPPI0_RST1_BIT)) 00558 00559 #define SPPI0_RST1_SET() outr(SPPI0_RST1_SOD_REG, _BV(SPPI0_RST1_BIT)) 00560 00561 #endif /* SPPI0_RST1_BIT */ 00562 00563 #ifdef SPPI0_RST2_BIT 00564 00565 #if !defined(SPPI0_RST2_PIO_ID) 00566 #define SPPI0_RST2_PE_REG PIO_PER 00567 #define SPPI0_RST2_OE_REG PIO_OER 00568 #define SPPI0_RST2_COD_REG PIO_CODR 00569 #define SPPI0_RST2_SOD_REG PIO_SODR 00570 #elif SPPI0_RST2_PIO_ID == PIO_ID 00571 #define SPPI0_RST2_PE_REG PIO_PER 00572 #define SPPI0_RST2_OE_REG PIO_OER 00573 #define SPPI0_RST2_COD_REG PIO_CODR 00574 #define SPPI0_RST2_SOD_REG PIO_SODR 00575 #elif SPPI0_RST2_PIO_ID == PIOA_ID 00576 #define SPPI0_RST2_PE_REG PIOA_PER 00577 #define SPPI0_RST2_OE_REG PIOA_OER 00578 #define SPPI0_RST2_COD_REG PIOA_CODR 00579 #define SPPI0_RST2_SOD_REG PIOA_SODR 00580 #elif SPPI0_RST2_PIO_ID == PIOB_ID 00581 #define SPPI0_RST2_PE_REG PIOB_PER 00582 #define SPPI0_RST2_OE_REG PIOB_OER 00583 #define SPPI0_RST2_COD_REG PIOB_CODR 00584 #define SPPI0_RST2_SOD_REG PIOB_SODR 00585 #elif SPPI0_RST2_PIO_ID == PIOC_ID 00586 #define SPPI0_RST2_PE_REG PIOC_PER 00587 #define SPPI0_RST2_OE_REG PIOC_OER 00588 #define SPPI0_RST2_COD_REG PIOC_CODR 00589 #define SPPI0_RST2_SOD_REG PIOC_SODR 00590 #endif 00591 00593 #define SPPI0_RST2_ENA() \ 00594 outr(SPPI0_RST2_PE_REG, _BV(SPPI0_RST2_BIT)); \ 00595 outr(SPPI0_RST2_OE_REG, _BV(SPPI0_RST2_BIT)) 00596 00597 #define SPPI0_RST2_CLR() outr(SPPI0_RST2_COD_REG, _BV(SPPI0_RST2_BIT)) 00598 00599 #define SPPI0_RST2_SET() outr(SPPI0_RST2_SOD_REG, _BV(SPPI0_RST2_BIT)) 00600 00601 #endif /* SPPI0_RST2_BIT */ 00602 00603 #ifdef SPPI0_RST3_BIT 00604 00605 #if !defined(SPPI0_RST3_PIO_ID) 00606 #define SPPI0_RST3_PE_REG PIO_PER 00607 #define SPPI0_RST3_OE_REG PIO_OER 00608 #define SPPI0_RST3_COD_REG PIO_CODR 00609 #define SPPI0_RST3_SOD_REG PIO_SODR 00610 #elif SPPI0_RST3_PIO_ID == PIO_ID 00611 #define SPPI0_RST3_PE_REG PIO_PER 00612 #define SPPI0_RST3_OE_REG PIO_OER 00613 #define SPPI0_RST3_COD_REG PIO_CODR 00614 #define SPPI0_RST3_SOD_REG PIO_SODR 00615 #elif SPPI0_RST3_PIO_ID == PIOA_ID 00616 #define SPPI0_RST3_PE_REG PIOA_PER 00617 #define SPPI0_RST3_OE_REG PIOA_OER 00618 #define SPPI0_RST3_COD_REG PIOA_CODR 00619 #define SPPI0_RST3_SOD_REG PIOA_SODR 00620 #elif SPPI0_RST3_PIO_ID == PIOB_ID 00621 #define SPPI0_RST3_PE_REG PIOB_PER 00622 #define SPPI0_RST3_OE_REG PIOB_OER 00623 #define SPPI0_RST3_COD_REG PIOB_CODR 00624 #define SPPI0_RST3_SOD_REG PIOB_SODR 00625 #elif SPPI0_RST3_PIO_ID == PIOC_ID 00626 #define SPPI0_RST3_PE_REG PIOC_PER 00627 #define SPPI0_RST3_OE_REG PIOC_OER 00628 #define SPPI0_RST3_COD_REG PIOC_CODR 00629 #define SPPI0_RST3_SOD_REG PIOC_SODR 00630 #endif 00631 00633 #define SPPI0_RST3_ENA() \ 00634 outr(SPPI0_RST3_PE_REG, _BV(SPPI0_RST3_BIT)); \ 00635 outr(SPPI0_RST3_OE_REG, _BV(SPPI0_RST3_BIT)) 00636 00637 #define SPPI0_RST3_CLR() outr(SPPI0_RST3_COD_REG, _BV(SPPI0_RST3_BIT)) 00638 00639 #define SPPI0_RST3_SET() outr(SPPI0_RST3_SOD_REG, _BV(SPPI0_RST3_BIT)) 00640 00641 #endif /* SPPI0_RST3_BIT */ 00642 00643 #endif /* MCU */ 00644 00645 __BEGIN_DECLS 00646 /* Function prototypes */ 00647 00648 extern int Sppi0SetMode(ureg_t ix, ureg_t mode); 00649 extern void Sppi0SetSpeed(ureg_t ix, uint32_t rate); 00650 extern void Sppi0Enable(ureg_t ix); 00651 extern void Sppi0ChipReset(ureg_t ix, uint8_t hi); 00652 extern void Sppi0ChipSelect(ureg_t ix, uint8_t hi); 00653 extern void Sppi0SelectDevice(ureg_t ix); 00654 extern void Sppi0DeselectDevice(ureg_t ix); 00655 extern void Sppi0NegSelectDevice(ureg_t ix); 00656 extern void Sppi0NegDeselectDevice(ureg_t ix); 00657 extern uint8_t Sppi0Byte(uint8_t data); 00658 extern void Sppi0Transact(CONST void *wdata, void *rdata, size_t len); 00659 00660 __END_DECLS 00661 /* End of prototypes */ 00662 00663 #endif