Nut/OS  4.10.3
API Reference
usart0at91.c
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00001 /*
00002  * Copyright (C) 2005 by egnite Software GmbH
00003  * Copyright 2009 by egnite GmbH
00004  *
00005  * All rights reserved.
00006  *
00007  * Redistribution and use in source and binary forms, with or without
00008  * modification, are permitted provided that the following conditions
00009  * are met:
00010  *
00011  * 1. Redistributions of source code must retain the above copyright
00012  *    notice, this list of conditions and the following disclaimer.
00013  * 2. Redistributions in binary form must reproduce the above copyright
00014  *    notice, this list of conditions and the following disclaimer in the
00015  *    documentation and/or other materials provided with the distribution.
00016  * 3. Neither the name of the copyright holders nor the names of
00017  *    contributors may be used to endorse or promote products derived
00018  *    from this software without specific prior written permission.
00019  *
00020  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
00021  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00022  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00023  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
00024  * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
00025  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
00026  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
00027  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
00028  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00029  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
00030  * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
00031  * SUCH DAMAGE.
00032  *
00033  * For additional information see http://www.ethernut.de/
00034  */
00035 
00036 /*
00037  * $Id: usart0at91.c 3449 2011-05-31 19:08:15Z mifi $
00038  */
00039 
00040 #include <cfg/os.h>
00041 #include <cfg/clock.h>
00042 #include <cfg/arch.h>
00043 #include <cfg/uart.h>
00044 #include <cfg/arch/gpio.h>
00045 
00046 #include <string.h>
00047 
00048 #include <sys/atom.h>
00049 #include <sys/event.h>
00050 #include <sys/timer.h>
00051 
00052 #include <dev/irqreg.h>
00053 #include <dev/gpio.h>
00054 #include <dev/usartat91.h>
00055 
00056 #ifndef NUT_CPU_FREQ
00057 #ifdef NUT_PLL_CPUCLK
00058 #include <dev/cy2239x.h>
00059 #else /* !NUT_PLL_CPUCLK */
00060 #define NUT_CPU_FREQ    73728000UL
00061 #endif /* !NUT_PLL_CPUCLK */
00062 #endif /* !NUT_CPU_FREQ */
00063 
00064 /*
00065  * Local function prototypes.
00066  */
00067 static uint32_t At91UsartGetSpeed(void);
00068 static int At91UsartSetSpeed(uint32_t rate);
00069 static uint8_t At91UsartGetDataBits(void);
00070 static int At91UsartSetDataBits(uint8_t bits);
00071 static uint8_t At91UsartGetParity(void);
00072 static int At91UsartSetParity(uint8_t mode);
00073 static uint8_t At91UsartGetStopBits(void);
00074 static int At91UsartSetStopBits(uint8_t bits);
00075 static uint32_t At91UsartGetFlowControl(void);
00076 static int At91UsartSetFlowControl(uint32_t flags);
00077 static uint32_t At91UsartGetStatus(void);
00078 static int At91UsartSetStatus(uint32_t flags);
00079 static uint8_t At91UsartGetClockMode(void);
00080 static int At91UsartSetClockMode(uint8_t mode);
00081 static void At91UsartTxStart(void);
00082 static void At91UsartRxStart(void);
00083 static int At91UsartInit(void);
00084 static int At91UsartDeinit(void);
00085 
00090 
00094 static USARTDCB dcb_usart0 = {
00095     0,                          /* dcb_modeflags */
00096     0,                          /* dcb_statusflags */
00097     0,                          /* dcb_rtimeout */
00098     0,                          /* dcb_wtimeout */
00099     {0, 0, 0, 0, 0, 0, 0, 0},   /* dcb_tx_rbf */
00100     {0, 0, 0, 0, 0, 0, 0, 0},   /* dcb_rx_rbf */
00101     0,                          /* dbc_last_eol */
00102     At91UsartInit,              /* dcb_init */
00103     At91UsartDeinit,            /* dcb_deinit */
00104     At91UsartTxStart,           /* dcb_tx_start */
00105     At91UsartRxStart,           /* dcb_rx_start */
00106     At91UsartSetFlowControl,    /* dcb_set_flow_control */
00107     At91UsartGetFlowControl,    /* dcb_get_flow_control */
00108     At91UsartSetSpeed,          /* dcb_set_speed */
00109     At91UsartGetSpeed,          /* dcb_get_speed */
00110     At91UsartSetDataBits,       /* dcb_set_data_bits */
00111     At91UsartGetDataBits,       /* dcb_get_data_bits */
00112     At91UsartSetParity,         /* dcb_set_parity */
00113     At91UsartGetParity,         /* dcb_get_parity */
00114     At91UsartSetStopBits,       /* dcb_set_stop_bits */
00115     At91UsartGetStopBits,       /* dcb_get_stop_bits */
00116     At91UsartSetStatus,         /* dcb_set_status */
00117     At91UsartGetStatus,         /* dcb_get_status */
00118     At91UsartSetClockMode,      /* dcb_set_clock_mode */
00119     At91UsartGetClockMode,      /* dcb_get_clock_mode */
00120 };
00121 
00137 NUTDEVICE devUsartAt910 = {
00138     0,                          /* Pointer to next device, dev_next. */
00139     {'u', 'a', 'r', 't', '0', 0, 0, 0, 0},    /* Unique device name, dev_name. */
00140     IFTYP_CHAR,                 /* Type of device, dev_type. */
00141     0,                          /* Base address, dev_base (not used). */
00142     0,                          /* First interrupt number, dev_irq (not used). */
00143     0,                          /* Interface control block, dev_icb (not used). */
00144     &dcb_usart0,                /* Driver control block, dev_dcb. */
00145     UsartInit,                  /* Driver initialization routine, dev_init. */
00146     UsartIOCtl,                 /* Driver specific control function, dev_ioctl. */
00147     UsartRead,                  /* Read from device, dev_read. */
00148     UsartWrite,                 /* Write to device, dev_write. */
00149     UsartOpen,                  /* Open a device or file, dev_open. */
00150     UsartClose,                 /* Close a device or file, dev_close. */
00151     UsartSize                   /* Request file size, dev_size. */
00152 };
00153 
00157 
00158 /* Modem control includes hardware handshake. */
00159 #if defined(UART0_MODEM_CONTROL)
00160 #define UART_MODEM_CONTROL
00161 #define UART_HARDWARE_HANDSHAKE
00162 #elif defined(UART0_HARDWARE_HANDSHAKE)
00163 #define UART_HARDWARE_HANDSHAKE
00164 #endif
00165 
00166 /*
00167 ** SAM9260 and SAM9XE pins.
00168 */
00169 #if defined(MCU_AT91SAM9260) || defined(MCU_AT91SAM9XE)
00170 
00171 #define UART_RXTX_PINS  (_BV(PB5_RXD0_A) | _BV(PB4_TXD0_A))
00172 #define UART_HDX_PIN    _BV(PB26_RTS0_A)
00173 #define UART_RTS_PIN    _BV(PB26_RTS0_A)
00174 #define UART_CTS_PIN    _BV(PB27_CTS0_A)
00175 #define UART_MODEM_PINS (_BV(PB24_DTR0_A) | _BV(PB22_DSR0_A) | _BV(PB23_DCD0_A) | _BV(PB25_RI0_A))
00176 
00177 #define UART_RXTX_PINS_ENABLE()     outr(PIOB_ASR, UART_RXTX_PINS); \
00178                                     outr(PIOB_PDR, UART_RXTX_PINS)
00179 
00180 #if defined(UART_HARDWARE_HANDSHAKE)
00181 #define UART_HDX_PIN_ENABLE()       outr(PIOB_ASR, UART_HDX_PIN); \
00182                                     outr(PIOB_PDR, UART_HDX_PIN)
00183 #define UART_RTS_PIN_ENABLE()       outr(PIOB_ASR, UART_RTS_PIN); \
00184                                     outr(PIOB_PDR, UART_RTS_PIN)
00185 #define UART_CTS_PIN_ENABLE()       outr(PIOB_ASR, UART_CTS_PIN); \
00186                                     outr(PIOB_PDR, UART_CTS_PIN)
00187 #endif
00188 
00189 #if defined(UART_MODEM_CONTROL)
00190 #define UART_MODEM_PINS_ENABLE()    outr(PIOB_ASR, UART_MODEM_PINS); \
00191                                     outr(PIOB_PDR, UART_MODEM_PINS)
00192 #endif
00193 
00194 /*
00195 ** SAM7S and SAM7SE pins.
00196 */
00197 #elif defined(MCU_AT91SAM7S) || defined(MCU_AT91SAM7SE)
00198 
00199 #define UART_RXTX_PINS  (_BV(PA5_RXD0_A) | _BV(PA6_TXD0_A))
00200 #define UART_HDX_PIN    _BV(PA7_RTS0_A)
00201 #define UART_RTS_PIN    _BV(PA7_RTS0_A)
00202 #define UART_CTS_PIN    _BV(PA8_CTS0_A)
00203 
00204 #define UART_RXTX_PINS_ENABLE() outr(PIOA_ASR, UART_RXTX_PINS); \
00205                                 outr(PIOA_PDR, UART_RXTX_PINS)
00206 
00207 #if defined(UART_HARDWARE_HANDSHAKE)
00208 #define UART_HDX_PIN_ENABLE()   outr(PIOA_ASR, UART_HDX_PIN); \
00209                                 outr(PIOA_PDR, UART_HDX_PIN)
00210 #define UART_RTS_PIN_ENABLE()   outr(PIOA_ASR, UART_RTS_PIN); \
00211                                 outr(PIOA_PDR, UART_RTS_PIN)
00212 #define UART_CTS_PIN_ENABLE()   outr(PIOA_ASR, UART_CTS_PIN); \
00213                                 outr(PIOA_PDR, UART_CTS_PIN)
00214 #endif
00215 
00216 /*
00217 ** AT91SAM9G45 pins.
00218 */
00219 #elif defined(MCU_AT91SAM9G45)
00220 
00221 #define UART_RXTX_PINS  (_BV(PB19_TXD0_A) | _BV(PB18_RXD0_A))
00222 #define UART_HDX_PIN    _BV(PB17_RTS0_B)
00223 #define UART_RTS_PIN    _BV(PB17_RTS0_B)
00224 #define UART_CTS_PIN    _BV(PB15_CTS0_B)
00225 
00226 #define UART_RXTX_PINS_ENABLE()     outr(PIOB_ASR, UART_RXTX_PINS); \
00227                                     outr(PIOB_PDR, UART_RXTX_PINS)
00228 
00229 #if defined(UART_HARDWARE_HANDSHAKE)
00230 #define UART_HDX_PIN_ENABLE()       outr(PIOD_BSR, UART_HDX_PIN); \
00231                                     outr(PIOD_PDR, UART_HDX_PIN)
00232 #define UART_RTS_PIN_ENABLE()       outr(PIOD_BSR, UART_RTS_PIN); \
00233                                     outr(PIOD_PDR, UART_RTS_PIN)
00234 #define UART_CTS_PIN_ENABLE()       outr(PIOD_BSR, UART_CTS_PIN); \
00235                                     outr(PIOD_PDR, UART_CTS_PIN)
00236 #endif
00237 
00238 
00239 /*
00240 ** SAM7X pins.
00241 */
00242 #elif defined(MCU_AT91SAM7X)
00243 
00244 #define UART_RXTX_PINS  (_BV(PA0_RXD0_A) | _BV(PA1_TXD0_A))
00245 #define UART_HDX_PIN    _BV(PA3_RTS0_A)
00246 #define UART_RTS_PIN    _BV(PA3_RTS0_A)
00247 #define UART_CTS_PIN    _BV(PA4_CTS0_A)
00248 
00249 #define UART_RXTX_PINS_ENABLE() outr(PIOA_ASR, UART_RXTX_PINS); \
00250                                 outr(PIOA_PDR, UART_RXTX_PINS)
00251 
00252 #if defined(UART_HARDWARE_HANDSHAKE)
00253 #define UART_HDX_PIN_ENABLE()   outr(PIOA_ASR, UART_HDX_PIN); \
00254                                 outr(PIOA_PDR, UART_HDX_PIN)
00255 #define UART_RTS_PIN_ENABLE()   outr(PIOA_ASR, UART_RTS_PIN); \
00256                                 outr(PIOA_PDR, UART_RTS_PIN)
00257 #define UART_CTS_PIN_ENABLE()   outr(PIOA_ASR, UART_CTS_PIN); \
00258                                 outr(PIOA_PDR, UART_CTS_PIN)
00259 #endif
00260 
00261 /*
00262 ** X40 pins.
00263 */
00264 #elif defined(MCU_AT91R40008)
00265 
00266 #define UART_RXTX_PINS  (_BV(P15_RXD0) | _BV(P14_TXD0))
00267 
00268 #define UART_RXTX_PINS_ENABLE() outr(PIO_PDR, UART_RXTX_PINS)
00269 
00270 /*
00271 ** Add more targets here.
00272 **
00273 ** For unsupported targets you may also do basic initializations in
00274 ** your application code.
00275 */
00276 
00277 #endif
00278 
00279 /*
00280 ** CPLD logic, currently used on Ethernut 3 only.
00281 */
00282 #if defined(ETHERNUT3)
00283 #define UART_USES_NPL   1
00284 #endif
00285 
00286 /*
00287 ** Determine the CTS GPIO interrupt, based on the port ID.
00288 */
00289 #if defined(UART0_CTS_BIT) && !defined(UART0_CTS_SIGNAL)
00290 #if UART0_CTS_PIO_ID == PIOA_ID
00291 #define UART0_CTS_SIGNAL    sig_GPIO1
00292 #elif UART0_CTS_PIO_ID == PIOB_ID
00293 #define UART0_CTS_SIGNAL    sig_GPIO2
00294 #elif UART0_CTS_PIO_ID == PIOC_ID
00295 #define UART0_CTS_SIGNAL    sig_GPIO3
00296 #else
00297 #define UART0_CTS_SIGNAL    sig_GPIO
00298 #endif
00299 #endif
00300 
00301 /*
00302 ** Translate all macros for UART0 to generalized ones used by the
00303 ** source that will be included at the end of this file.
00304 */
00305 #if defined(UART0_HDX_BIT)
00306 #define UART_HDX_BIT    UART0_HDX_BIT
00307 #endif
00308 #if defined(UART0_HDX_PIO_ID)
00309 #define UART_HDX_PIO_ID UART0_HDX_PIO_ID
00310 #endif
00311 
00312 #if defined(UART0_RTS_BIT)
00313 #define UART_RTS_BIT    UART0_RTS_BIT
00314 #endif
00315 #if defined(UART0_RTS_PIO_ID)
00316 #define UART_RTS_PIO_ID UART0_RTS_PIO_ID
00317 #endif
00318 
00319 #if defined(UART0_CTS_BIT)
00320 #define UART_CTS_BIT    UART0_CTS_BIT
00321 #endif
00322 #if defined(UART0_CTS_PIO_ID)
00323 #define UART_CTS_PIO_ID UART0_CTS_PIO_ID
00324 #endif
00325 #if defined(UART0_CTS_SIGNAL)
00326 #define UART_CTS_SIGNAL UART0_CTS_SIGNAL
00327 #endif
00328 
00329 #if defined(UART0_INIT_BAUDRATE)
00330 #define UART_INIT_BAUDRATE  UART0_INIT_BAUDRATE
00331 #endif
00332 
00333 #define USARTn_BASE     USART0_BASE
00334 #define US_ID           US0_ID
00335 #define SIG_UART        sig_UART0
00336 #define dcb_usart       dcb_usart0
00337 
00338 #include "usartat91.c"