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Nut/OS
4.10.3
API Reference
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Nut/OS
4.10.3
API Reference
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00001 /* 00002 * Copyright (C) 2005 by egnite Software GmbH 00003 * Copyright 2009 by egnite GmbH 00004 * 00005 * All rights reserved. 00006 * 00007 * Redistribution and use in source and binary forms, with or without 00008 * modification, are permitted provided that the following conditions 00009 * are met: 00010 * 00011 * 1. Redistributions of source code must retain the above copyright 00012 * notice, this list of conditions and the following disclaimer. 00013 * 2. Redistributions in binary form must reproduce the above copyright 00014 * notice, this list of conditions and the following disclaimer in the 00015 * documentation and/or other materials provided with the distribution. 00016 * 3. Neither the name of the copyright holders nor the names of 00017 * contributors may be used to endorse or promote products derived 00018 * from this software without specific prior written permission. 00019 * 00020 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 00021 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 00022 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 00023 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 00024 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 00025 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 00026 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 00027 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 00028 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00029 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 00030 * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 00031 * SUCH DAMAGE. 00032 * 00033 * For additional information see http://www.ethernut.de/ 00034 */ 00035 00036 /* 00037 * $Id: usart1at91.c 3449 2011-05-31 19:08:15Z mifi $ 00038 */ 00039 00040 #include <cfg/os.h> 00041 #include <cfg/clock.h> 00042 #include <cfg/arch.h> 00043 #include <cfg/uart.h> 00044 #include <cfg/arch/gpio.h> 00045 00046 #include <string.h> 00047 00048 #include <sys/atom.h> 00049 #include <sys/event.h> 00050 #include <sys/timer.h> 00051 00052 #include <dev/irqreg.h> 00053 #include <dev/gpio.h> 00054 #include <dev/usartat91.h> 00055 00056 #ifndef NUT_CPU_FREQ 00057 #ifdef NUT_PLL_CPUCLK 00058 #include <dev/cy2239x.h> 00059 #else /* !NUT_PLL_CPUCLK */ 00060 #define NUT_CPU_FREQ 73728000UL 00061 #endif /* !NUT_PLL_CPUCLK */ 00062 #endif /* !NUT_CPU_FREQ */ 00063 00064 /* 00065 * Local function prototypes. 00066 */ 00067 static uint32_t At91UsartGetSpeed(void); 00068 static int At91UsartSetSpeed(uint32_t rate); 00069 static uint8_t At91UsartGetDataBits(void); 00070 static int At91UsartSetDataBits(uint8_t bits); 00071 static uint8_t At91UsartGetParity(void); 00072 static int At91UsartSetParity(uint8_t mode); 00073 static uint8_t At91UsartGetStopBits(void); 00074 static int At91UsartSetStopBits(uint8_t bits); 00075 static uint32_t At91UsartGetFlowControl(void); 00076 static int At91UsartSetFlowControl(uint32_t flags); 00077 static uint32_t At91UsartGetStatus(void); 00078 static int At91UsartSetStatus(uint32_t flags); 00079 static uint8_t At91UsartGetClockMode(void); 00080 static int At91UsartSetClockMode(uint8_t mode); 00081 static void At91UsartTxStart(void); 00082 static void At91UsartRxStart(void); 00083 static int At91UsartInit(void); 00084 static int At91UsartDeinit(void); 00085 00090 00094 static USARTDCB dcb_usart1 = { 00095 0, /* dcb_modeflags */ 00096 0, /* dcb_statusflags */ 00097 0, /* dcb_rtimeout */ 00098 0, /* dcb_wtimeout */ 00099 {0, 0, 0, 0, 0, 0, 0, 0}, /* dcb_tx_rbf */ 00100 {0, 0, 0, 0, 0, 0, 0, 0}, /* dcb_rx_rbf */ 00101 0, /* dbc_last_eol */ 00102 At91UsartInit, /* dcb_init */ 00103 At91UsartDeinit, /* dcb_deinit */ 00104 At91UsartTxStart, /* dcb_tx_start */ 00105 At91UsartRxStart, /* dcb_rx_start */ 00106 At91UsartSetFlowControl, /* dcb_set_flow_control */ 00107 At91UsartGetFlowControl, /* dcb_get_flow_control */ 00108 At91UsartSetSpeed, /* dcb_set_speed */ 00109 At91UsartGetSpeed, /* dcb_get_speed */ 00110 At91UsartSetDataBits, /* dcb_set_data_bits */ 00111 At91UsartGetDataBits, /* dcb_get_data_bits */ 00112 At91UsartSetParity, /* dcb_set_parity */ 00113 At91UsartGetParity, /* dcb_get_parity */ 00114 At91UsartSetStopBits, /* dcb_set_stop_bits */ 00115 At91UsartGetStopBits, /* dcb_get_stop_bits */ 00116 At91UsartSetStatus, /* dcb_set_status */ 00117 At91UsartGetStatus, /* dcb_get_status */ 00118 At91UsartSetClockMode, /* dcb_set_clock_mode */ 00119 At91UsartGetClockMode, /* dcb_get_clock_mode */ 00120 }; 00121 00137 NUTDEVICE devUsartAt911 = { 00138 0, /* Pointer to next device, dev_next. */ 00139 {'u', 'a', 'r', 't', '1', 0, 0, 0, 0}, /* Unique device name, dev_name. */ 00140 IFTYP_CHAR, /* Type of device, dev_type. */ 00141 1, /* Base address, dev_base (not used). */ 00142 0, /* First interrupt number, dev_irq (not used). */ 00143 0, /* Interface control block, dev_icb (not used). */ 00144 &dcb_usart1, /* Driver control block, dev_dcb. */ 00145 UsartInit, /* Driver initialization routine, dev_init. */ 00146 UsartIOCtl, /* Driver specific control function, dev_ioctl. */ 00147 UsartRead, /* Read from device, dev_read. */ 00148 UsartWrite, /* Write to device, dev_write. */ 00149 UsartOpen, /* Open a device or file, dev_open. */ 00150 UsartClose, /* Close a device or file, dev_close. */ 00151 UsartSize /* Request file size, dev_size. */ 00152 }; 00153 00157 00158 /* Modem control includes hardware handshake. */ 00159 #if defined(UART1_MODEM_CONTROL) 00160 #define UART_MODEM_CONTROL 00161 #define UART_HARDWARE_HANDSHAKE 00162 #elif defined(UART1_HARDWARE_HANDSHAKE) 00163 #define UART_HARDWARE_HANDSHAKE 00164 #endif 00165 00166 /* 00167 ** SAM9260 and SAM9XE pins. 00168 */ 00169 #if defined(MCU_AT91SAM9260) || defined(MCU_AT91SAM9XE) 00170 00171 #define UART_RXTX_PINS (_BV(PB7_RXD1_A) | _BV(PB6_TXD1_A)) 00172 #define UART_HDX_PIN _BV(PB28_RTS1_A) 00173 #define UART_RTS_PIN _BV(PB28_RTS1_A) 00174 #define UART_CTS_PIN _BV(PB29_CTS1_A) 00175 00176 #define UART_RXTX_PINS_ENABLE() outr(PIOB_ASR, UART_RXTX_PINS); \ 00177 outr(PIOB_PDR, UART_RXTX_PINS) 00178 00179 #if defined(UART_HARDWARE_HANDSHAKE) 00180 #define UART_HDX_PIN_ENABLE() outr(PIOB_ASR, UART_HDX_PIN); \ 00181 outr(PIOB_PDR, UART_HDX_PIN) 00182 #define UART_RTS_PIN_ENABLE() outr(PIOB_ASR, UART_RTS_PIN); \ 00183 outr(PIOB_PDR, UART_RTS_PIN) 00184 #define UART_CTS_PIN_ENABLE() outr(PIOB_ASR, UART_CTS_PIN); \ 00185 outr(PIOB_PDR, UART_CTS_PIN) 00186 #endif 00187 00188 /* 00189 ** AT91SAM9G45 pins. 00190 */ 00191 #elif defined(MCU_AT91SAM9G45) 00192 00193 #define UART_RXTX_PINS (_BV(PB4_TXD1_A) | _BV(PB5_RXD1_A)) 00194 #define UART_HDX_PIN _BV(PD16_RTS1_A) 00195 #define UART_RTS_PIN _BV(PD16_RTS1_A) 00196 #define UART_CTS_PIN _BV(PD17_CTS1_A) 00197 00198 #define UART_RXTX_PINS_ENABLE() outr(PIOB_ASR, UART_RXTX_PINS); \ 00199 outr(PIOB_PDR, UART_RXTX_PINS) 00200 00201 #if defined(UART_HARDWARE_HANDSHAKE) 00202 #define UART_HDX_PIN_ENABLE() outr(PIOD_ASR, UART_HDX_PIN); \ 00203 outr(PIOD_PDR, UART_HDX_PIN) 00204 #define UART_RTS_PIN_ENABLE() outr(PIOD_ASR, UART_RTS_PIN); \ 00205 outr(PIOD_PDR, UART_RTS_PIN) 00206 #define UART_CTS_PIN_ENABLE() outr(PIOD_ASR, UART_CTS_PIN); \ 00207 outr(PIOD_PDR, UART_CTS_PIN) 00208 #endif 00209 00210 #elif defined(MCU_AT91SAM7S) || defined(MCU_AT91SAM7SE) 00211 00212 #define UART_RXTX_PINS (_BV(PA21_RXD1_A) | _BV(PA22_TXD1_A)) 00213 #define UART_HDX_PIN _BV(PA24_RTS1_A) 00214 #define UART_RTS_PIN _BV(PA24_RTS1_A) 00215 #define UART_CTS_PIN _BV(PA25_CTS1_A) 00216 #define UART_MODEM_PINS (_BV(PB27_DTR1_A) | _BV(PB28_DSR1_A) | _BV(PB26_DCD1_A) | _BV(PB29_RI1_A)) 00217 00218 #define UART_RXTX_PINS_ENABLE() outr(PIOA_ASR, UART_RXTX_PINS); \ 00219 outr(PIOA_PDR, UART_RXTX_PINS) 00220 00221 #if defined(UART_HARDWARE_HANDSHAKE) 00222 #define UART_HDX_PIN_ENABLE() outr(PIOA_ASR, UART_HDX_PIN); \ 00223 outr(PIOA_PDR, UART_HDX_PIN) 00224 #define UART_RTS_PIN_ENABLE() outr(PIOA_ASR, UART_RTS_PIN); \ 00225 outr(PIOA_PDR, UART_RTS_PIN) 00226 #define UART_CTS_PIN_ENABLE() outr(PIOA_ASR, UART_CTS_PIN); \ 00227 outr(PIOA_PDR, UART_CTS_PIN) 00228 #endif 00229 00230 #if defined(UART_MODEM_CONTROL) 00231 #define UART_MODEM_PINS_ENABLE() outr(PIOB_ASR, UART_MODEM_PINS); \ 00232 outr(PIOB_PDR, UART_MODEM_PINS) 00233 #endif 00234 00235 /* 00236 ** SAM7X pins. 00237 */ 00238 #elif defined(MCU_AT91SAM7X) 00239 #define UART_RXTX_PINS (_BV(PA5_RXD1_A) | _BV(PA6_TXD1_A)) 00240 #define UART_HDX_PIN _BV(PA8_RTS1_A) 00241 #define UART_RTS_PIN _BV(PA8_RTS1_A) 00242 #define UART_CTS_PIN _BV(PA9_CTS1_A) 00243 #define UART_MODEM_PINS (_BV(PB25_DTR1_B) | _BV(PB24_DSR1_B) | _BV(PB23_DCD1_B) | _BV(PB26_RI1_B)) 00244 00245 #define UART_RXTX_PINS_ENABLE() outr(PIOA_ASR, UART_RXTX_PINS); \ 00246 outr(PIOA_PDR, UART_RXTX_PINS) 00247 00248 #if defined(UART_HARDWARE_HANDSHAKE) 00249 #define UART_HDX_PIN_ENABLE() outr(PIOA_ASR, UART_HDX_PIN); \ 00250 outr(PIOA_PDR, UART_HDX_PIN) 00251 #define UART_RTS_PIN_ENABLE() outr(PIOA_ASR, UART_RTS_PIN); \ 00252 outr(PIOA_PDR, UART_RTS_PIN) 00253 #define UART_CTS_PIN_ENABLE() outr(PIOA_ASR, UART_CTS_PIN); \ 00254 outr(PIOA_PDR, UART_CTS_PIN) 00255 #endif 00256 00257 #if defined(UART_MODEM_CONTROL) 00258 #define UART_MODEM_PINS_ENABLE() outr(PIOB_BSR, UART_MODEM_PINS); \ 00259 outr(PIOB_PDR, UART_MODEM_PINS) 00260 #endif 00261 00262 /* 00263 ** X40 pins. 00264 */ 00265 #elif defined(MCU_AT91R40008) 00266 00267 #define UART_RXTX_PINS (_BV(P22_RXD1) | _BV(P21_TXD1)) 00268 00269 #define UART_RXTX_PINS_ENABLE() outr(PIO_PDR, UART_RXTX_PINS) 00270 00271 /* 00272 ** Add more targets here. 00273 ** 00274 ** For unsupported targets you may also do basic initializations in 00275 ** your application code. 00276 */ 00277 00278 #endif 00279 00280 /* 00281 ** CPLD logic, currently used on Ethernut 3 only. 00282 */ 00283 #if defined(ETHERNUT3) 00284 #define UART_USES_NPL 1 00285 #endif 00286 00287 /* 00288 ** Determine the CTS GPIO interrupt, based on the port ID. 00289 */ 00290 #if defined(UART1_CTS_BIT) && !defined(UART1_CTS_SIGNAL) 00291 #if UART1_CTS_PIO_ID == PIOA_ID 00292 #define UART1_CTS_SIGNAL sig_GPIO1 00293 #elif UART1_CTS_PIO_ID == PIOB_ID 00294 #define UART1_CTS_SIGNAL sig_GPIO2 00295 #elif UART1_CTS_PIO_ID == PIOC_ID 00296 #define UART1_CTS_SIGNAL sig_GPIO3 00297 #else 00298 #define UART1_CTS_SIGNAL sig_GPIO 00299 #endif 00300 #endif 00301 00302 /* 00303 ** Translate all macros for UART1 to generalized ones used by the 00304 ** source that will be included at the end of this file. 00305 */ 00306 #if defined(UART1_HDX_BIT) 00307 #define UART_HDX_BIT UART1_HDX_BIT 00308 #endif 00309 #if defined(UART1_HDX_PIO_ID) 00310 #define UART_HDX_PIO_ID UART1_HDX_PIO_ID 00311 #endif 00312 00313 #if defined(UART1_RTS_BIT) 00314 #define UART_RTS_BIT UART1_RTS_BIT 00315 #endif 00316 #if defined(UART1_RTS_PIO_ID) 00317 #define UART_RTS_PIO_ID UART1_RTS_PIO_ID 00318 #endif 00319 00320 #if defined(UART1_CTS_BIT) 00321 #define UART_CTS_BIT UART1_CTS_BIT 00322 #endif 00323 #if defined(UART1_CTS_PIO_ID) 00324 #define UART_CTS_PIO_ID UART1_CTS_PIO_ID 00325 #endif 00326 #if defined(UART1_CTS_SIGNAL) 00327 #define UART_CTS_SIGNAL UART1_CTS_SIGNAL 00328 #endif 00329 00330 #if defined(UART1_INIT_BAUDRATE) 00331 #define UART_INIT_BAUDRATE UART1_INIT_BAUDRATE 00332 #endif 00333 00334 #define USARTn_BASE USART1_BASE 00335 #define US_ID US1_ID 00336 #define SIG_UART sig_UART1 00337 #define dcb_usart dcb_usart1 00338 00339 #include "usartat91.c"