Data Structures | |
struct | _NICINFO |
Network interface controller information structure. More... | |
struct | _NICINFO |
Network interface controller information structure. More... | |
Defines | |
#define | NIC_BSR |
Bank select register. | |
#define | NIC_TCR |
Bank 0 - Transmit control register. | |
#define | TCR_SWFDUP |
#define | TCR_EPH_LOOP |
#define | TCR_STP_SQET |
#define | TCR_FDUPLX |
#define | TCR_MON_CSN |
#define | TCR_NOCRC |
#define | TCR_PAD_EN |
#define | TCR_FORCOL |
#define | TCR_LOOP |
#define | TCR_TXENA |
#define | NIC_EPHSR |
Bank 0 - EPH status register. | |
#define | NIC_RCR |
Bank 0 - Receive control register. | |
#define | RCR_SOFT_RST |
#define | RCR_FILT_CAR |
#define | RCR_ABORT_ENB |
#define | RCR_STRIP_CRC |
#define | RCR_RXEN |
#define | RCR_ALMUL |
#define | RCR_PRMS |
#define | RCR_RX_ABORT |
#define | NIC_ECR |
Bank 0 - Counter register. | |
#define | NIC_MIR |
Bank 0 - Memory information register. | |
#define | NIC_RPCR |
Bank 0 - Receive / PHY control register. | |
#define | RPCR_SPEED |
#define | RPCR_DPLX |
#define | RPCR_ANEG |
#define | RPCR_LEDA_PAT |
#define | RPCR_LEDB_PAT |
#define | NIC_CR |
Bank 1 - Configuration register. | |
#define | CR_EPH_EN |
#define | NIC_BAR |
Bank 1 - Base address register. | |
#define | NIC_IAR |
Bank 1 - Individual address register. | |
#define | NIC_GPR |
Bank 1 - General purpose register. | |
#define | NIC_CTR |
Bank 1 - Control register. | |
#define | CTR_RCV_BAD |
#define | CTR_AUTO_RELEASE |
#define | NIC_MMUCR |
Bank 2 - MMU command register. | |
#define | MMUCR_BUSY |
#define | MMU_NOP |
#define | MMU_ALO |
#define | MMU_RST |
#define | MMU_REM |
#define | MMU_TOP |
#define | MMU_PKT |
#define | MMU_ENQ |
#define | MMU_RTX |
#define | NIC_PNR |
Bank 2 - Packet number register. | |
#define | NIC_ARR |
Bank 2 - Allocation result register. | |
#define | ARR_FAILED |
#define | NIC_FIFO |
Bank 2 - FIFO ports register. | |
#define | NIC_PTR |
Bank 2 - Pointer register. | |
#define | PTR_RCV |
#define | PTR_AUTO_INCR |
#define | PTR_READ |
#define | PTR_ETEN |
#define | PTR_NOT_EMPTY |
#define | NIC_DATA |
Bank 2 - Data register. | |
#define | NIC_IST |
Bank 2 - Interrupt status register. | |
#define | NIC_ACK |
Bank 2 - Interrupt acknowledge register. | |
#define | NIC_MSK |
Bank 2 - Interrupt mask register. | |
#define | INT_MD |
#define | INT_ERCV |
#define | INT_EPH |
#define | INT_RX_OVRN |
#define | INT_ALLOC |
#define | INT_TX_EMPTY |
#define | INT_TX |
#define | INT_RCV |
#define | NIC_MT |
Bank 3 - Multicast table register. | |
#define | NIC_MGMT |
Bank 3 - Management interface register. | |
#define | MGMT_MDOE |
#define | MGMT_MCLK |
#define | MGMT_MDI |
#define | MGMT_MDO |
#define | NIC_REV |
Bank 3 - Revision register. | |
#define | NIC_ERCV |
Bank 3 - Early RCV register. | |
#define | NIC_PHYCR |
PHY control register. | |
#define | PHYCR_RST |
#define | PHYCR_LPBK |
#define | PHYCR_SPEED |
#define | PHYCR_ANEG_EN |
#define | PHYCR_PDN |
#define | PHYCR_MII_DIS |
#define | PHYCR_ANEG_RST |
#define | PHYCR_DPLX |
#define | PHYCR_COLST |
#define | NIC_PHYSR |
PHY status register. | |
#define | PHYSR_CAP_T4 |
#define | PHYSR_CAP_TXF |
#define | PHYSR_CAP_TXH |
#define | PHYSR_CAP_TF |
#define | PHYSR_CAP_TH |
#define | PHYSR_CAP_SUPR |
#define | PHYSR_ANEG_ACK |
#define | PHYSR_REM_FLT |
#define | PHYSR_CAP_ANEG |
#define | PHYSR_LINK |
#define | PHYSR_JAB |
#define | PHYSR_EXREG |
#define | NIC_PHYID1 |
PHY identifier register 1. | |
#define | NIC_PHYID2 |
PHY identifier register 1. | |
#define | NIC_PHYANAD |
PHY auto-negotiation advertisement register. | |
#define | PHYANAD_NP |
#define | PHYANAD_ACK |
#define | PHYANAD_RF |
#define | PHYANAD_T4 |
#define | PHYANAD_TX_FDX |
#define | PHYANAD_TX_HDX |
#define | PHYANAD_10FDX |
#define | PHYANAD_10_HDX |
#define | PHYANAD_CSMA |
#define | NIC_PHYANRC |
PHY auto-negotiation remote end capability register. | |
#define | NIC_PHYCFR1 |
PHY configuration register 1. | |
#define | NIC_PHYCFR2 |
PHY configuration register 2. | |
#define | NIC_PHYSOR |
PHY status output register. | |
#define | PHYSOR_INT |
#define | PHYSOR_LNKFAIL |
#define | PHYSOR_LOSSSYNC |
#define | PHYSOR_CWRD |
#define | PHYSOR_SSD |
#define | PHYSOR_ESD |
#define | PHYSOR_RPOL |
#define | PHYSOR_JAB |
#define | PHYSOR_SPDDET |
#define | PHYSOR_DPLXDET |
#define | NIC_PHYMSK |
PHY mask register. | |
#define | PHYMSK_MINT |
#define | PHYMSK_MLNKFAIL |
#define | PHYMSK_MLOSSSYN |
#define | PHYMSK_MCWRD |
#define | PHYMSK_MSSD |
#define | PHYMSK_MESD |
#define | PHYMSK_MRPOL |
#define | PHYMSK_MJAB |
#define | PHYMSK_MSPDDT |
#define | PHYMSK_MDPLDT |
#define | MSBV(bit) |
#define | nic_outlb(addr, val) |
#define | nic_outhb(addr, val) |
#define | nic_outwx(addr, val) |
#define | nic_outw(addr, val) |
#define | nic_inlb(addr) |
#define | nic_inhb(addr) |
#define | nic_inw(addr) |
#define | nic_bs(bank) |
Typedefs | |
typedef _NICINFO | NICINFO |
Network interface controller information type. |
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NIC_CR bit mask, . |
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NIC_CTR bit mask, transmit packets automatically released. |
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NIC_CTR bit mask. |
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Transmit allocation interrupt bit mask. |
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Ethernet protocol interrupt bit mask. |
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Early receive interrupt bit mask. |
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PHY state change interrupt bit mask. |
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Receive interrupt bit mask. |
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Receive overrun interrupt bit mask. |
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Transmit complete interrupt bit mask. |
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Transmitter empty interrupt bit mask. |
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NIC_MGMT bit mask, drives MDCLK pin. |
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NIC_MGMT bit mask, reflects MDI pin status. |
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NIC_MGMT bit mask, drives MDO pin. |
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NIC_MGMT bit mask, enables MDO pin. |
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Bank 2 - Allocation result register. This byte register is updated upon a MMU_ALO command. |
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Bank 2 - Packet number register. This byte register specifies the accessible transmit packet number. |
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NIC_PHYANAD bit mask, indicates 10BASE-T half duplex capability. |
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NIC_PHYANAD bit mask, indicates 10BASE-T full duplex capability. |
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NIC_PHYANAD bit mask, acknowledged. |
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NIC_PHYANAD bit mask, indicates 802.3 CSMA capability. |
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NIC_PHYANAD bit mask, exchanging next page information. |
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NIC_PHYANAD bit mask, remote fault. |
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NIC_PHYANAD bit mask, indicates 100BASE-T4 capability. |
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NIC_PHYANAD bit mask, indicates 100BASE-TX full duplex capability. |
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NIC_PHYANAD bit mask, indicates 100BASE-TX half duplex capability. |
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NIC_PHYCR bit mask, . |
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NIC_PHYCR bit mask, . |
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NIC_PHYCR bit mask, . |
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NIC_PHYCR bit mask, . |
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NIC_PHYCR bit mask, . |
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NIC_PHYCR bit mask, . |
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NIC_PHYCR bit mask, . |
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NIC_PHYCR bit mask, resets PHY. |
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NIC_PHYCR bit mask, . |
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NIC_PHYMSK bit mask, enables PHYSOR_CWRD interrupt. |
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NIC_PHYMSK bit mask, enables PHYSOR_DPLXDET interrupt. |
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NIC_PHYMSK bit mask, enables PHYSOR_ESD interrupt. |
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NIC_PHYMSK bit mask, enables PHYSOR_INT interrupt. |
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NIC_PHYMSK bit mask, enables PHYSOR_JAB interrupt. |
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NIC_PHYMSK bit mask, enables PHYSOR_LNKFAIL interrupt. |
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NIC_PHYMSK bit mask, enables PHYSOR_LOSSSYNC interrupt. |
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NIC_PHYMSK bit mask, enables PHYSOR_RPOL interrupt. |
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NIC_PHYMSK bit mask, enables PHYSOR_SPDDET interrupt. |
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NIC_PHYMSK bit mask, enables PHYSOR_SSD interrupt. |
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NIC_PHYSOR bit mask, code word error detected. |
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NIC_PHYSOR bit mask, duplex detected. |
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NIC_PHYSOR bit mask, end of stream error detected. |
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NIC_PHYSOR bit mask, interrupt bits changed. |
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NIC_PHYSOR bit mask, jabber detected. |
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NIC_PHYSOR bit mask, link failure detected. |
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NIC_PHYSOR bit mask, descrambler sync lost detected. |
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NIC_PHYSOR bit mask, reverse polarity detected. |
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NIC_PHYSOR bit mask, 100/10 speed detected. |
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NIC_PHYSOR bit mask, start of stream error detected. |
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NIC_PHYSR bit mask, auto-negotiation completed. |
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NIC_PHYSR bit mask, indicates auto-negotiation capability. |
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NIC_PHYSR bit mask, indicates preamble suppression capability. |
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NIC_PHYSR bit mask, indicates 100BASE-T4 capability. |
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NIC_PHYSR bit mask, indicates 10BASE-T full duplex capability. |
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NIC_PHYSR bit mask, indicates 10BASE-T half duplex capability. |
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NIC_PHYSR bit mask, indicates 100BASE-TX full duplex capability. |
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NIC_PHYSR bit mask, indicates 100BASE-TX half duplex capability. |
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NIC_PHYSR bit mask, extended capabilities available. |
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NIC_PHYSR bit mask, jabber collision detected. |
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NIC_PHYSR bit mask, valid link status. |
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NIC_PHYSR bit mask, remote fault detected. |
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NIC_RCR bit mask, enables receive abort on collision. |
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NIC_RCR bit mask, multicast frames accepted when set. |
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NIC_RCR bit mask, enables carrier filter. |
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NIC_RCR bit mask, enables promiscuous mode. |
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NIC_RCR bit mask, set when receive was aborted. |
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NIC_RCR bit mask, enables receiver. |
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NIC_RCR bit mask, activates software reset. |
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NIC_RCR bit mask, strips CRC. |
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NIC_RPCR bit mask, sets PHY in auto-negotiation mode. |
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NIC_RPCR bit mask, PHY operates at full duplex mode. |
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NIC_RPCR bit mask for LEDA mode. |
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NIC_RPCR bit mask for LEDB mode. |
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NIC_RPCR bit mask, PHY operates at 100 Mbps. |
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NIC_TCR bit mask, enables internal loopback. |
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NIC_TCR bit mask, enables receiving own frames. |
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NIC_TCR bit mask, forces collision. |
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NIC_TCR bit mask, enables PHY loopback. |
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NIC_TCR bit mask, enables carrier monitoring. |
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NIC_TCR bit mask, disables CRC transmission. |
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NIC_TCR bit mask, enables automatic padding. |
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NIC_TCR bit mask, enables transmission stop on SQET error. |
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NIC_TCR bit mask, enables full duplex. |
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NIC_TCR bit mask, enables transmitter. |