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Interrupt Controller
[AT91]


Detailed Description

Advanced interrupt controller registers.

The AT91 series provides an 8-level priority, individually maskable, vectored interrupt controller.


Interrupt Source Mode Registers

#define AIC_SMR(i)   (AIC_BASE + i * 4)
 Source mode register array.
#define AIC_PRIOR   0x00000007
 Priority mask.
#define AIC_SRCTYPE   0x00000060
 Interrupt source type mask.
#define AIC_SRCTYPE_INT_LEVEL_SENSITIVE   0x00000000
 Internal level sensitive.
#define AIC_SRCTYPE_INT_EDGE_TRIGGERED   0x00000020
 Internal edge triggered.
#define AIC_SRCTYPE_EXT_LOW_LEVEL   0x00000000
 External low level.
#define AIC_SRCTYPE_EXT_NEGATIVE_EDGE   0x00000020
 External falling edge.
#define AIC_SRCTYPE_EXT_HIGH_LEVEL   0x00000040
 External high level.
#define AIC_SRCTYPE_EXT_POSITIVE_EDGE   0x00000060
 External rising edge.

Interrupt Source Vector Registers

#define AIC_SVR(i)   (AIC_BASE + 0x80 + i * 4)
 Source vector register array.

Interrupt Vector Register

#define AIC_IVR   (AIC_BASE + 0x100)
 IRQ vector register address.

Fast Interrupt Vector Register

#define AIC_FVR   (AIC_BASE + 0x104)
 FIQ vector register address.

Interrupt Status Register

#define AIC_ISR   (AIC_BASE + 0x108)
 Interrupt status register address.
#define AIC_IRQID   0x0000001F
 Current interrupt identifier mask.

Interrupt Pending Register

#define AIC_IPR   (AIC_BASE + 0x10C)
 Interrupt pending register address.

Interrupt Mask Register

#define AIC_IMR   (AIC_BASE + 0x110)
 Interrupt mask register address.

Interrupt Core Status Register

#define AIC_CISR   (AIC_BASE + 0x114)
 Core interrupt status register address.
#define AIC_NFIQ   0x00000001
 Core FIQ Status.
#define AIC_NIRQ   0x00000002
 Core IRQ Status.

Interrupt Enable Command Register

#define AIC_IECR   (AIC_BASE + 0x120)
 Interrupt enable command register address.

Interrupt Disable Command Register

#define AIC_IDCR   (AIC_BASE + 0x124)
 Interrupt disable command register address.

Interrupt Clear Command Register

#define AIC_ICCR   (AIC_BASE + 0x128)
 Interrupt clear command register address.

Interrupt Set Command Register

#define AIC_ISCR   (AIC_BASE + 0x12C)
 Interrupt set command register address.

End Of Interrupt Command Register

#define AIC_EOICR   (AIC_BASE + 0x130)
 End of interrupt command register address.

Spurious Interrupt Vector Register

#define AIC_SPU   (AIC_BASE + 0x134)
 Spurious vector register address.

Defines

#define AIC_BASE   0xFFFFF000
#define IRQ_ENTRY()
 Interrupt entry.
#define IRQ_EXIT()
 Interrupt exit.


Define Documentation

#define AIC_BASE   0xFFFFF000
 

AIC base address.

#define AIC_PRIOR   0x00000007
 

Priority mask.

Priority levels can be between 0 (lowest) and 7 (highest).

#define AIC_SRCTYPE   0x00000060
 

Interrupt source type mask.

Internal interrupts can level sensitive or edge triggered.

External interrupts can triggered on positive or negative levels or on rising or falling edges.

#define AIC_SVR  )     (AIC_BASE + 0x80 + i * 4)
 

Source vector register array.

Stores the addresses of the corresponding interrupt handlers.

 
#define IRQ_ENTRY  ) 
 

Value:

asm volatile("sub   lr, lr,#4"          "\n\t"  /* Adjust LR */ \
                 "stmfd sp!,{r0-r12,lr}"    "\n\t"  /* Save registers on IRQ stack. */ \
                 "mrs   r1, spsr"           "\n\t"  /* Save SPSR */ \
                 "stmfd sp!,{r1}"           "\n\t")
Interrupt entry.

 
#define IRQ_EXIT  ) 
 

Value:

asm volatile("ldmfd sp!, {r1}"          "\n\t"  /* Restore SPSR */ \
                 "msr   spsr_c, r1"         "\n\t"  /* */ \
                 "ldr   r0, =0xFFFFF000"    "\n\t"  /* End of interrupt. */ \
                 "str   r0, [r0, #0x130]"   "\n\t"  /* */ \
                 "ldmfd sp!, {r0-r12, pc}^" "\n\t")
Interrupt exit.


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