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at91.h File Reference


Detailed Description

AT91 peripherals.

 *
 * $Log: at91.h,v $
 * Revision 1.2  2005/11/20 14:44:14  haraldkipp
 * Register offsets added.
 *
 * Revision 1.1  2005/10/24 10:31:13  haraldkipp
 * Moved from parent directory.
 *
 *
 * 


Chip Select Register

#define EBI_CSR(i)   (EBI_BASE + i * 4)
 Chip select register address.
#define EBI_DBW   0x00000003
 Masks data bus width.
#define EBI_DBW_16   0x00000001
 16-bit data bus width
#define EBI_DBW_8   0x00000002
 8-bit data bus width
#define EBI_NWS   0x0000001C
 Masks number of wait states.
#define EBI_NWS_1   0x00000000
 1 wait state
#define EBI_NWS_2   0x00000004
 2 wait states
#define EBI_NWS_3   0x00000008
 3 wait states
#define EBI_NWS_4   0x0000000C
 4 wait states
#define EBI_NWS_5   0x00000010
 5 wait states
#define EBI_NWS_6   0x00000014
 6 wait states
#define EBI_NWS_7   0x00000018
 7 wait states
#define EBI_NWS_8   0x0000001C
 8 wait states
#define EBI_WSE   0x00000020
 Wait state enable.
#define EBI_PAGES   0x00000180
 Page size mask.
#define EBI_PAGES_1M   0x00000000
 1 MByte page size
#define EBI_PAGES_4M   0x00000080
 4 MBytes page size
#define EBI_PAGES_16M   0x00000100
 16 MBytes page size
#define EBI_PAGES_64M   0x00000180
 64 MBytes page size
#define EBI_TDF   0x00000E00
 Masks data float output time clock cycles.
#define EBI_TDF_0   0x00000000
 No added cycles.
#define EBI_TDF_1   0x00000200
 1 cycle
#define EBI_TDF_2   0x00000400
 2 cycles
#define EBI_TDF_3   0x00000600
 3 cycles
#define EBI_TDF_4   0x00000800
 4 cycles
#define EBI_TDF_5   0x00000A00
 5 cycles
#define EBI_TDF_6   0x00000C00
 6 cycles
#define EBI_TDF_7   0x00000E00
 7 cycles
#define EBI_BAT   0x00001000
 Byte access type.
#define EBI_BAT_BYTE_WRITE   0x00000000
 Byte write access type.
#define EBI_BAT_BYTE_SELECT   0x00001000
 Byte select access type.
#define EBI_CSEN   0x00002000
 Chip select enable.
#define EBI_BA   0xFFF00000
 Page base address mask.

Remap Control Register

#define EBI_RCR   (EBI_BASE + 0x20)
 Remap control register address.
#define EBI_RCB   0x00000001
 Remap command.

Memory Control Register

#define EBI_MCR   (EBI_BASE + 0x24)
 Memory control register address.
#define EBI_ALE   0x00000007
 Address line enable.
#define EBI_ALE_16M   0x00000000
 16 Mbytes total address space
#define EBI_ALE_8M   0x00000004
 8 Mbytes total address space
#define EBI_ALE_4M   0x00000005
 4 Mbytes total address space
#define EBI_ALE_2M   0x00000006
 2 Mbytes total address space
#define EBI_ALE_1M   0x00000007
 1 Mbyte total address space
#define EBI_DRP   0x00000010
 Data read protocol mask.
#define EBI_DRP_STANDARD   0x00000000
 Standard read protocol.
#define EBI_DRP_EARLY   0x00000010
 Early read protocol.

Chip Identification Registers

#define SF_CIDR   (SF_BASE + 0x00)
 Chip ID register address.
#define SF_EXID   (SF_BASE + 0x04)
 Chip ID extension register address.
#define SF_VERSION   0x0000001F
 Version number mask.
#define SF_NVPSIZ   0x00000F00
 Masks non volatile program memory size.
#define SF_NVPSIZ_NONE   0x00000000
 No NV program memory.
#define SF_NVPSIZ_32K   0x00000300
 32 kBytes NV program memory
#define SF_NVPSIZ_64K   0x00000500
 64 kBytes NV program memory
#define SF_NVPSIZ_128K   0x00000700
 128 kBytes NV program memory
#define SF_NVPSIZ_256K   0x00000900
 256 kBytes NV program memory
#define SF_NVDSIZ   0x0000F000
 Masks non volatile data memory size.
#define SF_NVDSIZ_NONE   0x00000000
 No NV data memory.
#define SF_VDSIZ   0x000F0000
 Masks volatile data memory size.
#define SF_VDSIZ_NONE   0x00000000
 No volatile data memory.
#define SF_VDSIZ_1K   0x00010000
 1 kBytes volatile data memory
#define SF_VDSIZ_2K   0x00020000
 2 kBytes volatile data memory
#define SF_VDSIZ_4K   0x00040000
 4 kBytes volatile data memory
#define SF_VDSIZ_8K   0x00080000
 8 kBytes volatile data memory
#define SF_ARCH   0x0FF00000
 Architecture code mask.
#define SF_ARCH_AT91x40   0x04000000
 AT91x40 architecture.
#define SF_ARCH_AT91x55   0x05500000
 AT91x55 architecture.
#define SF_ARCH_AT91x63   0x06300000
 AT91x63 architecture.
#define SF_NVPTYP   0x70000000
 Masks non volatile program memory type.
#define SF_NVPTYP_M   0x01000000
 M or F series.
#define SF_NVPTYP_C   0x02000000
 C series.
#define SF_NVPTYP_S   0x03000000
 S series.
#define SF_NVPTYP_R   0x04000000
 R series.
#define SF_EXT   0x80000000
 Extension flag.

Reset Status Flag Register

#define SF_RSR   (SF_BASE + 0x08)
 Reset status register address.
#define SF_EXT_RESET   0x0000006C
 Reset caused by external pin.
#define SF_WD_RESET   0x00000053
 Reset caused by internal watch dog.

Memory Mode Register

#define SF_MMR   (SF_BASE + 0x0C)
 Memory mode register address.
#define SF_RAMWU   0x00000001
 Internal extended RAM write allowed.

Protect Mode Register

#define SF_PMR   (SF_BASE + 0x18)
 Protect mode register address.
#define SF_AIC   0x00000020
 AIC runs in protect mode.

USART Control Register

#define US_CR_OFF   0x00000000
 USART control register offset.
#define US0_CR   (USART0_BASE + US_CR_OFF)
 Channel 0 control register address.
#define US1_CR   (USART1_BASE + US_CR_OFF)
 Channel 1 control register address.
#define US_RSTRX   0x00000004
 Reset receiver.
#define US_RSTTX   0x00000008
 Reset transmitter.
#define US_RXEN   0x00000010
 Receiver enable.
#define US_RXDIS   0x00000020
 Receiver disable.
#define US_TXEN   0x00000040
 Transmitter enable.
#define US_TXDIS   0x00000080
 Transmitter disable.
#define US_RSTSTA   0x00000100
 Reset status bits.
#define US_STTBRK   0x00000200
 Start break.
#define US_STPBRK   0x00000400
 Stop break.
#define US_STTTO   0x00000800
 Start timeout.
#define US_SENDA   0x00001000
 Send next byte with address bit set.

Mode Register

#define US_MR_OFF   0x00000004
 USART mode register offset.
#define US0_MR   (USART0_BASE + US_MR_OFF)
 Channel 0 mode register address.
#define US1_MR   (USART1_BASE + US_MR_OFF)
 Channel 1 mode register address.
#define US_CLKS   0x00000030
 Clock selection mask.
#define US_CLKS_MCK   0x00000000
 Master clock.
#define US_CLKS_MCK8   0x00000010
 Master clock divided by 8.
#define US_CLKS_SCK   0x00000020
 External clock.
#define US_CLKS_SLCK   0x00000030
 Slow clock.
#define US_CHRL   0x000000C0
 Masks data length.
#define US_CHRL_5   0x00000000
 5 data bits
#define US_CHRL_6   0x00000040
 6 data bits
#define US_CHRL_7   0x00000080
 7 data bits
#define US_CHRL_8   0x000000C0
 8 data bits
#define US_SYNC   0x00000100
 Synchronous mode enable.
#define US_PAR   0x00000E00
 Parity mode mask.
#define US_PAR_EVEN   0x00000000
 Even parity.
#define US_PAR_ODD   0x00000200
 Odd parity.
#define US_PAR_SPACE   0x00000400
 Space parity.
#define US_PAR_MARK   0x00000600
 Marked parity.
#define US_PAR_NO   0x00000800
 No parity.
#define US_PAR_MULTIDROP   0x00000C00
 Multi-drop mode.
#define US_NBSTOP   0x00003000
 Masks stop bit length.
#define US_NBSTOP_1   0x00000000
 1 stop bit
#define US_NBSTOP_1_5   0x00001000
 1.5 stop bits
#define US_NBSTOP_2   0x00002000
 2 stop bits
#define US_CHMODE   0x0000C000
 Channel mode mask.
#define US_CHMODE_NORMAL   0x00000000
 Normal mode.
#define US_CHMODE_AUTOMATIC_ECHO   0x00004000
 Automatic echo.
#define US_CHMODE_LOCAL_LOOPBACK   0x00008000
 Local loopback.
#define US_CHMODE_REMOTE_LOOPBACK   0x0000C000
 Remote loopback.
#define US_MODE9   0x00020000
 9 bit mode
#define US_CLKO   0x00040000
 Baud rate output enable.

Status and Interrupt Register

#define US_CSR_OFF   0x00000014
 USART status register offset.
#define US0_CSR   (USART0_BASE + US_CSR_OFF)
 Channel 0 status register address.
#define US1_CSR   (USART1_BASE + US_CSR_OFF)
 Channel 1 status register address.
#define US_IER_OFF   0x00000008
 USART interrupt enable register offset.
#define US0_IER   (USART0_BASE + US_IER_OFF)
 Channel 0 interrupt enable register address.
#define US1_IER   (USART1_BASE + US_IER_OFF)
 Channel 1 interrupt enable register address.
#define US_IDR_OFF   0x0000000C
 USART interrupt disable register offset.
#define US0_IDR   (USART0_BASE + US_IDR_OFF)
 Channel 0 interrupt disable register address.
#define US1_IDR   (USART1_BASE + US_IDR_OFF)
 Channel 1 interrupt disable register address.
#define US_IMR_OFF   0x00000010
 USART interrupt mask register offset.
#define US0_IMR   (USART0_BASE + US_IMR_OFF)
 Channel 0 interrupt mask register address.
#define US1_IMR   (USART1_BASE + US_IMR_OFF)
 Channel 1 interrupt mask register address.
#define US_RXRDY   0x00000001
 Receiver ready.
#define US_TXRDY   0x00000002
 Transmitter ready.
#define US_RXBRK   0x00000004
 Receiver break.
#define US_ENDRX   0x00000008
 End of receiver PDC transfer.
#define US_ENDTX   0x00000010
 End of transmitter PDC transfer.
#define US_OVRE   0x00000020
 Overrun error.
#define US_FRAME   0x00000040
 Framing error.
#define US_PARE   0x00000080
 Parity error.
#define US_TIMEOUT   0x00000100
 Receiver timeout.
#define US_TXEMPTY   0x00000200
 Transmitter empty.
#define AT91_US_BAUD(baud)   ((NUT_CPU_FREQ / (8 * (baud)) + 1) / 2)
 Baud rate calculation helper macro.

Receiver Holding Register

#define US_RHR_OFF   0x00000018
 USART receiver holding register offset.
#define US0_RHR   (USART0_BASE + US_RHR_OFF)
 Channel 0 receiver holding register address.
#define US1_RHR   (USART1_BASE + US_RHR_OFF)
 Channel 1 receiver holding register address.

Transmitter Holding Register

#define US_THR_OFF   0x0000001C
 USART transmitter holding register offset.
#define US0_THR   (USART0_BASE + US_THR_OFF)
 Channel 0 transmitter holding register address.
#define US1_THR   (USART1_BASE + US_THR_OFF)
 Channel 1 transmitter holding register address.

Baud Rate Generator Register

#define US_BRGR_OFF   0x00000020
 USART baud rate register offset.
#define US0_BRGR   (USART0_BASE + US_BRGR_OFF)
 Channel 0 baud rate register address.
#define US1_BRGR   (USART1_BASE + US_BRGR_OFF)
 Channel 1 baud rate register address.

Receiver Timeout Register

#define US_RTOR_OFF   0x00000024
 USART receiver timeout register offset.
#define US0_RTOR   (USART0_BASE + US_RTOR_OFF)
 Channel 0 receiver timeout register address.
#define US1_RTOR   (USART1_BASE + US_RTOR_OFF)
 Channel 1 receiver timeout register address.

Transmitter Time Guard Register

#define US_TTGR_OFF   0x00000028
 USART transmitter time guard register offset.
#define US0_TTGR   (USART0_BASE + US_TTGR_OFF)
 Channel 0 transmitter time guard register address.
#define US1_TTGR   (USART1_BASE + US_TTGR_OFF)
 Channel 1 transmitter time guard register address.

Receive Pointer Register

#define US_RPR_OFF   0x00000030
 USART receive pointer register offset.
#define US0_RPR   (USART0_BASE + US_RPR_OFF)
 Channel 0 receive pointer register address.
#define US1_RPR   (USART1_BASE + US_RPR_OFF)
 Channel 1 receive pointer register address.

Receive Counter Register

#define US_RCR_OFF   0x00000034
 USART receive counter register offset.
#define US0_RCR   (USART0_BASE + US_RCR_OFF)
 Channel 0 receive counter register address.
#define US1_RCR   (USART1_BASE + US_RCR_OFF)
 Channel 1 receive counter register address.

Transmit Pointer Register

#define US_TPR_OFF   0x00000038
 USART transmit pointer register offset.
#define US0_TPR   (USART0_BASE + US_TPR_OFF)
 Channel 0 transmit pointer register address.
#define US1_TPR   (USART1_BASE + US_TPR_OFF)
 Channel 1 transmit pointer register address.

Transmit Counter Register

#define US_TCR_OFF   0x0000003C
 USART transmit counter register offset.
#define US0_TCR   (USART0_BASE + US_TCR_OFF)
 Channel 0 transmit counter register address.
#define US1_TCR   (USART1_BASE + US_TCR_OFF)
 Channel 1 transmit counter register address.

Timer Counter Control Register

#define TC0_CCR   (TC_BASE + 0x00)
 Channel 0 control register address.
#define TC1_CCR   (TC_BASE + 0x40)
 Channel 1 control register address.
#define TC2_CCR   (TC_BASE + 0x80)
 Channel 2 control register address.
#define TC_CLKEN   0x00000001
 Clock enable command.
#define TC_CLKDIS   0x00000002
 Clock disable command.
#define TC_SWTRG   0x00000004
 Software trigger command.

Timer Counter Channel Mode Register

#define TC0_CMR   (TC_BASE + 0x04)
 Channel 0 mode register address.
#define TC1_CMR   (TC_BASE + 0x44)
 Channel 1 mode register address.
#define TC2_CMR   (TC_BASE + 0x84)
 Channel 2 mode register address.
#define TC_CLKS   0x00000007
 Clock selection mask.
#define TC_CLKS_MCK2   0x00000000
 Selects MCK / 2.
#define TC_CLKS_MCK8   0x00000001
 Selects MCK / 8.
#define TC_CLKS_MCK32   0x00000002
 Selects MCK / 32.
#define TC_CLKS_MCK128   0x00000003
 Selects MCK / 128.
#define TC_CLKS_MCK1024   0x00000004
 Selects MCK / 1024.
#define TC_CLKS_XC0   0x00000005
 Selects external clock 0.
#define TC_CLKS_XC1   0x00000006
 Selects external clock 1.
#define TC_CLKS_XC2   0x00000007
 Selects external clock 2.
#define TC_CLKI   0x00000008
 Increments on falling edge.
#define TC_BURST   0x00000030
 Burst signal selection mask.
#define TC_BURST_NONE   0x00000000
 Clock is not gated by an external signal.
#define TC_BUSRT_XC0   0x00000010
 ANDed with external clock 0.
#define TC_BURST_XC1   0x00000020
 ANDed with external clock 1.
#define TC_BURST_XC2   0x00000030
 ANDed with external clock 2.
#define TC_CPCTRG   0x00004000
 RC Compare Enable Trigger Enable.
#define TC_WAVE   0x00008000
 Selects waveform mode.
#define TC_CAPT   0x00000000
 Selects capture mode.

Capture Mode

#define TC_LDBSTOP   0x00000040
 Counter clock stopped on RB loading.
#define TC_LDBDIS   0x00000080
 Counter clock disabled on RB loading.
#define TC_ETRGEDG   0x00000300
 External trigger edge selection mask.
#define TC_ETRGEDG_RISING_EDGE   0x00000100
 Trigger on external rising edge.
#define TC_ETRGEDG_FALLING_EDGE   0x00000200
 Trigger on external falling edge.
#define TC_ETRGEDG_BOTH_EDGE   0x00000300
 Trigger on both external edges.
#define TC_ABETRG   0x00000400
 TIOA or TIOB external trigger selection mask.
#define TC_ABETRG_TIOB   0x00000000
 TIOB used as an external trigger.
#define TC_ABETRG_TIOA   0x00000400
 TIOA used as an external trigger.
#define TC_LDRA   0x00030000
 RA loading selection mask.
#define TC_LDRA_RISING_EDGE   0x00010000
 Load RA on rising edge of TIOA.
#define TC_LDRA_FALLING_EDGE   0x00020000
 Load RA on falling edge of TIOA.
#define TC_LDRA_BOTH_EDGE   0x00030000
 Load RA on any edge of TIOA.
#define TC_LDRB   0x000C0000
 RB loading selection mask.
#define TC_LDRB_RISING_EDGE   0x00040000
 Load RB on rising edge of TIOA.
#define TC_LDRB_FALLING_EDGE   0x00080000
 Load RB on falling edge of TIOA.
#define TC_LDRB_BOTH_EDGE   0x000C0000
 Load RB on any edge of TIOA.

Waveform Mode

#define TC_CPCSTOP   0x00000040
 Counter clock stopped on RC compare.
#define TC_CPCDIS   0x00000080
 Counter clock disabled on RC compare.
#define TC_EEVTEDG   0x00000300
 External event edge selection mask.
#define TC_EEVTEDG_RISING_EDGE   0x00000100
 External event on rising edge.
#define TC_EEVTEDG_FALLING_EDGE   0x00000200
 External event on falling edge.
#define TC_EEVTEDG_BOTH_EDGE   0x00000300
 External event on any edge.
#define TC_EEVT   0x00000C00
 External event selection mask.
#define TC_EEVT_TIOB   0x00000000
 TIOB selected as external event.
#define TC_EEVT_XC0   0x00000400
 XC0 selected as external event.
#define TC_EEVT_XC1   0x00000800
 XC1 selected as external event.
#define TC_EEVT_XC2   0x00000C00
 XC2 selected as external event.
#define TC_ENETRG   0x00001000
 External event trigger enable.
#define TC_ACPA   0x00030000
 Masks RA compare effect on TIOA.
#define TC_ACPA_SET_OUTPUT   0x00010000
 RA compare sets TIOA.
#define TC_ACPA_CLEAR_OUTPUT   0x00020000
 RA compare clears TIOA.
#define TC_ACPA_TOGGLE_OUTPUT   0x00030000
 RA compare toggles TIOA.
#define TC_ACPC   0x000C0000
 Masks RC compare effect on TIOA.
#define TC_ACPC_SET_OUTPUT   0x00040000
 RC compare sets TIOA.
#define TC_ACPC_CLEAR_OUTPUT   0x00080000
 RC compare clears TIOA.
#define TC_ACPC_TOGGLE_OUTPUT   0x000C0000
 RC compare toggles TIOA.
#define TC_AEEVT   0x00300000
 Masks external event effect on TIOA.
#define TC_AEEVT_SET_OUTPUT   0x00100000
 External event sets TIOA.
#define TC_AEEVT_CLEAR_OUTPUT   0x00200000
 External event clears TIOA.
#define TC_AEEVT_TOGGLE_OUTPUT   0x00300000
 External event toggles TIOA.
#define TC_ASWTRG   0x00C00000
 Masks software trigger effect on TIOA.
#define TC_ASWTRG_SET_OUTPUT   0x00400000
 Software trigger sets TIOA.
#define TC_ASWTRG_CLEAR_OUTPUT   0x00800000
 Software trigger clears TIOA.
#define TC_ASWTRG_TOGGLE_OUTPUT   0x00C00000
 Software trigger toggles TIOA.
#define TC_BCPB   0x03000000
 Masks RB compare effect on TIOB.
#define TC_BCPB_SET_OUTPUT   0x01000000
 RB compare sets TIOB.
#define TC_BCPB_CLEAR_OUTPUT   0x02000000
 RB compare clears TIOB.
#define TC_BCPB_TOGGLE_OUTPUT   0x03000000
 RB compare toggles TIOB.
#define TC_BCPC   0x0C000000
 Masks RC compare effect on TIOB.
#define TC_BCPC_SET_OUTPUT   0x04000000
 RC compare sets TIOB.
#define TC_BCPC_CLEAR_OUTPUT   0x08000000
 RC compare clears TIOB.
#define TC_BCPC_TOGGLE_OUTPUT   0x0C000000
 RC compare toggles TIOB.
#define TC_BEEVT   0x30000000
 Masks external event effect on TIOB.
#define TC_BEEVT_SET_OUTPUT   0x10000000
 External event sets TIOB.
#define TC_BEEVT_CLEAR_OUTPUT   0x20000000
 External event clears TIOB.
#define TC_BEEVT_TOGGLE_OUTPUT   0x30000000
 External event toggles TIOB.
#define TC_BSWTRG   0xC0000000
 Masks software trigger effect on TIOB.
#define TC_BSWTRG_SET_OUTPUT   0x40000000
 Software trigger sets TIOB.
#define TC_BSWTRG_CLEAR_OUTPUT   0x80000000
 Software trigger clears TIOB.
#define TC_BSWTRG_TOGGLE_OUTPUT   0xC0000000
 Software trigger toggles TIOB.

Counter Value Register

#define TC0_CV   (TC_BASE + 0x10)
 Counter 0 value.
#define TC1_CV   (TC_BASE + 0x50)
 Counter 1 value.
#define TC2_CV   (TC_BASE + 0x90)
 Counter 2 value.

Timer Counter Register A

#define TC0_RA   (TC_BASE + 0x14)
 Channel 0 register A.
#define TC1_RA   (TC_BASE + 0x54)
 Channel 1 register A.
#define TC2_RA   (TC_BASE + 0x94)
 Channel 2 register A.

Timer Counter Register B

#define TC0_RB   (TC_BASE + 0x18)
 Channel 0 register B.
#define TC1_RB   (TC_BASE + 0x58)
 Channel 1 register B.
#define TC2_RB   (TC_BASE + 0x98)
 Channel 2 register B.

Timer Counter Register C

#define TC0_RC   (TC_BASE + 0x1C)
 Channel 0 register C.
#define TC1_RC   (TC_BASE + 0x5C)
 Channel 1 register C.
#define TC2_RC   (TC_BASE + 0x9C)
 Channel 2 register C.

Timer Counter Status and Interrupt Registers

#define TC0_SR   (TC_BASE + 0x20)
 Status register address.
#define TC1_SR   (TC_BASE + 0x60)
 Status register address.
#define TC2_SR   (TC_BASE + 0xA0)
 Status register address.
#define TC0_IER   (TC_BASE + 0x24)
 Channel 0 interrupt enable register address.
#define TC1_IER   (TC_BASE + 0x64)
 Channel 1 interrupt enable register address.
#define TC2_IER   (TC_BASE + 0xA4)
 Channel 2 interrupt enable register address.
#define TC0_IDR   (TC_BASE + 0x28)
 Channel 0 interrupt disable register address.
#define TC1_IDR   (TC_BASE + 0x68)
 Channel 1 interrupt disable register address.
#define TC2_IDR   (TC_BASE + 0xA8)
 Channel 2 interrupt disable register address.
#define TC0_IMR   (TC_BASE + 0x2C)
 Channel 0 interrupt mask register address.
#define TC1_IMR   (TC_BASE + 0x6C)
 Channel 1 interrupt mask register address.
#define TC2_IMR   (TC_BASE + 0xAC)
 Channel 2 interrupt mask register address.
#define TC_COVFS   0x00000001
 Counter overflow flag.
#define TC_LOVRS   0x00000002
 Load overrun flag.
#define TC_CPAS   0x00000004
 RA compare flag.
#define TC_CPBS   0x00000008
 RB compare flag.
#define TC_CPCS   0x00000010
 RC compare flag.
#define TC_LDRAS   0x00000020
 RA loading flag.
#define TC_LDRBS   0x00000040
 RB loading flag.
#define TC_ETRGS   0x00000080
 External trigger flag.
#define TC_CLKSTA   0x00010000
 Clock enable flag.
#define TC_MTIOA   0x00020000
 TIOA flag.
#define TC_MTIOB   0x00040000
 TIOB flag.

Timer Counter Block Control Register

#define TC_BCR   (TC_BASE + 0xC0)
 Block control register address.
#define TC_SYNC   0x00000001
 Synchronisation trigger.

Timer Counter Block Mode Register

#define TC_BMR   (TC_BASE + 0xC4)
 Block mode register address.
#define TC_TC0XC0S   0x00000003
 External clock signal 0 selection mask.
#define TC_TCLK0XC0   0x00000000
 Selects TCLK0.
#define TC_NONEXC0   0x00000001
 None selected.
#define TC_TIOA1XC0   0x00000002
 Selects TIOA1.
#define TC_TIOA2XC0   0x00000003
 Selects TIOA2.
#define TC_TC1XC1S   0x0000000C
 External clock signal 1 selection mask.
#define TC_TCLK1XC1   0x00000000
 Selects TCLK1.
#define TC_NONEXC1   0x00000004
 None selected.
#define TC_TIOA0XC1   0x00000008
 Selects TIOA0.
#define TC_TIOA2XC1   0x0000000C
 Selects TIOA2.
#define TC_TC2XC2S   0x00000030
 External clock signal 2 selection mask.
#define TC_TCLK2XC2   0x00000000
 Selects TCLK2.
#define TC_NONEXC2   0x00000010
 None selected.
#define TC_TIOA0XC2   0x00000020
 Selects TIOA0.
#define TC_TIOA1XC2   0x00000030
 Selects TIOA1.

PS Control Register

#define PS_CR   (PS_BASE + 0x00)
 Register address.

Peripheral Clock Control Registers

#define PS_PCER   (PS_BASE + 0x04)
 Peripheral clock enable register address.
#define PS_PCDR   (PS_BASE + 0x08)
 Peripheral clock disable register address.
#define PS_PCSR   (PS_BASE + 0x0C)
 Peripheral clock status register address.

Watch Dog Overflow Mode Register

#define WD_OMR   (WD_BASE + 0x00)
 Overflow mode register address.
#define WD_WDEN   0x00000001
 Watch Dog enable.
#define WD_RSTEN   0x00000002
 Internal reset enable.
#define WD_IRQEN   0x00000004
 Interrupt enable.
#define WD_EXTEN   0x00000008
 External signal enable.
#define WD_OKEY   0x00002340
 Overflow mode register access key.

Watch Dog Clock Register

#define WD_CMR   (WD_BASE + 0x04)
 Clock mode register address.
#define WD_WDCLKS   0x00000003
 Clock selection mask.
#define WD_WDCLKS_MCK8   0x00000000
 Selects MCK/8.
#define WD_WDCLKS_MCK32   0x00000001
 Selects MCK/32.
#define WD_WDCLKS_MCK128   0x00000002
 Selects MCK/128.
#define WD_WDCLKS_MCK1024   0x00000003
 Selects MCK/1024.
#define WD_HPCV   0x0000003C
 High preload counter value.
#define WD_CKEY   (0x06E<<7)
 Clock register access key.

Watch Dog Control Register

#define WD_CR   (WD_BASE + 0x08)
 Control register address.
#define WD_RSTKEY   0x0000C071
 Watch Dog restart key.

Watch Dog Status Register

#define WD_SR   (WD_BASE + 0x0C)
 Status register address.
#define WD_WDOVF   0x00000001
 Watch Dog overflow status.

Interrupt Source Mode Registers

#define AIC_SMR(i)   (AIC_BASE + i * 4)
 Source mode register array.
#define AIC_PRIOR   0x00000007
 Priority mask.
#define AIC_SRCTYPE   0x00000060
 Interrupt source type mask.
#define AIC_SRCTYPE_INT_LEVEL_SENSITIVE   0x00000000
 Internal level sensitive.
#define AIC_SRCTYPE_INT_EDGE_TRIGGERED   0x00000020
 Internal edge triggered.
#define AIC_SRCTYPE_EXT_LOW_LEVEL   0x00000000
 External low level.
#define AIC_SRCTYPE_EXT_NEGATIVE_EDGE   0x00000020
 External falling edge.
#define AIC_SRCTYPE_EXT_HIGH_LEVEL   0x00000040
 External high level.
#define AIC_SRCTYPE_EXT_POSITIVE_EDGE   0x00000060
 External rising edge.

Interrupt Source Vector Registers

#define AIC_SVR(i)   (AIC_BASE + 0x80 + i * 4)
 Source vector register array.

Interrupt Vector Register

#define AIC_IVR   (AIC_BASE + 0x100)
 IRQ vector register address.

Fast Interrupt Vector Register

#define AIC_FVR   (AIC_BASE + 0x104)
 FIQ vector register address.

Interrupt Status Register

#define AIC_ISR   (AIC_BASE + 0x108)
 Interrupt status register address.
#define AIC_IRQID   0x0000001F
 Current interrupt identifier mask.

Interrupt Pending Register

#define AIC_IPR   (AIC_BASE + 0x10C)
 Interrupt pending register address.

Interrupt Mask Register

#define AIC_IMR   (AIC_BASE + 0x110)
 Interrupt mask register address.

Interrupt Core Status Register

#define AIC_CISR   (AIC_BASE + 0x114)
 Core interrupt status register address.
#define AIC_NFIQ   0x00000001
 Core FIQ Status.
#define AIC_NIRQ   0x00000002
 Core IRQ Status.

Interrupt Enable Command Register

#define AIC_IECR   (AIC_BASE + 0x120)
 Interrupt enable command register address.

Interrupt Disable Command Register

#define AIC_IDCR   (AIC_BASE + 0x124)
 Interrupt disable command register address.

Interrupt Clear Command Register

#define AIC_ICCR   (AIC_BASE + 0x128)
 Interrupt clear command register address.

Interrupt Set Command Register

#define AIC_ISCR   (AIC_BASE + 0x12C)
 Interrupt set command register address.

End Of Interrupt Command Register

#define AIC_EOICR   (AIC_BASE + 0x130)
 End of interrupt command register address.

Spurious Interrupt Vector Register

#define AIC_SPU   (AIC_BASE + 0x134)
 Spurious vector register address.

Peripheral Identifiers and Interrupts

#define FIQ_ID   0
 Fast interrupt ID.
#define SWIRQ_ID   1
 Software interrupt ID.
#define US0_ID   2
 USART 0 ID.
#define US1_ID   3
 USART 1 ID.
#define TC0_ID   4
 Timer 0 ID.
#define TC1_ID   5
 Timer 1 ID.
#define TC2_ID   6
 Timer 2 ID.
#define WDI_ID   7
 Watchdog interrupt ID.
#define PIO_ID   8
 Parallel I/O controller ID.
#define IRQ0_ID   16
 External interrupt 0 ID.
#define IRQ1_ID   17
 External interrupt 1 ID.
#define IRQ2_ID   18
 External interrupt 2 ID.

Defines

#define EBI_BASE   0xFFE00000
 EBI base address.
#define SF_BASE   0xFFF00000
 Special function register base address.
#define USART1_BASE   0xFFFCC000
 USART 1 base address.
#define USART0_BASE   0xFFFD0000
 USART 0 base address.
#define TC_BASE   0xFFFE0000
 TC base address.
#define PIO_BASE   0xFFFF0000
 PIO base address.
#define PIO_PER   (PIO_BASE + 0x00)
 PIO enable register.
#define PIO_PDR   (PIO_BASE + 0x04)
 PIO disable register.
#define PIO_PSR   (PIO_BASE + 0x08)
 PIO status register.
#define PIO_OER   (PIO_BASE + 0x10)
 Output enable register.
#define PIO_ODR   (PIO_BASE + 0x14)
 Output disable register.
#define PIO_OSR   (PIO_BASE + 0x18)
 Output status register.
#define PIO_IFER   (PIO_BASE + 0x20)
 Input filter enable register.
#define PIO_IFDR   (PIO_BASE + 0x24)
 Input filter disable register.
#define PIO_IFSR   (PIO_BASE + 0x28)
 Input filter status register.
#define PIO_SODR   (PIO_BASE + 0x30)
 Set output data register.
#define PIO_CODR   (PIO_BASE + 0x34)
 Clear output data register.
#define PIO_ODSR   (PIO_BASE + 0x38)
 Output data status register.
#define PIO_PDSR   (PIO_BASE + 0x3C)
 Pin data status register.
#define PIO_IER   (PIO_BASE + 0x40)
 Interrupt enable register.
#define PIO_IDR   (PIO_BASE + 0x44)
 Interrupt disable register.
#define PIO_IMR   (PIO_BASE + 0x48)
 Interrupt mask register.
#define PIO_ISR   (PIO_BASE + 0x4C)
 Interrupt status register.
#define PS_BASE   0xFFFF4000
 PS base address.
#define WD_BASE   0xFFFF8000
 Watch Dog register base address.
#define AIC_BASE   0xFFFFF000
#define IRQ_ENTRY()
 Interrupt entry.
#define IRQ_EXIT()
 Interrupt exit.


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