Most parallel I/O lines are multiplexed with external signals of other peripherals to optimize the use of available package pins.
Defines | |
#define | PIO_BASE 0xFFFF0000 |
PIO base address. | |
#define | PIO_PER (PIO_BASE + 0x00) |
PIO enable register. | |
#define | PIO_PDR (PIO_BASE + 0x04) |
PIO disable register. | |
#define | PIO_PSR (PIO_BASE + 0x08) |
PIO status register. | |
#define | PIO_OER (PIO_BASE + 0x10) |
Output enable register. | |
#define | PIO_ODR (PIO_BASE + 0x14) |
Output disable register. | |
#define | PIO_OSR (PIO_BASE + 0x18) |
Output status register. | |
#define | PIO_IFER (PIO_BASE + 0x20) |
Input filter enable register. | |
#define | PIO_IFDR (PIO_BASE + 0x24) |
Input filter disable register. | |
#define | PIO_IFSR (PIO_BASE + 0x28) |
Input filter status register. | |
#define | PIO_SODR (PIO_BASE + 0x30) |
Set output data register. | |
#define | PIO_CODR (PIO_BASE + 0x34) |
Clear output data register. | |
#define | PIO_ODSR (PIO_BASE + 0x38) |
Output data status register. | |
#define | PIO_PDSR (PIO_BASE + 0x3C) |
Pin data status register. | |
#define | PIO_IER (PIO_BASE + 0x40) |
Interrupt enable register. | |
#define | PIO_IDR (PIO_BASE + 0x44) |
Interrupt disable register. | |
#define | PIO_IMR (PIO_BASE + 0x48) |
Interrupt mask register. | |
#define | PIO_ISR (PIO_BASE + 0x4C) |
Interrupt status register. |