Collaboration diagram for VLSI VS1001K:
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Defines | |
#define | VS_OPCODE_READ |
#define | VS_OPCODE_WRITE |
#define | VS_MODE_REG |
#define | VS_STATUS_REG |
#define | VS_INT_FCTLH_REG |
#define | VS_CLOCKF_REG |
#define | VS_DECODE_TIME_REG |
#define | VS_AUDATA_REG |
#define | VS_WRAM_REG |
#define | VS_WRAMADDR_REG |
#define | VS_HDAT0_REG |
#define | VS_HDAT1_REG |
#define | VS_A1ADDR_REG |
#define | VS_VOL_REG |
#define | VS_A1CTRL_REG |
#define | VS_SM_DIFF |
#define | VS_SM_FFWD |
#define | VS_SM_RESET |
#define | VS_SM_MP12 |
#define | VS_SM_PDOWN |
#define | VS_SM_DAC |
#define | VS_SM_DACMONO |
#define | VS_SM_BASS |
#define | VS_SM_DACT |
#define | VS_SM_BYTEORD |
#define | VS_SM_IBMODE |
#define | VS_SM_IBCLK |
#define | VS_CF_DOUBLER |
#define | VS_FLUSH_BYTES |
#define | VS_STATUS_STOPPED |
#define | VS_STATUS_RUNNING |
#define | VS_STATUS_EOF |
#define | VS_STATUS_EMPTY |
#define | VS_SCK_BIT |
VS1001 serial control interface clock input bit. | |
#define | VS_SCK_PORT |
#define | VS_SCK_DDR |
#define | VS_SS_BIT |
VS1001 serial data interface clock input bit. | |
#define | VS_SS_PORT |
#define | VS_SS_DDR |
#define | VS_SI_BIT |
VS1001 serial control interface data input. | |
#define | VS_SI_PORT |
#define | VS_SI_DDR |
#define | VS_SO_BIT |
VS1001 serial control interface data output. | |
#define | VS_SO_PIN |
#define | VS_SO_DDR |
#define | VS_XCS_BIT |
VS1001 active low chip select input. | |
#define | VS_XCS_PORT |
#define | VS_XCS_DDR |
#define | VS_BSYNC_BIT |
VS1001 serial data interface bit sync. | |
#define | VS_BSYNC_PORT |
#define | VS_BSYNC_DDR |
#define | VS_RESET_BIT |
VS1001 hardware reset input. | |
#define | VS_RESET_PORT |
#define | VS_RESET_DDR |
#define | VS_SIGNAL |
VS1001 data request interrupt. | |
#define | VS_DREQ_BIT |
#define | VS_DREQ_PORT |
#define | VS_DREQ_PIN |
#define | VS_DREQ_DDR |
Functions | |
int | VsPlayerInit (void) |
Initialize the VS1001 hardware interface. | |
int | VsPlayerReset (u_short mode) |
Software reset the decoder. | |
int | VsPlayerSetMode (u_short mode) |
Set mode register of the decoder. | |
int | VsPlayerKick (void) |
Start playback. | |
int | VsPlayerStop (void) |
Stops the playback. | |
int | VsPlayerFlush (void) |
Sets up decoder internal buffer flushing. | |
u_char | VsPlayerInterrupts (u_char enable) |
Enable or disable player interrupts. | |
u_char * | VsBufferInit (u_short size) |
u_char * | VsBufferReset (void) |
u_char * | VsBufferRequest (u_short *sizep) |
u_char * | VsBufferAcknowledge (u_short nbytes) |
u_short | VsBufferAvailable (void) |
u_short | VsPlayTime (void) |
Returns play time since last reset. | |
u_char | VsGetStatus (void) |
Returns status of the player. | |
u_short | VsMemoryTest (void) |
Initialize decoder memory test and return result. | |
int | VsSetVolume (u_char left, u_char right) |
Set volume. | |
int | VsBeep (u_char fsin, u_char ms) |
Sine wave beep. |
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VS1001 serial data interface bit sync. The first DCLK sampling edge, during which BSYNC is high, marks the first bit of a data byte. |
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Data direction register of VS_BSYNC_BIT. |
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Port output register of VS_BSYNC_BIT. |
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Data direction register of VS_DREQ_BIT. |
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Port input register of VS_DREQ_BIT. |
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Port output register of VS_DREQ_BIT. |
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Data direction register of VS_RESET_BIT. |
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Port output register of VS_RESET_BIT. |
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VS1001 serial control interface clock input bit. The first rising clock edge after XCS has gone low marks the first bit to be written to the decoder. |
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Data direction register of VS_SCK_BIT. |
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Port register of VS_SCK_BIT. |
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VS1001 serial control interface data input. The decoder samples this input on the rising edge of SCK if XCS is low. |
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Data direction register of VS_SI_BIT. |
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Port output register of VS_SI_BIT. |
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VS1001 serial control interface data output. If data is transfered from the decoder, bits are shifted out on the falling SCK edge. If data is transfered to the decoder, SO is at a high impedance state. |
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Data direction register of VS_SO_BIT. |
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Port input register of VS_SO_BIT. |
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Data direction register of VS_SS_BIT. |
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Port output register of VS_SS_BIT. |
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VS1001 active low chip select input. A high level forces the serial interface into standby mode, ending the current operation. A high level also forces serial output (SO) to high impedance state. |
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Data direction register of VS_XCS_BIT. |
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Port output register of VS_XCS_BIT. |
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Sine wave beep.
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Returns status of the player.
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Initialize decoder memory test and return result.
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Sets up decoder internal buffer flushing. This routine will set up internal VS buffer flushing, unless the buffer is already empty and starts the playback if necessary. The internal VS buffer is flushed in VsPlayerFeed() at the end of the stream. Decoder interrupts will be enabled.
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Initialize the VS1001 hardware interface.
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Enable or disable player interrupts. This routine is typically used by applications when dealing with unprotected buffers.
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Start playback. This routine will send the first MP3 data bytes to the decoder, until it is completely filled. The data buffer should have been filled before calling this routine. Decoder interrupts will be enabled.
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Software reset the decoder. This function is typically called after VsPlayerInit() and at the end of each track.
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Set mode register of the decoder.
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Stops the playback. This routine will stops the MP3 playback, VsPlayerKick() may be used to resume the playback.
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Returns play time since last reset.
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Set volume.
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