Defines | |
#define | EMAC_NCR |
Network Control Register. | |
#define | EMAC_LB |
Loopback. | |
#define | EMAC_LLB |
Loopback local. | |
#define | EMAC_RE |
Receive enable. | |
#define | EMAC_TE |
Transmit enable. | |
#define | EMAC_MPE |
Management port enable. | |
#define | EMAC_CLRSTAT |
Clear statistics registers. | |
#define | EMAC_INCSTAT |
Increment statistics registers. | |
#define | EMAC_WESTAT |
Write enable for statistics registers. | |
#define | EMAC_BP |
Back pressure. | |
#define | EMAC_TSTART |
Start Transmission. | |
#define | EMAC_THALT |
Transmission Halt. | |
#define | EMAC_TPFR |
Transmit pause frame. | |
#define | EMAC_TZQ |
Transmit zero quantum pause frame. | |
#define | EMAC_NCFGR |
Network Configuration Register. | |
#define | EMAC_SPD |
Speed. | |
#define | EMAC_FD |
Full duplex. | |
#define | EMAC_JFRAME |
Jumbo Frames. | |
#define | EMAC_CAF |
Copy all frames. | |
#define | EMAC_NBC |
No broadcast. | |
#define | EMAC_MTI |
Multicast hash event enable. | |
#define | EMAC_UNI |
Unicast hash enable. | |
#define | EMAC_BIG |
Receive 1522 bytes. | |
#define | EMAC_EAE |
External address match enable. | |
#define | EMAC_CLK |
#define | EMAC_CLK_HCLK_8 |
HCLK divided by 8. | |
#define | EMAC_CLK_HCLK_16 |
HCLK divided by 16. | |
#define | EMAC_CLK_HCLK_32 |
HCLK divided by 32. | |
#define | EMAC_CLK_HCLK_64 |
HCLK divided by 64. | |
#define | EMAC_RTY |
#define | EMAC_PAE |
#define | EMAC_RBOF |
#define | EMAC_RBOF_OFFSET_0 |
no offset from start of receive buffer | |
#define | EMAC_RBOF_OFFSET_1 |
one byte offset from start of receive buffer | |
#define | EMAC_RBOF_OFFSET_2 |
two bytes offset from start of receive buffer | |
#define | EMAC_RBOF_OFFSET_3 |
three bytes offset from start of receive buffer | |
#define | EMAC_RLCE |
Receive Length field Checking Enable. | |
#define | EMAC_DRFCS |
Discard Receive FCS. | |
#define | EMAC_EFRHD |
#define | EMAC_IRXFCS |
Ignore RX FCS. | |
#define | EMAC_NSR |
Network Status Register. | |
#define | EMAC_LINKR |
#define | EMAC_MDIO |
#define | EMAC_IDLE |
#define | EMAC_TSR |
Transmit Status Register. | |
#define | EMAC_UBR |
#define | EMAC_COL |
#define | EMAC_RLES |
#define | EMAC_TGO |
Transmit Go. | |
#define | EMAC_BEX |
Buffers exhausted mid frame. | |
#define | EMAC_COMP |
#define | EMAC_UND |
#define | EMAC_RBQP |
Receive Buffer Queue Pointer. | |
#define | EMAC_TBQP |
Transmit Buffer Queue Pointer. | |
#define | EMAC_RSR |
Receive Status Register. | |
#define | EMAC_BNA |
#define | EMAC_REC |
#define | EMAC_OVR |
#define | EMAC_ISR |
Interrupt Status Register. | |
#define | EMAC_MFD |
#define | EMAC_RCOMP |
#define | EMAC_RXUBR |
#define | EMAC_TXUBR |
#define | EMAC_TUNDR |
#define | EMAC_RLEX |
#define | EMAC_TXERR |
#define | EMAC_TCOMP |
#define | EMAC_LINK |
#define | EMAC_ROVR |
#define | EMAC_HRESP |
#define | EMAC_PFRE |
#define | EMAC_PTZ |
#define | EMAC_IER |
Interrupt Enable Register. | |
#define | EMAC_IDR |
Interrupt Disable Register. | |
#define | EMAC_IMR |
Interrupt Mask Register. | |
#define | EMAC_MAN |
PHY Maintenance Register. | |
#define | EMAC_DATA |
#define | EMAC_CODE |
#define | EMAC_REGA |
#define | EMAC_PHYA |
#define | EMAC_RW |
#define | EMAC_SOF |
#define | EMAC_PTR |
Pause Time Register. | |
#define | EMAC_PFR |
Pause Frames received Register. | |
#define | EMAC_FTO |
Frames Transmitted OK Register. | |
#define | EMAC_SCF |
Single Collision Frame Register. | |
#define | EMAC_MCF |
Multiple Collision Frame Register. | |
#define | EMAC_FRO |
Frames Received OK Register. | |
#define | EMAC_FCSE |
Frame Check Sequence Error Register. | |
#define | EMAC_ALE |
Alignment Error Register. | |
#define | EMAC_DTF |
Deferred Transmission Frame Register. | |
#define | EMAC_LCOL |
Late Collision Register. | |
#define | EMAC_ECOL |
Excessive Collision Register. | |
#define | EMAC_TUND |
Transmit Underrun Error Register. | |
#define | EMAC_CSE |
Carrier Sense Error Register. | |
#define | EMAC_RRE |
Receive Ressource Error Register. | |
#define | EMAC_ROV |
Receive Overrun Errors Register. | |
#define | EMAC_RSE |
Receive Symbol Errors Register. | |
#define | EMAC_ELE |
Excessive Length Errors Register. | |
#define | EMAC_RJA |
Receive Jabbers Register. | |
#define | EMAC_USF |
Undersize Frames Register. | |
#define | EMAC_STE |
SQE Test Error Register. | |
#define | EMAC_RLE |
Receive Length Field Mismatch Register. | |
#define | EMAC_TPF |
Transmitted Pause Frames Register. | |
#define | EMAC_HRB |
Hash Address Bottom[31:0]. | |
#define | EMAC_HRT |
Hash Address Top[63:32]. | |
#define | EMAC_SA1L |
Specific Address 1 Bottom, First 4 bytes. | |
#define | EMAC_SA1H |
Specific Address 1 Top, Last 2 bytes. | |
#define | EMAC_SA2L |
Specific Address 2 Bottom, First 4 bytes. | |
#define | EMAC_SA2H |
Specific Address 2 Top, Last 2 bytes. | |
#define | EMAC_SA3L |
Specific Address 3 Bottom, First 4 bytes. | |
#define | EMAC_SA3H |
Specific Address 3 Top, Last 2 bytes. | |
#define | EMAC_SA4L |
Specific Address 4 Bottom, First 4 bytes. | |
#define | EMAC_SA4H |
Specific Address 4 Top, Last 2 bytes. | |
#define | EMAC_TID |
Type ID Checking Register. | |
#define | EMAC_TPQ |
Transmit Pause Quantum Register. | |
#define | EMAC_USRIO |
USER Input/Output Register. | |
#define | EMAC_RMII |
Enable reduced MII. | |
#define | EMAC_CLKEN |
Enable tranceiver input clock. | |
#define | EMAC_WOL |
Wake On LAN Register. | |
#define | EMAC_IP |
ARP request IP address. | |
#define | EMAC_MAG |
Magic packet event enable. | |
#define | EMAC_ARP |
ARP request event enable. | |
#define | EMAC_SA1 |
Specific address register 1 event enable. | |
#define | EMAC_REV |
Revision Register. | |
#define | EMAC_REVREF |
#define | EMAC_PARTREF |
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Loopback. Optional. When set, loopback signal is at high level. |