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XgNutArchArmAt91Pmc


Defines

#define PMC_SCER_OFF
 System clock enable register offset.
#define PMC_SCER
 System clock enable register.
#define PMC_SCDR_OFF
 System clock disable register offset.
#define PMC_SCDR
 System clock disable register.
#define PMC_SCSR_OFF
 System clock status register offset.
#define PMC_SCSR
 System clock status register.
#define PMC_PCK
 Processor clock.
#define PMC_UDP
 USB device port clock.
#define PMC_PCK0
 Programmable clock 0 output.
#define PMC_PCK1
 Programmable clock 1 output.
#define PMC_PCK2
 Programmable clock 2 output.
#define PMC_PCK3
 Programmable clock 3 output.
#define PMC_PCER_OFF
 Peripheral clock enable register offset.
#define PMC_PCER
 Peripheral clock enable register.
#define PMC_PCDR_OFF
 Peripheral clock disable register offset.
#define PMC_PCDR
 Peripheral clock disable register.
#define PMC_PCSR_OFF
 Peripheral clock status register offset.
#define PMC_PCSR
 Peripheral clock status register.
#define CKGR_MOR_OFF
 Clock generator main oscillator register offset.
#define CKGR_MOR
 Clock generator main oscillator register.
#define CKGR_MOSCEN
 Main oscillator enable.
#define CKGR_OSCBYPASS
 Main oscillator bypass.
#define CKGR_OSCOUNT
 Main oscillator start-up time.
#define CKGR_MCFR_OFF
 Clock generator main clock frequency register offset.
#define CKGR_MCFR
 Clock generator main clock frequency register.
#define CKGR_MAINF
 Main clock frequency.
#define CKGR_MAINRDY
 Main clock ready.
#define CKGR_PLLR_OFF
 Clock generator PLL register offset.
#define CKGR_PLLR
 Clock generator PLL register.
#define CKGR_DIV
 Divider.
#define CKGR_DIV_LSB
 Least significant bit of the divider.
#define CKGR_DIV_0
 Divider output is 0.
#define CKGR_DIV_BYPASS
 Divider is bypassed.
#define CKGR_PLLCOUNT
 PLL counter.
#define CKGR_OUT
 PLL output frequency range.
#define CKGR_OUT_0
 Please refer to the PLL datasheet.
#define CKGR_OUT_1
 Please refer to the PLL datasheet.
#define CKGR_OUT_2
 Please refer to the PLL datasheet.
#define CKGR_OUT_3
 Please refer to the PLL datasheet.
#define CKGR_MUL
 PLL multiplier.
#define CKGR_MUL_LSB
 Least significant bit of the PLL multiplier.
#define CKGR_USBDIV
 Divider for USB clocks.
#define CKGR_USBDIV_0
 Divider output is PLL clock output.
#define CKGR_USBDIV_1
 Divider output is PLL clock output divided by 2.
#define CKGR_USBDIV_2
 Divider output is PLL clock output divided by 4.
#define PMC_MCKR_OFF
 Master clock register offset.
#define PMC_MCKR
 Master clock register.
#define PMC_PCKR0_OFF
 Programmable clock 0 register offset.
#define PMC_PCKR0
 Programmable clock 0 register.
#define PMC_PCKR1_OFF
 Programmable clock 1 register offset.
#define PMC_PCKR1
 Programmable clock 1 register.
#define PMC_PCKR2_OFF
 Programmable clock 2 register offset.
#define PMC_PCKR2
 Programmable clock 2 register.
#define PMC_PCKR3_OFF
 Programmable clock 3 register offset.
#define PMC_PCKR3
 Programmable clock 3 register.
#define PMC_CSS
 Clock selection mask.
#define PMC_CSS_LSB
 Least significant bit of the clock selection.
#define PMC_CSS_SLOW_CLK
 Slow clock selected.
#define PMC_CSS_MAIN_CLK
 Main clock selected.
#define PMC_CSS_PLL_CLK
 PLL clock selected.
#define PMC_PRES
 Clock prescaler mask.
#define PMC_PRES_LSB
 Clock prescaler's least signigifcant bit.
#define PMC_PRES_CLK
 Selected clock, not divided.
#define PMC_PRES_CLK_2
 Selected clock divided by 2.
#define PMC_PRES_CLK_4
 Selected clock divided by 4.
#define PMC_PRES_CLK_8
 Selected clock divided by 8.
#define PMC_PRES_CLK_16
 Selected clock divided by 16.
#define PMC_PRES_CLK_32
 Selected clock divided by 32.
#define PMC_PRES_CLK_64
 Selected clock divided by 64.
#define PMC_IER_OFF
 PMC interrupt enable register offset.
#define PMC_IER
 PMC interrupt enable register.
#define PMC_IDR_OFF
 PMC interrupt disable register offset.
#define PMC_IDR
 PMC interrupt disable register.
#define PMC_SR_OFF
 PMC status register offset.
#define PMC_SR
 PMC status register.
#define PMC_IMR_OFF
 PMC interrupt mask register offset.
#define PMC_IMR
 PMC interrupt mask register.
#define PMC_MOSCS
 Main oscillator.
#define PMC_LOCK
 PLL lock.
#define PMC_MCKRDY
 Master clock ready.
#define PMC_PCKRDY0
 Programmable clock 0 ready.
#define PMC_PCKRDY1
 Programmable clock 1 ready.
#define PMC_PCKRDY2
 Programmable clock 2 ready.
#define PMC_PCKRDY3
 Programmable clock 3 ready.


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