Watch Dog Control Register | |
#define | WDT_CR_OFF |
Watchdog control register offset. | |
#define | WDT_CR |
Watchdog control register address. | |
#define | WDT_WDRSTT |
Watchdog restart. | |
#define | WDT_KEY |
Watchdog password. | |
Watch Dog Mode Register | |
#define | WDT_MR_OFF |
Mode register offset. | |
#define | WDT_MR |
Mode register address. | |
#define | WDT_WDV |
Counter value mask. | |
#define | WDT_WDFIEN |
Fault interrupt enable. | |
#define | WDT_WDRSTEN |
Reset enable. | |
#define | WDT_WDRPROC |
Eset processor enable. | |
#define | WDT_WDDIS |
Watchdog disable. | |
#define | WDT_WDD |
Delta value mask. | |
#define | WDT_WDDBGHLT |
Watchdog debug halt. | |
#define | WDT_WDIDLEHLT |
Watchdog idle halt. | |
Watch Dog Status Register | |
#define | WDT_SR_OFF |
Status register offset. | |
#define | WDT_SR |
Status register address. | |
#define | WDT_WDUNF |
Watchdog underflow. | |
#define | WDT_WDERR |
Watchdog error. |