* * $Log: at91_mc.h,v $ * Revision 1.3 2006/07/26 11:21:35 haraldkipp * Made it usable for assembler. * * Revision 1.2 2006/07/18 14:04:55 haraldkipp * Base address removed. Should be specified in the upper level header. * * Revision 1.1 2006/07/05 07:45:28 haraldkipp * Split on-chip interface definitions. * * *
Defines | |
#define | MC_RCR_OFF |
MC remap control register offset. | |
#define | MC_RCR |
MC remap control register address. | |
#define | MC_RCB |
Remap command. | |
#define | MC_ASR_OFF |
MC abort status register offset. | |
#define | MC_ASR |
MC abort status register address. | |
#define | MC_UNDADD |
Undefined Addess Abort status. | |
#define | MC_MISADD |
Misaligned Addess Abort status. | |
#define | MC_ABTSZ_MASK |
Abort size status mask. | |
#define | MC_ABTSZ_BYTE |
Byte size abort. | |
#define | MC_ABTSZ_HWORD |
Half-word size abort. | |
#define | MC_ABTSZ_WORD |
Word size abort. | |
#define | MC_ABTTYP_MASK |
Abort type status mask. | |
#define | MC_ABTTYP_DATAR |
Data read abort. | |
#define | MC_ABTTYP_DATAW |
Data write abort. | |
#define | MC_ABTTYP_FETCH |
Code fetch abort. | |
#define | MC_MST_EMAC |
EMAC abort source. | |
#define | MC_MST_PDC |
PDC abort source. | |
#define | MC_MST_ARM |
ARM abort source. | |
#define | MC_SVMST_EMAC |
Saved EMAC abort source. | |
#define | MC_SVMST_PDC |
Saved PDC abort source. | |
#define | MC_SVMST_ARM |
Saved ARM abort source. | |
#define | MC_AASR_OFF |
MC abort address status register offset. | |
#define | MC_AASR |
MC abort address status register address. | |
#define | MC_FMR_OFF |
MC flash mode register offset. | |
#define | MC_FMR |
MC flash mode register address. | |
#define | MC_FRDY |
Flash ready. | |
#define | MC_LOCKE |
Lock error. | |
#define | MC_PROGE |
Programming error. | |
#define | MC_NEBP |
No erase before programming. | |
#define | MC_FWS_MASK |
Flash wait state mask. | |
#define | MC_FWS_1R2W |
1 cycle for read, 2 for write operations | |
#define | MC_FWS_2R3W |
2 cycles for read, 3 for write operations | |
#define | MC_FWS_3R4W |
3 cycles for read, 4 for write operations | |
#define | MC_FWS_4R4W |
4 cycles for read and write operations | |
#define | MC_FMCN_MASK |
Flash microsecond cycle number mask. | |
#define | MC_FCR_OFF |
MC flash command register offset. | |
#define | MC_FCR |
MC flash command register address. | |
#define | MC_FCMD_MASK |
Flash command mask. | |
#define | MC_FCMD_NOP |
No command. | |
#define | MC_FCMD_WP |
Write page. | |
#define | MC_FCMD_SLB |
Set lock bit. | |
#define | MC_FCMD_WPL |
Write page and lock. | |
#define | MC_FCMD_CLB |
Clear lock bit. | |
#define | MC_FCMD_EA |
Erase all. | |
#define | MC_FCMD_SGPB |
Set general purpose NVM bit. | |
#define | MC_FCMD_CGPB |
Clear general purpose NVM bit. | |
#define | MC_FCMD_SSB |
Set security bit. | |
#define | MC_PAGEN_MASK |
Page number mask. | |
#define | MC_KEY |
Writing protect key. | |
#define | MC_FSR_OFF |
MC flash status register offset. | |
#define | MC_FSR |
MC flash status register address. | |
#define | MC_SECURITY |
Security bit status. | |
#define | MC_GPNVM0 |
General purpose NVM bit 0. | |
#define | MC_GPNVM1 |
General purpose NVM bit 1. | |
#define | MC_GPNVM2 |
General purpose NVM bit 2. | |
#define | MC_LOCKS0 |
Lock region 0 lock status. | |
#define | MC_LOCKS1 |
Lock region 1 lock status. | |
#define | MC_LOCKS2 |
Lock region 2 lock status. | |
#define | MC_LOCKS3 |
Lock region 3 lock status. | |
#define | MC_LOCKS4 |
Lock region 4 lock status. | |
#define | MC_LOCKS5 |
Lock region 5 lock status. | |
#define | MC_LOCKS6 |
Lock region 6 lock status. | |
#define | MC_LOCKS7 |
Lock region 7 lock status. | |
#define | MC_LOCKS8 |
Lock region 8 lock status. | |
#define | MC_LOCKS9 |
Lock region 9 lock status. | |
#define | MC_LOCKS10 |
Lock region 10 lock status. | |
#define | MC_LOCKS11 |
Lock region 11 lock status. | |
#define | MC_LOCKS12 |
Lock region 12 lock status. | |
#define | MC_LOCKS13 |
Lock region 13 lock status. | |
#define | MC_LOCKS14 |
Lock region 14 lock status. | |
#define | MC_LOCKS15 |
Lock region 15 lock status. |