00001 #ifndef _ARCH_ARM_AT91_SMC_H_
00002 #define _ARCH_ARM_AT91_SMC_H_
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00054
00057 #define SMC_SETUP(cs) (SMC_BASE + 0x10 * cs + 0x00)
00058 #define SMC_NWE_SETUP 0x0000003F
00059 #define SMC_NWE_SETUP_LSB 0
00060 #define SMC_NCS_WR_SETUP 0x00003F00
00061 #define SMC_NCS_WR_SETUP_LSB 8
00062 #define SMC_NRD_SETUP 0x003F0000
00063 #define SMC_NRD_SETUP_LSB 16
00064 #define SMC_NCS_RD_SETUP 0x3F000000
00065 #define SMC_NCS_RD_SETUP_LSB 24
00067
00068
00070 #define SMC_PULSE(cs) (SMC_BASE + 0x10 * cs + 0x04)
00071 #define SMC_NWE_PULSE 0x0000003F
00072 #define SMC_NWE_PULSE_LSB 0
00073 #define SMC_NCS_WR_PULSE 0x00003F00
00074 #define SMC_NCS_WR_PULSE_LSB 8
00075 #define SMC_NRD_PULSE 0x003F0000
00076 #define SMC_NRD_PULSE_LSB 16
00077 #define SMC_NCS_RD_PULSE 0x3F000000
00078 #define SMC_NCS_RD_PULSE_LSB 24
00080
00081
00083 #define SMC_CYCLE(cs) (SMC_BASE + 0x10 * cs + 0x08)
00084 #define SMC_NWE_CYCLE 0x000001FF
00085 #define SMC_NWE_CYCLE_LSB 0
00086 #define SMC_NRD_CYCLE 0x01FF0000
00087 #define SMC_NRD_CYCLE_LSB 16
00089
00090
00092 #define SMC_MODE(cs) (SMC_BASE + 0x10 * cs + 0x0C)
00093 #define SMC_READ_MODE 0x00000001
00094 #define SMC_WRITE_MODE 0x00000002
00095 #define SMC_EXNW_MODE 0x00000030
00096 #define SMC_EXNW_MODE_DISABLED 0x00000000
00097 #define SMC_EXNW_MODE_FROZEN 0x00000020
00098 #define SMC_EXNW_MODE_READY 0x00000030
00099 #define SMC_BAT 0x00000100
00100 #define SMC_DBW 0x00003000
00101 #define SMC_DBW_8 0x00000000
00102 #define SMC_DBW_16 0x00001000
00103 #define SMC_DBW_32 0x00002000
00104 #define SMC_TDF_CYCLES 0x000F0000
00105 #define SMC_TDF_CYCLES_LSB 0x000F0000
00106 #define SMC_TDF_MODE 0x00100000
00107 #define SMC_PMEN 0x01000000
00108 #define SMC_PS 0x30000000
00109 #define SMC_PS_4 0x30000000
00110 #define SMC_PS_8 0x30000000
00111 #define SMC_PS_16 0x30000000
00112 #define SMC_PS_32 0x30000000
00114
00115
00118 #endif