ih_at91fiq.c

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00001 /*
00002  * Copyright (C) 2005 by egnite Software GmbH. All rights reserved.
00003  *
00004  * Redistribution and use in source and binary forms, with or without
00005  * modification, are permitted provided that the following conditions
00006  * are met:
00007  *
00008  * 1. Redistributions of source code must retain the above copyright
00009  *    notice, this list of conditions and the following disclaimer.
00010  * 2. Redistributions in binary form must reproduce the above copyright
00011  *    notice, this list of conditions and the following disclaimer in the
00012  *    documentation and/or other materials provided with the distribution.
00013  * 3. Neither the name of the copyright holders nor the names of
00014  *    contributors may be used to endorse or promote products derived
00015  *    from this software without specific prior written permission.
00016  *
00017  * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
00018  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00019  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00020  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
00021  * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
00022  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
00023  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
00024  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
00025  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00026  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
00027  * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
00028  * SUCH DAMAGE.
00029  *
00030  * For additional information see http://www.ethernut.de/
00031  *
00032  */
00033 
00034 /*
00035  * $Log: ih_at91fiq.c,v $
00036  * Revision 1.3  2006/06/28 17:10:15  haraldkipp
00037  * Include more general header file for ARM.
00038  *
00039  * Revision 1.2  2006/04/07 12:19:51  haraldkipp
00040  * Fast interrupts are now enabled correctly.
00041  * Mode set/get ioctl added and priority set/get removed.
00042  * Interrupt entry will no longer push R8-R12 on stack.
00043  *
00044  * Revision 1.1  2005/10/24 08:56:09  haraldkipp
00045  * First check in.
00046  *
00047  */
00048 
00049 #include <arch/arm.h>
00050 #include <dev/irqreg.h>
00051 
00052 #ifndef NUT_IRQPRI_FIQ
00053 #define NUT_IRQPRI_FIQ  4
00054 #endif
00055 
00056 static int FastIrqCtl(int cmd, void *param);
00057 
00058 IRQ_HANDLER sig_FIQ = {
00059 #ifdef NUT_PERFMON
00060     0,              /* Interrupt counter, ir_count. */
00061 #endif
00062     NULL,           /* Passed argument, ir_arg. */
00063     NULL,           /* Handler subroutine, ir_handler. */
00064     FastIrqCtl      /* Interrupt control, ir_ctl. */
00065 };
00066 
00072 static void FastIrqEntry(void) __attribute__ ((naked));
00073 void FastIrqEntry(void)
00074 {
00075     FIQ_ENTRY();
00076 #ifdef NUT_PERFMON
00077     sig_FIQ.ir_count++;
00078 #endif
00079     if (sig_FIQ.ir_handler) {
00080         (sig_FIQ.ir_handler) (sig_FIQ.ir_arg);
00081     }
00082     FIQ_EXIT();
00083 }
00084 
00100 static int FastIrqCtl(int cmd, void *param)
00101 {
00102     int rc = 0;
00103     u_int *ival = (u_int *)param;
00104     int enabled = inr(AIC_IMR) & _BV(FIQ_ID);
00105 
00106     /* Disable interrupt. */
00107     if (enabled) {
00108         outr(AIC_IDCR, _BV(FIQ_ID));
00109     }
00110 
00111     switch(cmd) {
00112     case NUT_IRQCTL_INIT:
00113         /* Set the vector. */
00114         outr(AIC_SVR(FIQ_ID), (unsigned int)FastIrqEntry);
00115         /* Initialize to edge triggered with defined priority. */
00116         outr(AIC_SMR(FIQ_ID), AIC_SRCTYPE_EXT_NEGATIVE_EDGE | NUT_IRQPRI_FIQ);
00117         /* Clear interrupt */
00118         outr(AIC_ICCR, _BV(FIQ_ID));
00119         break;
00120     case NUT_IRQCTL_STATUS:
00121         if (enabled) {
00122             *ival |= 1;
00123         }
00124         else {
00125             *ival &= ~1;
00126         }
00127         break;
00128     case NUT_IRQCTL_ENABLE:
00129         enabled = 1;
00130         break;
00131     case NUT_IRQCTL_DISABLE:
00132         enabled = 0;
00133         break;
00134     case NUT_IRQCTL_GETMODE:
00135         {
00136             u_int val = inr(AIC_SMR(FIQ_ID)) & AIC_SRCTYPE;
00137             if (val == AIC_SRCTYPE_EXT_LOW_LEVEL) {
00138                 *ival = NUT_IRQMODE_LOWLEVEL;
00139             } else if (val == AIC_SRCTYPE_EXT_HIGH_LEVEL) {
00140                 *ival = NUT_IRQMODE_HIGHLEVEL;
00141             } else if (val == AIC_SRCTYPE_EXT_POSITIVE_EDGE) {
00142                 *ival = NUT_IRQMODE_RISINGEDGE;
00143             } else  {
00144                 *ival = NUT_IRQMODE_FALLINGEDGE;
00145             }
00146         }
00147         break;
00148     case NUT_IRQCTL_SETMODE:
00149         if (*ival == NUT_IRQMODE_LOWLEVEL) {
00150             outr(AIC_SMR(FIQ_ID), (inr(AIC_SMR(FIQ_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_EXT_LOW_LEVEL);
00151         } else if (*ival == NUT_IRQMODE_HIGHLEVEL) {
00152             outr(AIC_SMR(FIQ_ID), (inr(AIC_SMR(FIQ_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_EXT_HIGH_LEVEL);
00153         } else if (*ival == NUT_IRQMODE_FALLINGEDGE) {
00154             outr(AIC_SMR(FIQ_ID), (inr(AIC_SMR(FIQ_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_EXT_NEGATIVE_EDGE);
00155         } else  if (*ival == NUT_IRQMODE_RISINGEDGE) {
00156             outr(AIC_SMR(FIQ_ID), (inr(AIC_SMR(FIQ_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_EXT_POSITIVE_EDGE);
00157         } else  {
00158             rc = -1;
00159         }
00160         break;
00161 #ifdef NUT_PERFMON
00162     case NUT_IRQCTL_GETCOUNT:
00163         *ival = (u_int)sig_FIQ.ir_count;
00164         sig_FIQ.ir_count = 0;
00165         break;
00166 #endif
00167     default:
00168         rc = -1;
00169         break;
00170     }
00171 
00172     /* Enable interrupt. */
00173     if (enabled) {
00174         outr(AIC_IECR, _BV(FIQ_ID));
00175     }
00176     return rc;
00177 }

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