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00064 #include <cfg/clock.h>
00065
00066 #include <sys/atom.h>
00067 #include <sys/event.h>
00068 #include <sys/timer.h>
00069
00070 #include <dev/irqreg.h>
00071
00072 #include <dev/usartat91.h>
00073
00078
00079
00080 #define ASCII_XON 0x11
00081
00082 #define ASCII_XOFF 0x13
00083
00084
00085 #define XON_PENDING 0x10
00086
00087 #define XOFF_PENDING 0x20
00088
00089 #define XOFF_SENT 0x40
00090
00091 #define XOFF_RCVD 0x80
00092
00093
00097 static ureg_t rx_errors;
00098
00102 static ureg_t flow_control;
00103
00107 static ureg_t tx_aframe;
00108
00109 #ifdef UART_HDX_BIT
00110
00111 #ifdef UART_HDX_FLIP_BIT
00112 #define UART_HDX_TX cbi
00113 #define UART_HDX_RX sbi
00114 #else
00115 #define UART_HDX_TX sbi
00116 #define UART_HDX_RX cbi
00117 #endif
00118 #endif
00119
00120
00121 #ifdef UART_HDX_BIT
00122
00128 static ureg_t hdx_control;
00129 #endif
00130
00131 #ifdef UART_RTS_BIT
00132
00138 static ureg_t rts_control;
00139 #endif
00140
00141 #ifdef UART_CTS_BIT
00142
00148 static ureg_t cts_sense;
00149 #endif
00150
00151 #ifdef UART_CTS_BIT
00152
00162 static void At91UsartCts(void *arg)
00163 {
00164
00165
00166
00167
00168 }
00169 #endif
00170
00171 #ifdef UART_HDX_BIT
00172
00173
00174
00175
00176
00177
00178
00179
00180
00181
00182
00183 static void At91UsartTxEmpty(RINGBUF *rbf)
00184 {
00185
00186
00187
00188
00189 if (hdx_control && rbf->rbf_cnt == 0) {
00190
00191 UART_HDX_RX(UART_HDX_PORT, UART_HDX_BIT);
00192 }
00193 }
00194 #endif
00195
00196
00197
00198
00199
00200
00201 static void At91UsartTxReady(RINGBUF *rbf)
00202 {
00203 register u_char *cp = rbf->rbf_tail;
00204
00205
00206
00207
00208 if (flow_control & (XON_PENDING | XOFF_PENDING)) {
00209 if (flow_control & XON_PENDING) {
00210 outr(USARTn_BASE + US_THR_OFF, ASCII_XOFF);
00211 flow_control |= XOFF_SENT;
00212 } else {
00213 outr(USARTn_BASE + US_THR_OFF, ASCII_XON);
00214 flow_control &= ~XOFF_SENT;
00215 }
00216 flow_control &= ~(XON_PENDING | XOFF_PENDING);
00217 return;
00218 }
00219
00220 if (flow_control & XOFF_RCVD) {
00221
00222
00223
00224
00225 outr(USARTn_BASE + US_IDR_OFF, US_TXRDY);
00226 return;
00227 }
00228
00229 if (rbf->rbf_cnt) {
00230
00231 #ifdef UART_CTS_BIT
00232
00233
00234
00235
00236 if (cts_sense && bit_is_set(UART_CTS_PIN, UART_CTS_BIT)) {
00237 outr(USARTn_BASE + US_IDR_OFF, US_TXRDY);
00238 sbi(EIMSK, UART_CTS_BIT);
00239 return;
00240 }
00241 #endif
00242 rbf->rbf_cnt--;
00243
00244
00245
00246
00247 if (tx_aframe) {
00248 outr(USARTn_BASE + US_CR_OFF, US_SENDA);
00249 }
00250
00251
00252
00253
00254 outr(USARTn_BASE + US_THR_OFF, *cp);
00255
00256
00257
00258
00259 if (++cp == rbf->rbf_last) {
00260 cp = rbf->rbf_start;
00261 }
00262 rbf->rbf_tail = cp;
00263 if (rbf->rbf_cnt == rbf->rbf_lwm) {
00264 NutEventPostFromIrq(&rbf->rbf_que);
00265 }
00266 }
00267
00268
00269
00270
00271 else {
00272 outr(USARTn_BASE + US_IDR_OFF, US_TXRDY);
00273 rbf->rbf_cnt = 0;
00274 NutEventPostFromIrq(&rbf->rbf_que);
00275 }
00276 }
00277
00278
00279
00280
00281
00282
00283
00284
00285
00286 static void At91UsartRxReady(RINGBUF *rbf)
00287 {
00288 register size_t cnt;
00289 register u_char ch;
00290
00291
00292
00293
00294
00295 ch = inb(USARTn_BASE + US_RHR_OFF);
00296
00297
00298 rx_errors |= inr(USARTn_BASE + US_CSR_OFF) & (US_OVRE | US_FRAME | US_PARE);
00299
00300
00301
00302
00303
00304
00305 if (flow_control) {
00306
00307 if (ch == ASCII_XOFF) {
00308 outr(USARTn_BASE + US_IDR_OFF, US_TXRDY);
00309 flow_control |= XOFF_RCVD;
00310 return;
00311 }
00312
00313 else if (ch == ASCII_XON) {
00314 outr(USARTn_BASE + US_IER_OFF, US_TXRDY);
00315 flow_control &= ~XOFF_RCVD;
00316 return;
00317 }
00318 }
00319
00320
00321
00322
00323 cnt = rbf->rbf_cnt;
00324 if (cnt >= rbf->rbf_siz) {
00325 rx_errors |= US_OVRE;
00326 return;
00327 }
00328
00329
00330 if (cnt++ == 0){
00331 NutEventPostFromIrq(&rbf->rbf_que);
00332 }
00333
00334
00335
00336
00337
00338 else if (flow_control) {
00339 if(cnt >= rbf->rbf_hwm) {
00340 if((flow_control & XOFF_SENT) == 0) {
00341 if (inr(USARTn_BASE + US_CSR_OFF) & US_TXRDY) {
00342 outb(USARTn_BASE + US_THR_OFF, ASCII_XOFF);
00343 flow_control |= XOFF_SENT;
00344 flow_control &= ~XOFF_PENDING;
00345 } else {
00346 flow_control |= XOFF_PENDING;
00347 }
00348 }
00349 }
00350 }
00351
00352 #ifdef UART_RTS_BIT
00353
00354
00355
00356
00357 else if (rts_control && cnt >= rbf->rbf_hwm) {
00358 sbi(UART_RTS_PORT, UART_RTS_BIT);
00359 }
00360 #endif
00361
00362
00363
00364
00365 *rbf->rbf_head++ = ch;
00366 if (rbf->rbf_head == rbf->rbf_last) {
00367 rbf->rbf_head = rbf->rbf_start;
00368 }
00369
00370
00371 rbf->rbf_cnt = cnt;
00372 }
00373
00379 static void At91UsartInterrupt(void *arg)
00380 {
00381 USARTDCB *dcb = (USARTDCB *)arg;
00382 ureg_t csr = inr(USARTn_BASE + US_CSR_OFF);
00383
00384 if (csr & US_RXRDY) {
00385 At91UsartRxReady(&dcb->dcb_rx_rbf);
00386 }
00387 if (csr & US_TXRDY) {
00388 At91UsartTxReady(&dcb->dcb_tx_rbf);
00389 }
00390
00391 #ifdef UART_HDX_BIT
00392 if (csr & US_TXEMPTY) {
00393 At91UsartTxEmpty(&dcb->dcb_tx_rbf);
00394 }
00395 #endif
00396 }
00397
00404 static void At91UsartEnable(void)
00405 {
00406 NutEnterCritical();
00407
00408
00409 outr(USARTn_BASE + US_CR_OFF, US_RXEN | US_TXEN);
00410
00411
00412 outr(USARTn_BASE + US_IER_OFF, US_RXRDY | US_TXRDY);
00413 NutIrqEnable(&SIG_UART);
00414
00415 #ifdef UART_HDX_BIT
00416 if (hdx_control) {
00417
00418 sbi(UCSRnB, TXCIE);
00419 }
00420 #endif
00421
00422 NutExitCritical();
00423 }
00424
00428 static void At91UsartDisable(void)
00429 {
00430
00431
00432
00433 NutEnterCritical();
00434 outr(USARTn_BASE + US_IDR_OFF, 0xFFFFFFFF);
00435 NutExitCritical();
00436
00437
00438
00439
00440 NutDelay(10);
00441
00442
00443
00444
00445 outr(USARTn_BASE + US_CR_OFF, US_RXDIS | US_TXDIS);
00446 }
00447
00456 static u_long At91UsartGetSpeed(void)
00457 {
00458 ureg_t cs = inr(USARTn_BASE + US_MR_OFF);
00459 u_long clk;
00460
00461 #if defined(AT91_PLL_MAINCK)
00462 clk = At91GetMasterClock();
00463 #else
00464 clk = NutGetCpuClock();
00465 #endif
00466 if ((cs & US_CLKS) == US_CLKS_MCK8) {
00467 clk /= 8;
00468 }
00469 else if ((cs & US_CLKS) != US_CLKS_MCK) {
00470 clk = 0;
00471 }
00472 return clk / (16UL * (inr(USARTn_BASE + US_BRGR_OFF) & 0xFFFF));
00473 }
00474
00485 static int At91UsartSetSpeed(u_long rate)
00486 {
00487 At91UsartDisable();
00488 #if defined(AT91_PLL_MAINCK)
00489 outr(USARTn_BASE + US_BRGR_OFF, (At91GetMasterClock() / (8 * (rate)) + 1) / 2);
00490 #else
00491 outr(USARTn_BASE + US_BRGR_OFF, (NutGetCpuClock() / (8 * (rate)) + 1) / 2);
00492 #endif
00493 At91UsartEnable();
00494
00495 return 0;
00496 }
00497
00506 static u_char At91UsartGetDataBits(void)
00507 {
00508 ureg_t val = inr(USARTn_BASE + US_MR_OFF);
00509
00510 if ((val & US_PAR) == US_PAR_MULTIDROP) {
00511 val = 9;
00512 }
00513 else {
00514 val &= US_CHRL;
00515 if (val == US_CHRL_5) {
00516 val = 5;
00517 }
00518 else if (val == US_CHRL_6) {
00519 val = 6;
00520 }
00521 else if (val == US_CHRL_7) {
00522 val = 7;
00523 }
00524 else {
00525 val = 8;
00526 }
00527 }
00528 return (u_char)val;
00529 }
00530
00539 static int At91UsartSetDataBits(u_char bits)
00540 {
00541 ureg_t val = inr(USARTn_BASE + US_MR_OFF);
00542
00543 if (bits == 9) {
00544 val &= ~US_PAR;
00545 val |= US_PAR_MULTIDROP;
00546 }
00547 else {
00548 val &= ~US_CHRL;
00549 if (bits == 5) {
00550 val |= US_CHRL_5;
00551 }
00552 else if (bits == 6) {
00553 val |= US_CHRL_6;
00554 }
00555 else if (bits == 7) {
00556 val |= US_CHRL_7;
00557 }
00558 else if (bits == 8) {
00559 val |= US_CHRL_8;
00560 }
00561 }
00562
00563 At91UsartDisable();
00564 outr(USARTn_BASE + US_MR_OFF, val);
00565 At91UsartEnable();
00566
00567
00568
00569
00570 if (At91UsartGetDataBits() != bits) {
00571 return -1;
00572 }
00573 return 0;
00574 }
00575
00584 static u_char At91UsartGetParity(void)
00585 {
00586 ureg_t val = inr(USARTn_BASE + US_MR_OFF) & US_PAR;
00587
00588 if ((val & US_PAR) == US_PAR_MULTIDROP) {
00589 val = 9;
00590 }
00591 else {
00592 if (val == US_PAR_ODD) {
00593 val = 1;
00594 }
00595 else if (val == US_PAR_EVEN) {
00596 val = 2;
00597 }
00598 else {
00599 val = 0;
00600 }
00601 }
00602 return (u_char)val;
00603 }
00604
00615 static int At91UsartSetParity(u_char mode)
00616 {
00617 ureg_t val = inr(USARTn_BASE + US_MR_OFF) & ~US_PAR;
00618
00619 switch (mode) {
00620 case 0:
00621 val |= US_PAR_NO;
00622 break;
00623 case 1:
00624 val |= US_PAR_ODD;
00625 break;
00626 case 2:
00627 val |= US_PAR_EVEN;
00628 break;
00629 }
00630 At91UsartDisable();
00631 outr(USARTn_BASE + US_MR_OFF, val);
00632 At91UsartEnable();
00633
00634
00635
00636
00637 if (At91UsartGetParity() != mode) {
00638 return -1;
00639 }
00640 return 0;
00641 }
00642
00651 static u_char At91UsartGetStopBits(void)
00652 {
00653 ureg_t val = inr(USARTn_BASE + US_MR_OFF) & US_NBSTOP;
00654 if (val == US_NBSTOP_1) {
00655 val = 1;
00656 }
00657 else if (val == US_NBSTOP_2) {
00658 val = 2;
00659 }
00660 else {
00661 val = 3;
00662 }
00663 return (u_char)val;
00664 }
00665
00674 static int At91UsartSetStopBits(u_char bits)
00675 {
00676 ureg_t val = inr(USARTn_BASE + US_MR_OFF) & ~US_NBSTOP;
00677
00678 switch(bits) {
00679 case 1:
00680 val |= US_NBSTOP_1;
00681 break;
00682 case 2:
00683 val |= US_NBSTOP_2;
00684 break;
00685 case 3:
00686 val |= US_NBSTOP_1_5;
00687 break;
00688 }
00689 At91UsartDisable();
00690 outr(USARTn_BASE + US_MR_OFF, val);
00691 At91UsartEnable();
00692
00693
00694
00695
00696 if (At91UsartGetStopBits() != bits) {
00697 return -1;
00698 }
00699 return 0;
00700 }
00701
00707 static u_long At91UsartGetStatus(void)
00708 {
00709 u_long rc = 0;
00710
00711
00712
00713
00714 if ((rx_errors & US_FRAME) != 0) {
00715 rc |= UART_FRAMINGERROR;
00716 }
00717 if ((rx_errors & US_OVRE) != 0) {
00718 rc |= UART_OVERRUNERROR;
00719 }
00720 if ((rx_errors & US_PARE) != 0) {
00721 rc |= UART_PARITYERROR;
00722 }
00723
00724
00725
00726
00727
00728 if (flow_control) {
00729 if (flow_control & XOFF_SENT) {
00730 rc |= UART_RXDISABLED;
00731 }
00732 if (flow_control & XOFF_RCVD) {
00733 rc |= UART_TXDISABLED;
00734 }
00735 }
00736 #ifdef UART_RTS_BIT
00737
00738
00739
00740 if (bit_is_set(UART_RTS_PORT, UART_RTS_BIT)) {
00741 rc |= UART_RTSDISABLED;
00742 if (rts_control) {
00743 rc |= UART_RXDISABLED;
00744 }
00745 } else {
00746 rc |= UART_RTSENABLED;
00747 }
00748 #endif
00749
00750 #ifdef UART_CTS_BIT
00751
00752
00753
00754 if (bit_is_set(UART_CTS_PIN, UART_CTS_BIT)) {
00755 rc |= UART_CTSDISABLED;
00756 if (cts_sense) {
00757 rc |= UART_RXDISABLED;
00758 }
00759 } else {
00760 rc |= UART_CTSENABLED;
00761 }
00762 #endif
00763
00764
00765
00766
00767
00768 if ((rc & UART_RXDISABLED) == 0) {
00769 rc |= UART_RXENABLED;
00770 }
00771 if ((rc & UART_TXDISABLED) == 0) {
00772 rc |= UART_TXENABLED;
00773 }
00774
00775
00776
00777
00778 if (tx_aframe) {
00779 rc |= UART_TXADDRFRAME;
00780 } else {
00781 rc |= UART_TXNORMFRAME;
00782 }
00783 return rc;
00784 }
00785
00793 static int At91UsartSetStatus(u_long flags)
00794 {
00795
00796
00797
00798 if (flow_control) {
00799
00800
00801 NutEnterCritical();
00802
00803
00804
00805
00806
00807 if (flags & UART_RXENABLED) {
00808 flow_control &= ~XOFF_SENT;
00809 } else if (flags & UART_RXDISABLED) {
00810 flow_control |= XOFF_SENT;
00811 }
00812
00813
00814
00815
00816
00817 if (flags & UART_TXENABLED) {
00818 flow_control &= ~XOFF_RCVD;
00819 } else if (flags & UART_TXDISABLED) {
00820 flow_control |= XOFF_RCVD;
00821 }
00822 NutExitCritical();
00823 }
00824 #ifdef UART_RTS_BIT
00825
00826
00827
00828 if (rts_control) {
00829 if (flags & UART_RXDISABLED) {
00830 sbi(UART_RTS_PORT, UART_RTS_BIT);
00831 }
00832 if (flags & UART_RXENABLED) {
00833 cbi(UART_RTS_PORT, UART_RTS_BIT);
00834 }
00835 }
00836 if (flags & UART_RTSDISABLED) {
00837 sbi(UART_RTS_PORT, UART_RTS_BIT);
00838 }
00839 if (flags & UART_RTSENABLED) {
00840 cbi(UART_RTS_PORT, UART_RTS_BIT);
00841 }
00842 #endif
00843
00844
00845
00846
00847 if (flags & UART_TXADDRFRAME) {
00848 tx_aframe = 1;
00849 }
00850 if (flags & UART_TXNORMFRAME) {
00851 tx_aframe = 0;
00852 }
00853
00854
00855
00856
00857 if (flags & UART_ERRORS) {
00858 outr(USARTn_BASE + US_CR_OFF, US_RSTSTA);
00859 }
00860
00861
00862
00863
00864 if ((At91UsartGetStatus() & ~UART_ERRORS) != flags) {
00865 return -1;
00866 }
00867 return 0;
00868 }
00869
00879 static u_char At91UsartGetClockMode(void)
00880 {
00881 u_char rc = 0;
00882
00883 return rc;
00884 }
00885
00897 static int At91UsartSetClockMode(u_char mode)
00898 {
00899
00900
00901
00902 if (At91UsartGetClockMode() != mode) {
00903 return -1;
00904 }
00905 return 0;
00906 }
00907
00916 static u_long At91UsartGetFlowControl(void)
00917 {
00918 u_long rc = 0;
00919
00920 if (flow_control) {
00921 rc |= USART_MF_XONXOFF;
00922 } else {
00923 rc &= ~USART_MF_XONXOFF;
00924 }
00925
00926 #ifdef UART_RTS_BIT
00927 if (rts_control) {
00928 rc |= USART_MF_RTSCONTROL;
00929 } else {
00930 rc &= ~USART_MF_RTSCONTROL;
00931 }
00932 #endif
00933
00934 #ifdef UART_CTS_BIT
00935 if (cts_sense) {
00936 rc |= USART_MF_CTSSENSE;
00937 } else {
00938 rc &= ~USART_MF_CTSSENSE;
00939 }
00940 #endif
00941
00942 #ifdef UART_HDX_BIT
00943 if (hdx_control) {
00944 rc |= USART_MF_HALFDUPLEX;
00945 } else {
00946 rc &= ~USART_MF_HALFDUPLEX;
00947 }
00948 #endif
00949
00950 return rc;
00951 }
00952
00963 static int At91UsartSetFlowControl(u_long flags)
00964 {
00965
00966
00967
00968 if (flags & USART_MF_XONXOFF) {
00969 if(flow_control == 0) {
00970 NutEnterCritical();
00971 flow_control = 1 | XOFF_SENT;
00972 NutExitCritical();
00973 }
00974 } else {
00975 NutEnterCritical();
00976 flow_control = 0;
00977 NutExitCritical();
00978 }
00979
00980 #ifdef UART_RTS_BIT
00981
00982
00983
00984 if (flags & USART_MF_RTSCONTROL) {
00985 sbi(UART_RTS_PORT, UART_RTS_BIT);
00986 sbi(UART_RTS_DDR, UART_RTS_BIT);
00987 rts_control = 1;
00988 } else if (rts_control) {
00989 rts_control = 0;
00990 cbi(UART_RTS_DDR, UART_RTS_BIT);
00991 }
00992 #endif
00993
00994 #ifdef UART_CTS_BIT
00995
00996
00997
00998 if (flags & USART_MF_CTSSENSE) {
00999
01000 if (NutRegisterIrqHandler(&UART_CTS_SIGNAL, At91UsartCts, 0)) {
01001 return -1;
01002 }
01003 sbi(UART_CTS_PORT, UART_CTS_BIT);
01004 cbi(UART_CTS_DDR, UART_CTS_BIT);
01005 cts_sense = 1;
01006 } else if (cts_sense) {
01007 cts_sense = 0;
01008
01009 NutRegisterIrqHandler(&UART_CTS_SIGNAL, 0, 0);
01010 cbi(UART_CTS_DDR, UART_CTS_BIT);
01011 }
01012 #endif
01013
01014 #ifdef UART_HDX_BIT
01015
01016
01017
01018 if (flags & USART_MF_HALFDUPLEX) {
01019
01020 if (NutRegisterIrqHandler(&sig_UART_TRANS, At91UsartTxComplete, &dcb_usart.dcb_rx_rbf)) {
01021 return -1;
01022 }
01023
01024 UART_HDX_RX(UART_HDX_PORT, UART_HDX_BIT);
01025 sbi(UART_HDX_DDR, UART_HDX_BIT);
01026 hdx_control = 1;
01027
01028 sbi(UCSRnB, TXCIE);
01029 } else if (hdx_control) {
01030 hdx_control = 0;
01031
01032 cbi(UCSRnB, TXCIE);
01033
01034 NutRegisterIrqHandler(&sig_UART_TRANS, 0, 0);
01035 cbi(UART_HDX_DDR, UART_HDX_BIT);
01036 }
01037 #endif
01038
01039
01040
01041
01042 if (At91UsartGetFlowControl() != flags) {
01043 return -1;
01044 }
01045 return 0;
01046 }
01047
01055 static void At91UsartTxStart(void)
01056 {
01057 #ifdef UART_HDX_BIT
01058 if (hdx_control) {
01059
01060 UART_HDX_TX(UART_HDX_PORT, UART_HDX_BIT);
01061 }
01062 #endif
01063
01064 outr(USARTn_BASE + US_IER_OFF, US_TXRDY);
01065 }
01066
01075 static void At91UsartRxStart(void)
01076 {
01077
01078
01079
01080 if (flow_control && (flow_control & XOFF_SENT) != 0) {
01081 NutEnterCritical();
01082 if ((inr(USARTn_BASE + US_CSR_OFF) & US_TXRDY)) {
01083 outr(USARTn_BASE + US_THR_OFF, ASCII_XON);
01084 flow_control &= ~XON_PENDING;
01085 } else {
01086 flow_control |= XON_PENDING;
01087 }
01088 flow_control &= ~(XOFF_SENT | XOFF_PENDING);
01089 NutExitCritical();
01090 }
01091 #ifdef UART_RTS_BIT
01092 if (rts_control) {
01093
01094 cbi(UART_RTS_PORT, UART_RTS_BIT);
01095 }
01096 #endif
01097 }
01098
01099
01100
01101
01102
01103
01104
01105
01106
01107 static int At91UsartInit(void)
01108 {
01109
01110
01111
01112 if (NutRegisterIrqHandler(&SIG_UART, At91UsartInterrupt, &dcb_usart)) {
01113 return -1;
01114 }
01115
01116 #if defined (MCU_AT91R40008)
01117
01118 outr(PS_PCER, _BV(US_ID));
01119
01120 outr(PIO_PDR, US_GPIO_PINS);
01121 #elif defined (MCU_AT91SAM7X256)
01122 outr(PMC_PCER, _BV(US_ID));
01123 outr(PIOA_PDR, US_GPIO_PINS);
01124 #endif
01125
01126 outr(USARTn_BASE + US_CR_OFF, US_RSTRX | US_RSTTX | US_RXDIS | US_TXDIS);
01127
01128 outr(USARTn_BASE + US_IDR_OFF, 0xFFFFFFFF);
01129
01130 #if defined (US_RCR_OFF)
01131 outr(USARTn_BASE + US_RCR_OFF, 0);
01132 #endif
01133 #if defined (US_TCR_OFF)
01134 outr(USARTn_BASE + US_TCR_OFF, 0);
01135 #endif
01136
01137 #if defined(AT91_PLL_MAINCK)
01138 outr(USARTn_BASE + US_BRGR_OFF, (At91GetMasterClock() / (8 * (115200)) + 1) / 2);
01139 #else
01140 outr(USARTn_BASE + US_BRGR_OFF, (NutGetCpuClock() / (8 * (115200)) + 1) / 2);
01141 #endif
01142
01143 outr(USARTn_BASE + US_MR_OFF, US_CHMODE_NORMAL | US_CHRL_8 | US_PAR_NO | US_NBSTOP_1);
01144
01145 return 0;
01146 }
01147
01148
01149
01150
01151
01152
01153
01154
01155
01156 static int At91UsartDeinit(void)
01157 {
01158
01159 NutRegisterIrqHandler(&SIG_UART, 0, 0);
01160
01161
01162 outr(USARTn_BASE + US_CR_OFF, US_RSTRX | US_RSTTX | US_RXDIS | US_TXDIS);
01163
01164 outr(USARTn_BASE + US_IDR_OFF, 0xFFFFFFFF);
01165 #if defined (MCU_AT91R40008)
01166
01167 outr(PS_PCDR, _BV(US_ID));
01168
01169 outr(PIO_PER, US_GPIO_PINS);
01170 #elif defined (MCU_AT91SAM7X256)
01171 outr(PMC_PCDR, _BV(US_ID));
01172 outr(PIOA_PER, US_GPIO_PINS);
01173 #endif
01174
01175
01176
01177
01178
01179
01180 #ifdef UART_HDX_BIT
01181
01182 if (hdx_control) {
01183 hdx_control = 0;
01184 NutRegisterIrqHandler(&sig_UART_TRANS, 0, 0);
01185 }
01186 #endif
01187
01188 #ifdef UART_CTS_BIT
01189 if (cts_sense) {
01190 cts_sense = 0;
01191 cbi(UART_CTS_DDR, UART_CTS_BIT);
01192
01193 NutRegisterIrqHandler(&UART_CTS_SIGNAL, 0, 0);
01194 }
01195 #endif
01196
01197 #ifdef UART_RTS_BIT
01198 if (rts_control) {
01199 rts_control = 0;
01200 cbi(UART_RTS_DDR, UART_RTS_BIT);
01201 }
01202 #endif
01203
01204 return 0;
01205 }
01206