ih_at91ssc.c

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00001 /*
00002  * Copyright (C) 2006 by egnite Software GmbH. All rights reserved.
00003  *
00004  * Redistribution and use in source and binary forms, with or without
00005  * modification, are permitted provided that the following conditions
00006  * are met:
00007  *
00008  * 1. Redistributions of source code must retain the above copyright
00009  *    notice, this list of conditions and the following disclaimer.
00010  * 2. Redistributions in binary form must reproduce the above copyright
00011  *    notice, this list of conditions and the following disclaimer in the
00012  *    documentation and/or other materials provided with the distribution.
00013  * 3. Neither the name of the copyright holders nor the names of
00014  *    contributors may be used to endorse or promote products derived
00015  *    from this software without specific prior written permission.
00016  *
00017  * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
00018  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00019  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00020  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
00021  * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
00022  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
00023  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
00024  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
00025  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00026  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
00027  * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
00028  * SUCH DAMAGE.
00029  *
00030  * For additional information see http://www.ethernut.de/
00031  *
00032  */
00033 
00034 /*
00035  * $Log: ih_at91ssc.c,v $
00036  * Revision 1.2  2006/09/29 12:36:02  haraldkipp
00037  * Default interrupt priority changed from 4 to 5. Usually this is used for
00038  * high speed links.
00039  *
00040  * Revision 1.1  2006/09/05 12:33:45  haraldkipp
00041  * SSC interrupt handler added.
00042  *
00043  */
00044 
00045 #include <arch/arm.h>
00046 #include <dev/irqreg.h>
00047 
00048 #ifndef NUT_IRQPRI_SSC
00049 #define NUT_IRQPRI_SSC  5
00050 #endif
00051 
00052 static int SyncSerialIrqCtl(int cmd, void *param);
00053 
00054 IRQ_HANDLER sig_SSC = {
00055 #ifdef NUT_PERFMON
00056     0,                  /* Interrupt counter, ir_count. */
00057 #endif
00058     NULL,               /* Passed argument, ir_arg. */
00059     NULL,               /* Handler subroutine, ir_handler. */
00060     SyncSerialIrqCtl    /* Interrupt control, ir_ctl. */
00061 };
00062 
00066 static void SyncSerialIrqEntry(void) __attribute__ ((naked));
00067 void SyncSerialIrqEntry(void)
00068 {
00069     IRQ_ENTRY();
00070 #ifdef NUT_PERFMON
00071     sig_SSC.ir_count++;
00072 #endif
00073     if (sig_SSC.ir_handler) {
00074         (sig_SSC.ir_handler) (sig_SSC.ir_arg);
00075     }
00076     IRQ_EXIT();
00077 }
00078 
00094 static int SyncSerialIrqCtl(int cmd, void *param)
00095 {
00096     int rc = 0;
00097     u_int *ival = (u_int *)param;
00098     int enabled = inr(AIC_IMR) & _BV(SSC_ID);
00099 
00100     /* Disable interrupt. */
00101     if (enabled) {
00102         outr(AIC_IDCR, _BV(SSC_ID));
00103     }
00104 
00105     switch(cmd) {
00106     case NUT_IRQCTL_INIT:
00107         /* Set the vector. */
00108         outr(AIC_SVR(SSC_ID), (unsigned int)SyncSerialIrqEntry);
00109         /* Initialize to edge triggered with defined priority. */
00110         outr(AIC_SMR(SSC_ID), AIC_SRCTYPE_INT_EDGE_TRIGGERED | NUT_IRQPRI_SSC);
00111         /* Clear interrupt */
00112         outr(AIC_ICCR, _BV(SSC_ID));
00113         break;
00114     case NUT_IRQCTL_STATUS:
00115         if (enabled) {
00116             *ival |= 1;
00117         }
00118         else {
00119             *ival &= ~1;
00120         }
00121         break;
00122     case NUT_IRQCTL_ENABLE:
00123         enabled = 1;
00124         break;
00125     case NUT_IRQCTL_DISABLE:
00126         enabled = 0;
00127         break;
00128     case NUT_IRQCTL_GETPRIO:
00129         *ival = inr(AIC_SMR(SSC_ID)) & AIC_PRIOR;
00130         break;
00131     case NUT_IRQCTL_SETPRIO:
00132         outr(AIC_SMR(SSC_ID), (inr(AIC_SMR(SSC_ID)) & ~AIC_PRIOR) | *ival);
00133         break;
00134 #ifdef NUT_PERFMON
00135     case NUT_IRQCTL_GETCOUNT:
00136         *ival = (u_int)sig_SSC.ir_count;
00137         sig_SSC.ir_count = 0;
00138         break;
00139 #endif
00140     default:
00141         rc = -1;
00142         break;
00143     }
00144 
00145     /* Enable interrupt. */
00146     if (enabled) {
00147         outr(AIC_IECR, _BV(SSC_ID));
00148     }
00149     return rc;
00150 }

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