spimmc_at91.c

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00001 /*
00002  * Copyright (C) 2006 by egnite Software GmbH. All rights reserved.
00003  *
00004  * Redistribution and use in source and binary forms, with or without
00005  * modification, are permitted provided that the following conditions
00006  * are met:
00007  *
00008  * 1. Redistributions of source code must retain the above copyright
00009  *    notice, this list of conditions and the following disclaimer.
00010  * 2. Redistributions in binary form must reproduce the above copyright
00011  *    notice, this list of conditions and the following disclaimer in the
00012  *    documentation and/or other materials provided with the distribution.
00013  * 3. Neither the name of the copyright holders nor the names of
00014  *    contributors may be used to endorse or promote products derived
00015  *    from this software without specific prior written permission.
00016  *
00017  * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
00018  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00019  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00020  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
00021  * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
00022  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
00023  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
00024  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
00025  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00026  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
00027  * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
00028  * SUCH DAMAGE.
00029  *
00030  * For additional information see http://www.ethernut.de/
00031  */
00032 
00054 #include <cfg/arch.h>
00055 #include <cfg/arch/gpio.h>
00056 
00057 #include <dev/mmcard.h>
00058 #include <dev/spimmc_at91.h>
00059 
00060 #if 0
00061 /* Use for local debugging. */
00062 #define NUTDEBUG
00063 #include <stdio.h>
00064 #endif
00065 
00070 
00071 #if defined(MCU_AT91SAM9260)
00072 
00073 #ifndef MMC_CS_BIT
00074 #define MMC_CS_BIT      PA3_SPI0_NPCS0_A
00075 #endif
00076 #define MMC_DATAOUT_BIT PA0_SPI0_MISO_A
00077 #define MMC_DATAIN_BIT  PA1_SPI0_MOSI_A
00078 #define MMC_CLK_BIT     PA2_SPI0_SPCK_A
00079 
00080 #elif defined(MCU_AT91SAM7X256)
00081 
00082 #ifndef MMC_CS_BIT
00083 #define MMC_CS_BIT      SPI0_NPCS1_PA13A
00084 #endif
00085 #define MMC_DATAOUT_BIT SPI0_MISO_PA16A
00086 #define MMC_DATAIN_BIT  SPI0_MOSI_PA17A
00087 #define MMC_CLK_BIT     SPI0_SPCK_PA18A
00088 
00089 #else   /* MCU_AT91SAM7X256 */
00090 #warning "MMC SPI mode not supported on this MCU"
00091 #endif
00092 
00093 #ifndef MMC_PIO_ASR
00094 #define MMC_PIO_ASR     PIOA_ASR
00095 #endif
00096 
00097 #ifndef MMC_PIO_BSR
00098 #define MMC_PIO_BSR     PIOA_BSR
00099 #endif
00100 
00101 #ifndef MMC_PIO_PDR
00102 #define MMC_PIO_PDR     PIOA_PDR
00103 #endif
00104 
00105 #ifndef MMC_PINS_A
00106 #define MMC_PINS_A      (_BV(MMC_DATAOUT_BIT) | _BV(MMC_DATAIN_BIT) | _BV(MMC_CLK_BIT))
00107 #endif
00108 
00109 #ifndef MMC_PINS_B
00110 #define MMC_PINS_B      0
00111 #endif
00112 
00113 #ifndef MMC_CS_PER
00114 #define MMC_CS_PER      PIOA_PER
00115 #endif
00116 
00117 #ifndef MMC_CS_OER
00118 #define MMC_CS_OER      PIOA_OER
00119 #endif
00120 
00121 #ifndef MMC_CS_SODR
00122 #define MMC_CS_SODR     PIOA_SODR
00123 #endif
00124 
00125 #ifndef MMC_CS_CODR
00126 #define MMC_CS_CODR     PIOA_CODR
00127 #endif
00128 
00129 #ifndef MMC_SPI_CR
00130 #define MMC_SPI_CR      SPI0_CR
00131 #endif
00132 
00133 #ifndef MMC_SPI_MR
00134 #define MMC_SPI_MR      SPI0_MR
00135 #endif
00136 
00137 #ifndef MMC_SPI_RDR
00138 #define MMC_SPI_RDR     SPI0_RDR
00139 #endif
00140 
00141 #ifndef MMC_SPI_TDR
00142 #define MMC_SPI_TDR     SPI0_TDR
00143 #endif
00144 
00145 #ifndef MMC_SPI_SR
00146 #define MMC_SPI_SR      SPI0_SR
00147 #endif
00148 
00149 #ifndef MMC_SPI_CSR1
00150 #define MMC_SPI_CSR1    SPI0_CSR1
00151 #endif
00152 
00153 #ifndef MMC_SPI_ID
00154 #define MMC_SPI_ID      SPI0_ID
00155 #endif
00156 
00157 
00166 static int At91SpiMmCard0Init(void)
00167 {
00168     return 0;
00169 }
00170 
00179 static int At91SpiMmCard0Select(int on)
00180 {
00181     int rc = (inr(PIOA_ODSR) & _BV(MMC_CS_BIT)) == 0;
00182 
00183     /* MMC select is low active. */
00184     if (on == 1) {
00185         outr(MMC_CS_CODR, _BV(MMC_CS_BIT));
00186     } else if (on == 0) {
00187         outr(MMC_CS_SODR, _BV(MMC_CS_BIT));
00188     }
00189     return rc;
00190 }
00191 
00199 static u_char At91SpiMmCard0Io(u_char val)
00200 {
00201 #ifdef NUTDEBUG
00202     putchar('[');
00203     if (val != 0xFF) {
00204         printf("s%02X", val);
00205     }
00206 #endif
00207 
00208     /* Transmission is started by writing the transmit data. */
00209     outr(MMC_SPI_TDR, val);
00210     /* Wait for receiver data register full. */
00211     while((inr(MMC_SPI_SR) & SPI_RDRF) == 0);
00212     /* Read data. */
00213     val = (u_char)inr(MMC_SPI_RDR);
00214 
00215 #ifdef NUTDEBUG
00216     if (val != 0xFF) {
00217         printf("r%02X", val);
00218     }
00219     putchar(']');
00220 #endif
00221     return val;
00222 }
00223 
00234 int At91SpiMmCard0Avail(void)
00235 {
00236     return 1;
00237 }
00238 
00246 int At91SpiMmCard0WrProt(void)
00247 {
00248     return 0;
00249 }
00250 
00259 static int At91SpiMmcIfcInit(NUTDEVICE * dev)
00260 {
00261     /* Disable PIO lines used for SPI. */
00262     outr(MMC_PIO_PDR, MMC_PINS_A | MMC_PINS_B);
00263     /* Enable peripherals. */
00264     outr(MMC_PIO_ASR, MMC_PINS_A);
00265     outr(MMC_PIO_BSR, MMC_PINS_B);
00266 
00267     /* MMC chip select is manually controlled. */
00268     outr(MMC_CS_PER, _BV(MMC_CS_BIT));
00269     outr(MMC_CS_SODR, _BV(MMC_CS_BIT));
00270     outr(MMC_CS_OER, _BV(MMC_CS_BIT));
00271 
00272     /* Enable SPI clock. */
00273     outr(PMC_PCER, _BV(MMC_SPI_ID));
00274 
00275     /* SPI enable and reset. */
00276     outr(MMC_SPI_CR, SPI_SPIEN | SPI_SWRST);
00277     outr(MMC_SPI_CR, SPI_SPIEN);
00278 
00279     /* Set SPI to master mode, fixed peripheral at CS1, fault detection disabled. */
00280     outr(MMC_SPI_MR, (1 << SPI_PCS_LSB) | SPI_MODFDIS | SPI_MSTR);
00281 
00282     /* Data changes during clock low and will be sampled on rising edges. */
00283     outr(MMC_SPI_CSR1, (3 << SPI_SCBR_LSB) | SPI_CPOL);
00284 
00285     return MmCardDevInit(dev);
00286 }
00287 
00288 static MMCIFC mmc0_ifc = {
00289     At91SpiMmCard0Init,             
00290     At91SpiMmCard0Io,               
00291     At91SpiMmCard0Select,           
00292     At91SpiMmCard0Avail,            
00293     At91SpiMmCard0WrProt            
00294 };
00295 
00308 NUTDEVICE devAt91SpiMmc0 = {
00309     0,                          
00310     {'M', 'M', 'C', '0', 0, 0, 0, 0, 0}
00311     ,                           
00312     0,                          
00313     0,                          
00314     0,                          
00315     &mmc0_ifc,                  
00316     0,                          
00317     At91SpiMmcIfcInit,          
00318     MmCardIOCtl,                
00319     MmCardBlockRead,            
00320     MmCardBlockWrite,           
00321 #ifdef __HARVARD_ARCH__
00322     MmCardBlockWrite_P,         
00323 #endif
00324     MmCardMount,                
00325     MmCardUnmount,              
00326     0                           
00327 };
00328 

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