at91_sdramc.h

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00001 #ifndef _ARCH_ARM_AT91_SDRAMC_H_
00002 #define _ARCH_ARM_AT91_SDRAMC_H_
00003 
00004 /*
00005  * Copyright (C) 2006 by egnite Software GmbH. All rights reserved.
00006  *
00007  * Redistribution and use in source and binary forms, with or without
00008  * modification, are permitted provided that the following conditions
00009  * are met:
00010  *
00011  * 1. Redistributions of source code must retain the above copyright
00012  *    notice, this list of conditions and the following disclaimer.
00013  * 2. Redistributions in binary form must reproduce the above copyright
00014  *    notice, this list of conditions and the following disclaimer in the
00015  *    documentation and/or other materials provided with the distribution.
00016  * 3. Neither the name of the copyright holders nor the names of
00017  *    contributors may be used to endorse or promote products derived
00018  *    from this software without specific prior written permission.
00019  *
00020  * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
00021  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00022  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00023  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
00024  * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
00025  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
00026  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
00027  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
00028  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00029  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
00030  * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
00031  * SUCH DAMAGE.
00032  *
00033  * For additional information see http://www.ethernut.de/
00034  */
00035 
00054 
00057 #define SDRAMC_MR_OFF                   0x00000000      
00058 #define SDRAMC_MR   (SDRAMC_BASE + SDRAMC_MR_OFF)       
00059 #define SDRAMC_MODE                     0x00000007      
00060 #define SDRAMC_MODE_NORMAL              0x00000000      
00061 #define SDRAMC_MODE_NOP                 0x00000001      
00062 #define SDRAMC_MODE_PRCGALL             0x00000002      
00063 #define SDRAMC_MODE_LMR                 0x00000003      
00064 #define SDRAMC_MODE_RFSH                0x00000004      
00065 #define SDRAMC_MODE_EXT_LMR             0x00000005      
00066 #define SDRAMC_MODE_DEEP                0x00000006      
00068 
00069 
00071 #define SDRAMC_TR_OFF                   0x00000004      
00072 #define SDRAMC_TR   (SDRAMC_BASE + SDRAMC_TR_OFF)       
00073 #define SDRAMC_COUNT                    0x00000FFF      
00075 
00076 
00078 #define SDRAMC_CR_OFF                   0x00000008      
00079 #define SDRAMC_CR   (SDRAMC_BASE + SDRAMC_CR_OFF)       
00080 #define SDRAMC_NC                       0x00000003      
00081 #define SDRAMC_NC_8                     0x00000000      
00082 #define SDRAMC_NC_9                     0x00000001      
00083 #define SDRAMC_NC_10                    0x00000002      
00084 #define SDRAMC_NC_11                    0x00000003      
00085 #define SDRAMC_NR                       0x0000000C      
00086 #define SDRAMC_NR_11                    0x00000000      
00087 #define SDRAMC_NR_12                    0x00000004      
00088 #define SDRAMC_NR_13                    0x00000008      
00089 #define SDRAMC_NB                       0x00000010      
00090 #define SDRAMC_CAS                      0x00000060      
00091 #define SDRAMC_CAS_1                    0x00000020      
00092 #define SDRAMC_CAS_2                    0x00000040      
00093 #define SDRAMC_CAS_3                    0x00000060      
00094 #define SDRAMC_DBW                      0x00000080      
00095 #define SDRAMC_TWR                      0x00000F00      
00096 #define SDRAMC_TWR_LSB                          8       
00097 #define SDRAMC_TRC                      0x0000F000      
00098 #define SDRAMC_TRC_LSB                          12      
00099 #define SDRAMC_TRP                      0x000F0000      
00100 #define SDRAMC_TRP_LSB                          16      
00101 #define SDRAMC_TRCD                     0x00F00000      
00102 #define SDRAMC_TRCD_LSB                         20      
00103 #define SDRAMC_TRAS                     0x0F000000      
00104 #define SDRAMC_TRAS_LSB                         24      
00105 #define SDRAMC_TXSR                     0xF0000000      
00106 #define SDRAMC_TXSR_LSB                         28      
00108 
00109 
00111 #define SDRAMC_LPR_OFF                  0x00000010      
00112 #define SDRAMC_LPR  (SDRAMC_BASE + SDRAMC_LPR_OFF)      
00113 #define SDRAMC_LPCB                     0x00000003      
00114 #define SDRAMC_LPCB_DISABLE             0x00000000      
00115 #define SDRAMC_LPCB_SELF_REFRESH        0x00000001      
00116 #define SDRAMC_LPCB_POWER_DOWN          0x00000002      
00117 #define SDRAMC_LPCB_DEEP_POWER_DOWN     0x00000003      
00118 #define SDRAMC_PASR                     0x00000070      
00119 #define SDRAMC_PASR_LSB                         4       
00120 #define SDRAMC_TCSR                     0x00000300      
00121 #define SDRAMC_TCSR_LSB                         8       
00122 #define SDRAMC_DS                       0x00000C00      
00123 #define SDRAMC_DS_LSB                           10      
00124 #define SDRAMC_TIMEOUT                  0x00003000      
00125 #define SDRAMC_TIMEOUT_0                0x00000000      
00126 #define SDRAMC_TIMEOUT_64               0x00001000      
00127 #define SDRAMC_TIMEOUT_128              0x00002000      
00129 
00130 
00132 #define SDRAMC_IER_OFF                  0x00000014      
00133 #define SDRAMC_IER  (SDRAMC_BASE + SDRAMC_IER_OFF)      
00134 #define SDRAMC_IDR_OFF                  0x00000018      
00135 #define SDRAMC_IDR  (SDRAMC_BASE + SDRAMC_IDR_OFF)      
00136 #define SDRAMC_IMR_OFF                  0x0000001C      
00137 #define SDRAMC_IMR  (SDRAMC_BASE + SDRAMC_IMR_OFF)      
00138 #define SDRAMC_ISR_OFF                  0x00000020      
00139 #define SDRAMC_ISR  (SDRAMC_BASE + SDRAMC_ISR_OFF)      
00140 #define SDRAMC_RES                      0x00000001      
00142 
00143 
00145 #define SDRAMC_MDR_OFF                  0x00000024      
00146 #define SDRAMC_MDR  (SDRAMC_BASE + SDRAMC_MDR_OFF)      
00147 #define SDRAMC_MD                       0x00000003      
00148 #define SDRAMC_MD                       0x00000003      
00149 #define SDRAMC_MD_SDRAM                 0x00000000      
00150 #define SDRAMC_MD_LPSDRAM               0x00000001      
00152 
00153 
00155 #endif                          /* _ARCH_ARM_AT91_SDRAMC_H_ */

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