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00049 #include <arch/arm.h>
00050 #include <dev/irqreg.h>
00051
00052 #ifndef NUT_IRQPRI_FIQ
00053 #define NUT_IRQPRI_FIQ 4
00054 #endif
00055
00056 static int FastIrqCtl(int cmd, void *param);
00057
00058 IRQ_HANDLER sig_FIQ = {
00059 #ifdef NUT_PERFMON
00060 0,
00061 #endif
00062 NULL,
00063 NULL,
00064 FastIrqCtl
00065 };
00066
00072 static void FastIrqEntry(void) __attribute__ ((naked));
00073 void FastIrqEntry(void)
00074 {
00075 FIQ_ENTRY();
00076 #ifdef NUT_PERFMON
00077 sig_FIQ.ir_count++;
00078 #endif
00079 if (sig_FIQ.ir_handler) {
00080 (sig_FIQ.ir_handler) (sig_FIQ.ir_arg);
00081 }
00082 FIQ_EXIT();
00083 }
00084
00100 static int FastIrqCtl(int cmd, void *param)
00101 {
00102 int rc = 0;
00103 u_int *ival = (u_int *)param;
00104 int enabled = inr(AIC_IMR) & _BV(FIQ_ID);
00105
00106
00107 if (enabled) {
00108 outr(AIC_IDCR, _BV(FIQ_ID));
00109 }
00110
00111 switch(cmd) {
00112 case NUT_IRQCTL_INIT:
00113
00114 outr(AIC_SVR(FIQ_ID), (unsigned int)FastIrqEntry);
00115
00116 outr(AIC_SMR(FIQ_ID), AIC_SRCTYPE_EXT_NEGATIVE_EDGE | NUT_IRQPRI_FIQ);
00117
00118 outr(AIC_ICCR, _BV(FIQ_ID));
00119 break;
00120 case NUT_IRQCTL_STATUS:
00121 if (enabled) {
00122 *ival |= 1;
00123 }
00124 else {
00125 *ival &= ~1;
00126 }
00127 break;
00128 case NUT_IRQCTL_ENABLE:
00129 enabled = 1;
00130 break;
00131 case NUT_IRQCTL_DISABLE:
00132 enabled = 0;
00133 break;
00134 case NUT_IRQCTL_GETMODE:
00135 {
00136 u_int val = inr(AIC_SMR(FIQ_ID)) & AIC_SRCTYPE;
00137 if (val == AIC_SRCTYPE_EXT_LOW_LEVEL) {
00138 *ival = NUT_IRQMODE_LOWLEVEL;
00139 } else if (val == AIC_SRCTYPE_EXT_HIGH_LEVEL) {
00140 *ival = NUT_IRQMODE_HIGHLEVEL;
00141 } else if (val == AIC_SRCTYPE_EXT_POSITIVE_EDGE) {
00142 *ival = NUT_IRQMODE_RISINGEDGE;
00143 } else {
00144 *ival = NUT_IRQMODE_FALLINGEDGE;
00145 }
00146 }
00147 break;
00148 case NUT_IRQCTL_SETMODE:
00149 if (*ival == NUT_IRQMODE_LOWLEVEL) {
00150 outr(AIC_SMR(FIQ_ID), (inr(AIC_SMR(FIQ_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_EXT_LOW_LEVEL);
00151 } else if (*ival == NUT_IRQMODE_HIGHLEVEL) {
00152 outr(AIC_SMR(FIQ_ID), (inr(AIC_SMR(FIQ_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_EXT_HIGH_LEVEL);
00153 } else if (*ival == NUT_IRQMODE_FALLINGEDGE) {
00154 outr(AIC_SMR(FIQ_ID), (inr(AIC_SMR(FIQ_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_EXT_NEGATIVE_EDGE);
00155 } else if (*ival == NUT_IRQMODE_RISINGEDGE) {
00156 outr(AIC_SMR(FIQ_ID), (inr(AIC_SMR(FIQ_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_EXT_POSITIVE_EDGE);
00157 } else {
00158 rc = -1;
00159 }
00160 break;
00161 #ifdef NUT_PERFMON
00162 case NUT_IRQCTL_GETCOUNT:
00163 *ival = (u_int)sig_FIQ.ir_count;
00164 sig_FIQ.ir_count = 0;
00165 break;
00166 #endif
00167 default:
00168 rc = -1;
00169 break;
00170 }
00171
00172
00173 if (enabled) {
00174 outr(AIC_IECR, _BV(FIQ_ID));
00175 }
00176 return rc;
00177 }