ih_at91adc.c

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00001 /*
00002  * Copyright (C) 2001-2005 by EmbeddedIT, 
00003  * Ole Reinhardt <ole.reinhardt@embedded-it.de> All rights reserved.
00004  *
00005  * Redistribution and use in source and binary forms, with or without
00006  * modification, are permitted provided that the following conditions
00007  * are met:
00008  *
00009  * 1. Redistributions of source code must retain the above copyright
00010  *    notice, this list of conditions and the following disclaimer.
00011  * 2. Redistributions in binary form must reproduce the above copyright
00012  *    notice, this list of conditions and the following disclaimer in the
00013  *    documentation and/or other materials provided with the distribution.
00014  * 3. Neither the name of the copyright holders nor the names of
00015  *    contributors may be used to endorse or promote products derived
00016  *    from this software without specific prior written permission.
00017  *
00018  * THIS SOFTWARE IS PROVIDED BY EMBEDDED IT AND CONTRIBUTORS
00019  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00020  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00021  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EMBEDDED IT
00022  * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
00023  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 
00024  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 
00025  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
00026  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 
00027  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 
00028  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00029  *
00030  * For additional information see http://www.ethernut.de/
00031  *
00032  */
00033 
00034 /*
00035  * $Log: ih_at91adc.c,v $
00036  * Revision 1.2  2008/07/26 09:43:01  haraldkipp
00037  * Added support for retrieving and setting the interrupt mode.
00038  *
00039  * Revision 1.1  2007/12/09 21:36:05  olereinhardt
00040  * Initial checkin of adc irq handler
00041  *
00042  */
00043 
00044 #include <arch/arm.h>
00045 #include <dev/irqreg.h>
00046 
00047 #if defined(ADC_ID)
00048 
00049 #ifndef NUT_IRQPRI_ADC
00050 #define NUT_IRQPRI_ADC  4
00051 #endif
00052 
00053 static int AdcIrqCtl(int cmd, void *param);
00054 
00055 IRQ_HANDLER sig_ADC = {
00056 #ifdef NUT_PERFMON
00057     0,                  /* Interrupt counter, ir_count. */
00058 #endif
00059     NULL,               /* Passed argument, ir_arg. */
00060     NULL,               /* Handler subroutine, ir_handler. */
00061     AdcIrqCtl           /* Interrupt control, ir_ctl. */
00062 };
00063 
00067 static void AdcIrqEntry(void) __attribute__ ((naked));
00068 void AdcIrqEntry(void)
00069 {
00070     IRQ_ENTRY();
00071 #ifdef NUT_PERFMON
00072     sig_ADC.ir_count++;
00073 #endif
00074     if (sig_ADC.ir_handler) {
00075         (sig_ADC.ir_handler) (sig_ADC.ir_arg);
00076     }
00077     IRQ_EXIT();
00078 }
00079 
00097 static int AdcIrqCtl(int cmd, void *param)
00098 {
00099     int rc = 0;
00100     u_int *ival = (u_int *)param;
00101     int enabled = inr(AIC_IMR) & _BV(ADC_ID);
00102 
00103     /* Disable interrupt. */
00104     if (enabled) {
00105         outr(AIC_IDCR, _BV(ADC_ID));
00106     }
00107 
00108     switch(cmd) {
00109     case NUT_IRQCTL_INIT:
00110         /* Set the vector. */
00111         outr(AIC_SVR(ADC_ID), (unsigned int)AdcIrqEntry);
00112         /* Initialize to edge triggered with defined priority. */
00113         outr(AIC_SMR(ADC_ID), AIC_SRCTYPE_INT_EDGE_TRIGGERED | NUT_IRQPRI_ADC);
00114         /* Clear interrupt */
00115         outr(AIC_ICCR, _BV(ADC_ID));
00116         break;
00117     case NUT_IRQCTL_STATUS:
00118         if (enabled) {
00119             *ival |= 1;
00120         }
00121         else {
00122             *ival &= ~1;
00123         }
00124         break;
00125     case NUT_IRQCTL_ENABLE:
00126         enabled = 1;
00127         break;
00128     case NUT_IRQCTL_DISABLE:
00129         enabled = 0;
00130         break;
00131     case NUT_IRQCTL_GETMODE:
00132         {
00133             u_int val = inr(AIC_SMR(ADC_ID)) & AIC_SRCTYPE;
00134             if (val == AIC_SRCTYPE_INT_LEVEL_SENSITIVE || val == AIC_SRCTYPE_EXT_HIGH_LEVEL) {
00135                 *ival = NUT_IRQMODE_LEVEL;
00136             } else  {
00137                 *ival = NUT_IRQMODE_EDGE;
00138             }
00139         }
00140         break;
00141     case NUT_IRQCTL_SETMODE:
00142         if (*ival == NUT_IRQMODE_LEVEL) {
00143             outr(AIC_SMR(ADC_ID), (inr(AIC_SMR(ADC_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_INT_LEVEL_SENSITIVE);
00144         } else if (*ival == NUT_IRQMODE_EDGE) {
00145             outr(AIC_SMR(ADC_ID), (inr(AIC_SMR(ADC_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_INT_EDGE_TRIGGERED);
00146         } else  {
00147             rc = -1;
00148         }
00149         break;
00150     case NUT_IRQCTL_GETPRIO:
00151         *ival = inr(AIC_SMR(ADC_ID)) & AIC_PRIOR;
00152         break;
00153     case NUT_IRQCTL_SETPRIO:
00154         outr(AIC_SMR(ADC_ID), (inr(AIC_SMR(ADC_ID)) & ~AIC_PRIOR) | *ival);
00155         break;
00156 #ifdef NUT_PERFMON
00157     case NUT_IRQCTL_GETCOUNT:
00158         *ival = (u_int)sig_ADC.ir_count;
00159         sig_ADC.ir_count = 0;
00160         break;
00161 #endif
00162     default:
00163         rc = -1;
00164         break;
00165     }
00166 
00167     /* Enable interrupt. */
00168     if (enabled) {
00169         outr(AIC_IECR, _BV(ADC_ID));
00170     }
00171     return rc;
00172 }
00173 
00174 #endif /* ADC_ID */

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