ih_at91spi0.c

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00001 /*
00002  * Copyright (C) 2006 by egnite Software GmbH. All rights reserved.
00003  *
00004  * Redistribution and use in source and binary forms, with or without
00005  * modification, are permitted provided that the following conditions
00006  * are met:
00007  *
00008  * 1. Redistributions of source code must retain the above copyright
00009  *    notice, this list of conditions and the following disclaimer.
00010  * 2. Redistributions in binary form must reproduce the above copyright
00011  *    notice, this list of conditions and the following disclaimer in the
00012  *    documentation and/or other materials provided with the distribution.
00013  * 3. Neither the name of the copyright holders nor the names of
00014  *    contributors may be used to endorse or promote products derived
00015  *    from this software without specific prior written permission.
00016  *
00017  * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
00018  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00019  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00020  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
00021  * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
00022  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
00023  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
00024  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
00025  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00026  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
00027  * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
00028  * SUCH DAMAGE.
00029  *
00030  * For additional information see http://www.ethernut.de/
00031  *
00032  */
00033 
00034 /*
00035  * $Log: ih_at91spi0.c,v $
00036  * Revision 1.2  2008/07/26 09:43:01  haraldkipp
00037  * Added support for retrieving and setting the interrupt mode.
00038  *
00039  * Revision 1.1  2006/09/29 12:34:59  haraldkipp
00040  * Basic AT91 SPI support added.
00041  *
00042  */
00043 
00044 #include <arch/arm.h>
00045 #include <dev/irqreg.h>
00046 
00047 #ifndef NUT_IRQPRI_SPI0
00048 #define NUT_IRQPRI_SPI0  4
00049 #endif
00050 
00051 static int SerialPeripheral0IrqCtl(int cmd, void *param);
00052 
00053 IRQ_HANDLER sig_SPI0 = {
00054 #ifdef NUT_PERFMON
00055     0,                          /* Interrupt counter, ir_count. */
00056 #endif
00057     NULL,                       /* Passed argument, ir_arg. */
00058     NULL,                       /* Handler subroutine, ir_handler. */
00059     SerialPeripheral0IrqCtl     /* Interrupt control, ir_ctl. */
00060 };
00061 
00065 static void SerialPeripheral0IrqEntry(void) __attribute__ ((naked));
00066 void SerialPeripheral0IrqEntry(void)
00067 {
00068     IRQ_ENTRY();
00069 #ifdef NUT_PERFMON
00070     sig_SPI0.ir_count++;
00071 #endif
00072     if (sig_SPI0.ir_handler) {
00073         (sig_SPI0.ir_handler) (sig_SPI0.ir_arg);
00074     }
00075     IRQ_EXIT();
00076 }
00077 
00095 static int SerialPeripheral0IrqCtl(int cmd, void *param)
00096 {
00097     int rc = 0;
00098     u_int *ival = (u_int *) param;
00099     int enabled = inr(AIC_IMR) & _BV(SPI0_ID);
00100 
00101     /* Disable interrupt. */
00102     if (enabled) {
00103         outr(AIC_IDCR, _BV(SPI0_ID));
00104     }
00105 
00106     switch (cmd) {
00107     case NUT_IRQCTL_INIT:
00108         /* Set the vector. */
00109         outr(AIC_SVR(SPI0_ID), (unsigned int) SerialPeripheral0IrqEntry);
00110         /* Initialize to edge triggered with defined priority. */
00111         outr(AIC_SMR(SPI0_ID), AIC_SRCTYPE_INT_EDGE_TRIGGERED | NUT_IRQPRI_SPI0);
00112         /* Clear interrupt */
00113         outr(AIC_ICCR, _BV(SPI0_ID));
00114         break;
00115     case NUT_IRQCTL_STATUS:
00116         if (enabled) {
00117             *ival |= 1;
00118         } else {
00119             *ival &= ~1;
00120         }
00121         break;
00122     case NUT_IRQCTL_ENABLE:
00123         enabled = 1;
00124         break;
00125     case NUT_IRQCTL_DISABLE:
00126         enabled = 0;
00127         break;
00128     case NUT_IRQCTL_GETMODE:
00129         {
00130             u_int val = inr(AIC_SMR(SPI0_ID)) & AIC_SRCTYPE;
00131             if (val == AIC_SRCTYPE_INT_LEVEL_SENSITIVE || val == AIC_SRCTYPE_EXT_HIGH_LEVEL) {
00132                 *ival = NUT_IRQMODE_LEVEL;
00133             } else  {
00134                 *ival = NUT_IRQMODE_EDGE;
00135             }
00136         }
00137         break;
00138     case NUT_IRQCTL_SETMODE:
00139         if (*ival == NUT_IRQMODE_LEVEL) {
00140             outr(AIC_SMR(SPI0_ID), (inr(AIC_SMR(SPI0_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_INT_LEVEL_SENSITIVE);
00141         } else if (*ival == NUT_IRQMODE_EDGE) {
00142             outr(AIC_SMR(SPI0_ID), (inr(AIC_SMR(SPI0_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_INT_EDGE_TRIGGERED);
00143         } else  {
00144             rc = -1;
00145         }
00146         break;
00147     case NUT_IRQCTL_GETPRIO:
00148         *ival = inr(AIC_SMR(SPI0_ID)) & AIC_PRIOR;
00149         break;
00150     case NUT_IRQCTL_SETPRIO:
00151         outr(AIC_SMR(SPI0_ID), (inr(AIC_SMR(SPI0_ID)) & ~AIC_PRIOR) | *ival);
00152         break;
00153 #ifdef NUT_PERFMON
00154     case NUT_IRQCTL_GETCOUNT:
00155         *ival = (u_int) sig_SPI0.ir_count;
00156         sig_SPI0.ir_count = 0;
00157         break;
00158 #endif
00159     default:
00160         rc = -1;
00161         break;
00162     }
00163 
00164     /* Enable interrupt. */
00165     if (enabled) {
00166         outr(AIC_IECR, _BV(SPI0_ID));
00167     }
00168     return rc;
00169 }

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