at91_us.h

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00001 #ifndef _ARCH_ARM_AT91_US_H_
00002 #define _ARCH_ARM_AT91_US_H_
00003 
00004 /*
00005  * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
00006  *
00007  * Redistribution and use in source and binary forms, with or without
00008  * modification, are permitted provided that the following conditions
00009  * are met:
00010  *
00011  * 1. Redistributions of source code must retain the above copyright
00012  *    notice, this list of conditions and the following disclaimer.
00013  * 2. Redistributions in binary form must reproduce the above copyright
00014  *    notice, this list of conditions and the following disclaimer in the
00015  *    documentation and/or other materials provided with the distribution.
00016  * 3. Neither the name of the copyright holders nor the names of
00017  *    contributors may be used to endorse or promote products derived
00018  *    from this software without specific prior written permission.
00019  *
00020  * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
00021  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00022  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00023  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
00024  * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
00025  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
00026  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
00027  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
00028  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00029  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
00030  * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
00031  * SUCH DAMAGE.
00032  *
00033  * For additional information see http://www.ethernut.de/
00034  */
00035 
00063 
00066 #define US_CR_OFF               0x00000000      
00067 #define US0_CR  (USART0_BASE + US_CR_OFF)       
00068 #define US1_CR  (USART1_BASE + US_CR_OFF)       
00069 #define US_RSTRX                0x00000004      
00070 #define US_RSTTX                0x00000008      
00071 #define US_RXEN                 0x00000010      
00072 #define US_RXDIS                0x00000020      
00073 #define US_TXEN                 0x00000040      
00074 #define US_TXDIS                0x00000080      
00075 #define US_RSTSTA               0x00000100      
00076 #define US_STTBRK               0x00000200      
00077 #define US_STPBRK               0x00000400      
00078 #define US_STTTO                0x00000800      
00079 #define US_SENDA                0x00001000      
00081 
00082 
00084 #define US_MR_OFF               0x00000004      
00085 #define US0_MR  (USART0_BASE + US_MR_OFF)       
00086 #define US1_MR  (USART1_BASE + US_MR_OFF)       
00088 #define US_CLKS                 0x00000030      
00089 #define US_CLKS_MCK             0x00000000      
00090 #define US_CLKS_MCK8            0x00000010      
00091 #define US_CLKS_SCK             0x00000020      
00092 #define US_CLKS_SLCK            0x00000030      
00094 #define US_CHRL                 0x000000C0      
00095 #define US_CHRL_5               0x00000000      
00096 #define US_CHRL_6               0x00000040      
00097 #define US_CHRL_7               0x00000080      
00098 #define US_CHRL_8               0x000000C0      
00100 #define US_SYNC                 0x00000100      
00102 #define US_PAR                  0x00000E00      
00103 #define US_PAR_EVEN             0x00000000      
00104 #define US_PAR_ODD              0x00000200      
00105 #define US_PAR_SPACE            0x00000400      
00106 #define US_PAR_MARK             0x00000600      
00107 #define US_PAR_NO               0x00000800      
00108 #define US_PAR_MULTIDROP        0x00000C00      
00110 #define US_NBSTOP               0x00003000      
00111 #define US_NBSTOP_1             0x00000000      
00112 #define US_NBSTOP_1_5           0x00001000      
00113 #define US_NBSTOP_2             0x00002000      
00115 #define US_CHMODE                   0x0000C000  
00116 #define US_CHMODE_NORMAL            0x00000000  
00117 #define US_CHMODE_AUTOMATIC_ECHO    0x00004000  
00118 #define US_CHMODE_LOCAL_LOOPBACK    0x00008000  
00119 #define US_CHMODE_REMOTE_LOOPBACK   0x0000C000  
00121 #define US_MODE_RS485           0x00000001      
00122 #define US_MODE_HWHANDSHAKE     0x00000002      
00123 #define US_MODE_MODEM           0x00000003      
00124 #define US_MODE9                0x00020000      
00126 #define US_CLKO                 0x00040000      
00128 
00129 
00131 #define US_CSR_OFF              0x00000014      
00132 #define US0_CSR (USART0_BASE + US_CSR_OFF)      
00133 #define US1_CSR (USART1_BASE + US_CSR_OFF)      
00135 #define US_IER_OFF              0x00000008      
00136 #define US0_IER (USART0_BASE + US_IER_OFF)      
00137 #define US1_IER (USART1_BASE + US_IER_OFF)      
00139 #define US_IDR_OFF              0x0000000C      
00140 #define US0_IDR (USART0_BASE + US_IDR_OFF)      
00141 #define US1_IDR (USART1_BASE + US_IDR_OFF)      
00143 #define US_IMR_OFF              0x00000010      
00144 #define US0_IMR (USART0_BASE + US_IMR_OFF)      
00145 #define US1_IMR (USART1_BASE + US_IMR_OFF)      
00147 #define US_RXRDY                0x00000001      
00148 #define US_TXRDY                0x00000002      
00149 #define US_RXBRK                0x00000004      
00150 #define US_ENDRX                0x00000008      
00151 #define US_ENDTX                0x00000010      
00152 #define US_OVRE                 0x00000020      
00153 #define US_FRAME                0x00000040      
00154 #define US_PARE                 0x00000080      
00155 #define US_TIMEOUT              0x00000100      
00156 #define US_TXEMPTY              0x00000200      
00157 #define US_RXBUFF               0x00001000      
00163 #define AT91_US_BAUD(baud) ((NUT_CPU_FREQ / (8 * (baud)) + 1) / 2)
00164 
00168 #define US_RHR_OFF              0x00000018      
00169 #define US0_RHR (USART0_BASE + US_RHR_OFF)      
00170 #define US1_RHR (USART1_BASE + US_RHR_OFF)      
00172 
00173 
00175 #define US_THR_OFF              0x0000001C      
00176 #define US0_THR (USART0_BASE + US_THR_OFF)      
00177 #define US1_THR (USART1_BASE + US_THR_OFF)      
00179 
00180 
00182 #define US_BRGR_OFF             0x00000020      
00183 #define US0_BRGR (USART0_BASE + US_BRGR_OFF)    
00184 #define US1_BRGR (USART1_BASE + US_BRGR_OFF)    
00186 
00187 
00189 #define US_RTOR_OFF             0x00000024      
00190 #define US0_RTOR (USART0_BASE + US_RTOR_OFF)    
00191 #define US1_RTOR (USART1_BASE + US_RTOR_OFF)    
00193 
00194 
00196 #define US_TTGR_OFF             0x00000028      
00197 #define US0_TTGR (USART0_BASE + US_TTGR_OFF)    
00198 #define US1_TTGR (USART1_BASE + US_TTGR_OFF)    
00200 
00201 
00203 #define US_FIDI_OFF             0x00000040      
00204 #define US0_FIDI (USART0_BASE + US_FIDI_OFF)    
00205 #define US1_FIDI (USART1_BASE + US_FIDI_OFF)    
00207 
00208 
00210 #define US_NER_OFF              0x00000044      
00211 #define US0_NER  (USART0_BASE + US_NER_OFF)     
00212 #define US1_NER  (USART1_BASE + US_NER_OFF)     
00214 
00215 
00217 #define US_IF_OFF               0x0000004C      
00218 #define US0_IF (USART0_BASE + US_IF_OFF)        
00219 #define US1_IF (USART1_BASE + US_IF_OFF)        
00221 
00222 #if defined(USART_HAS_PDC)
00223 
00226 #define US0_RPR (USART0_BASE + PERIPH_RPR_OFF)      
00227 #define US1_RPR (USART1_BASE + PERIPH_RPR_OFF)      
00229 
00230 
00232 #define US0_RCR (USART0_BASE + PERIPH_RCR_OFF)      
00233 #define US1_RCR (USART1_BASE + PERIPH_RCR_OFF)      
00235 
00236 
00238 #define US0_TPR (USART0_BASE + PERIPH_TPR_OFF)      
00239 #define US1_TPR (USART1_BASE + PERIPH_TPR_OFF)      
00241 
00242 
00244 #define US0_TCR (USART0_BASE + PERIPH_TCR_OFF)      
00245 #define US1_TCR (USART1_BASE + PERIPH_TCR_OFF)      
00247 
00248 #if defined(PERIPH_RNPR_OFF) && defined(PERIPH_RNCR_OFF)
00249 #define US0_RNPR   (USART0_BASE + PERIPH_RNPR_OFF)  
00250 #define US1_RNPR   (USART1_BASE + PERIPH_RNPR_OFF)  
00251 #define US0_RNCR   (USART0_BASE + PERIPH_RNCR_OFF)  
00252 #define US1_RNCR   (USART1_BASE + PERIPH_RNCR_OFF)  
00253 #endif
00254 
00255 #if defined(PERIPH_TNPR_OFF) && defined(PERIPH_TNCR_OFF)
00256 #define US0_TNPR   (USART0_BASE + PERIPH_TNPR_OFF)  
00257 #define US1_TNPR   (USART1_BASE + PERIPH_TNPR_OFF)  
00258 #define US0_TNCR   (USART0_BASE + PERIPH_TNCR_OFF)  
00259 #define US1_TNCR   (USART1_BASE + PERIPH_TNCR_OFF)  
00260 #endif
00261 
00262 #if defined(PERIPH_PTCR_OFF)
00263 #define US0_PTCR   (USART0_BASE + PERIPH_PTCR_OFF)  
00264 #define US1_PTCR   (USART1_BASE + PERIPH_PTCR_OFF)  
00265 #endif
00266 
00267 #if defined(PERIPH_PTSR_OFF)
00268 #define US0_PTSR   (USART0_BASE + PERIPH_PTSR_OFF)  
00269 #define US1_PTSR   (USART1_BASE + PERIPH_PTSR_OFF)  
00270 #endif
00271 
00272 #endif  /* USART_HAS_PDC */
00273 
00277 #endif                          /* _ARCH_ARM_AT91_US_H_ */

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