ih_at91irq1.c

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00001 /*
00002  * Copyright (C) 2005 by egnite Software GmbH. All rights reserved.
00003  *
00004  * Redistribution and use in source and binary forms, with or without
00005  * modification, are permitted provided that the following conditions
00006  * are met:
00007  *
00008  * 1. Redistributions of source code must retain the above copyright
00009  *    notice, this list of conditions and the following disclaimer.
00010  * 2. Redistributions in binary form must reproduce the above copyright
00011  *    notice, this list of conditions and the following disclaimer in the
00012  *    documentation and/or other materials provided with the distribution.
00013  * 3. Neither the name of the copyright holders nor the names of
00014  *    contributors may be used to endorse or promote products derived
00015  *    from this software without specific prior written permission.
00016  *
00017  * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
00018  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00019  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00020  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
00021  * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
00022  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
00023  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
00024  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
00025  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00026  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
00027  * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
00028  * SUCH DAMAGE.
00029  *
00030  * For additional information see http://www.ethernut.de/
00031  *
00032  */
00033 
00034 /*
00035  * $Log: ih_at91irq1.c,v $
00036  * Revision 1.3  2006/06/28 17:10:15  haraldkipp
00037  * Include more general header file for ARM.
00038  *
00039  * Revision 1.2  2006/04/07 12:21:43  haraldkipp
00040  * Added missing IRQ sense settings.
00041  *
00042  * Revision 1.1  2005/10/24 08:56:09  haraldkipp
00043  * First check in.
00044  *
00045  */
00046 
00047 #include <arch/arm.h>
00048 #include <dev/irqreg.h>
00049 
00050 #ifndef NUT_IRQPRI_IRQ1
00051 #define NUT_IRQPRI_IRQ1  4
00052 #endif
00053 
00054 static int Interrupt1Ctl(int cmd, void *param);
00055 
00056 IRQ_HANDLER sig_INTERRUPT1 = {
00057 #ifdef NUT_PERFMON
00058     0,                  /* Interrupt counter, ir_count. */
00059 #endif
00060     NULL,               /* Passed argument, ir_arg. */
00061     NULL,               /* Handler subroutine, ir_handler. */
00062     Interrupt1Ctl       /* Interrupt control, ir_ctl. */
00063 };
00064 
00068 static void Interrupt1Entry(void) __attribute__ ((naked));
00069 void Interrupt1Entry(void)
00070 {
00071     IRQ_ENTRY();
00072 #ifdef NUT_PERFMON
00073     sig_INTERRUPT1.ir_count++;
00074 #endif
00075     if (sig_INTERRUPT1.ir_handler) {
00076         (sig_INTERRUPT1.ir_handler) (sig_INTERRUPT1.ir_arg);
00077     }
00078     IRQ_EXIT();
00079 }
00080 
00096 static int Interrupt1Ctl(int cmd, void *param)
00097 {
00098     int rc = 0;
00099     u_int *ival = (u_int *)param;
00100     int enabled = inr(AIC_IMR) & _BV(IRQ1_ID);
00101 
00102     /* Disable interrupt. */
00103     if (enabled) {
00104         outr(AIC_IDCR, _BV(IRQ1_ID));
00105     }
00106 
00107     switch(cmd) {
00108     case NUT_IRQCTL_INIT:
00109         /* Set the vector. */
00110         outr(AIC_SVR(IRQ1_ID), (unsigned int)Interrupt1Entry);
00111         /* Initialize to edge triggered with defined priority. */
00112         outr(AIC_SMR(IRQ1_ID), AIC_SRCTYPE_EXT_HIGH_LEVEL | NUT_IRQPRI_IRQ1);
00113         /* Clear interrupt */
00114         outr(AIC_ICCR, _BV(IRQ1_ID));
00115         break;
00116     case NUT_IRQCTL_STATUS:
00117         if (enabled) {
00118             *ival |= 1;
00119         }
00120         else {
00121             *ival &= ~1;
00122         }
00123         break;
00124     case NUT_IRQCTL_ENABLE:
00125         enabled = 1;
00126         break;
00127     case NUT_IRQCTL_DISABLE:
00128         enabled = 0;
00129         break;
00130     case NUT_IRQCTL_GETMODE:
00131         {
00132             u_int val = inr(AIC_SMR(IRQ1_ID)) & AIC_SRCTYPE;
00133             if (val == AIC_SRCTYPE_EXT_LOW_LEVEL) {
00134                 *ival = NUT_IRQMODE_LOWLEVEL;
00135             } else if (val == AIC_SRCTYPE_EXT_HIGH_LEVEL) {
00136                 *ival = NUT_IRQMODE_HIGHLEVEL;
00137             } else if (val == AIC_SRCTYPE_EXT_POSITIVE_EDGE) {
00138                 *ival = NUT_IRQMODE_RISINGEDGE;
00139             } else  {
00140                 *ival = NUT_IRQMODE_FALLINGEDGE;
00141             }
00142         }
00143         break;
00144     case NUT_IRQCTL_SETMODE:
00145         if (*ival == NUT_IRQMODE_LOWLEVEL) {
00146             outr(AIC_SMR(IRQ1_ID), (inr(AIC_SMR(IRQ1_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_EXT_LOW_LEVEL);
00147         } else if (*ival == NUT_IRQMODE_HIGHLEVEL) {
00148             outr(AIC_SMR(IRQ1_ID), (inr(AIC_SMR(IRQ1_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_EXT_HIGH_LEVEL);
00149         } else if (*ival == NUT_IRQMODE_FALLINGEDGE) {
00150             outr(AIC_SMR(IRQ1_ID), (inr(AIC_SMR(IRQ1_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_EXT_NEGATIVE_EDGE);
00151         } else  if (*ival == NUT_IRQMODE_RISINGEDGE) {
00152             outr(AIC_SMR(IRQ1_ID), (inr(AIC_SMR(IRQ1_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_EXT_POSITIVE_EDGE);
00153         } else  {
00154             rc = -1;
00155         }
00156         break;
00157     case NUT_IRQCTL_GETPRIO:
00158         *ival = inr(AIC_SMR(IRQ1_ID)) & AIC_PRIOR;
00159         break;
00160     case NUT_IRQCTL_SETPRIO:
00161         outr(AIC_SMR(IRQ1_ID), (inr(AIC_SMR(IRQ1_ID)) & ~AIC_PRIOR) | *ival);
00162         break;
00163 #ifdef NUT_PERFMON
00164     case NUT_IRQCTL_GETCOUNT:
00165         *ival = (u_int)sig_INTERRUPT1.ir_count;
00166         sig_INTERRUPT1.ir_count = 0;
00167         break;
00168 #endif
00169     default:
00170         rc = -1;
00171         break;
00172     }
00173 
00174     /* Enable interrupt. */
00175     if (enabled) {
00176         outr(AIC_IECR, _BV(IRQ1_ID));
00177     }
00178     return rc;
00179 }
00180 

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