00001 /* 00002 * Copyright (C) 2001-2004 by egnite Software GmbH. All rights reserved. 00003 * 00004 * Redistribution and use in source and binary forms, with or without 00005 * modification, are permitted provided that the following conditions 00006 * are met: 00007 * 00008 * 1. Redistributions of source code must retain the above copyright 00009 * notice, this list of conditions and the following disclaimer. 00010 * 2. Redistributions in binary form must reproduce the above copyright 00011 * notice, this list of conditions and the following disclaimer in the 00012 * documentation and/or other materials provided with the distribution. 00013 * 3. Neither the name of the copyright holders nor the names of 00014 * contributors may be used to endorse or promote products derived 00015 * from this software without specific prior written permission. 00016 * 00017 * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS 00018 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 00019 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 00020 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE 00021 * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 00022 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 00023 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 00024 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 00025 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00026 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 00027 * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 00028 * SUCH DAMAGE. 00029 * 00030 * For additional information see http://www.ethernut.de/ 00031 * 00032 */ 00033 00034 /* 00035 * $Log: ostimer_s3c4510b.c,v $ 00036 * Revision 1.5 2008/07/08 08:25:04 haraldkipp 00037 * NutDelay is no more architecture specific. 00038 * Number of loops per millisecond is configurable or will be automatically 00039 * determined. 00040 * A new function NutMicroDelay provides shorter delays. 00041 * 00042 * Revision 1.4 2007/08/17 10:44:37 haraldkipp 00043 * Timer enable/disable macro replaces previous global interrupt 00044 * enable/disable or function calling. 00045 * 00046 * Revision 1.3 2006/10/08 16:48:07 haraldkipp 00047 * Documentation fixed 00048 * 00049 * Revision 1.2 2005/10/24 08:58:48 haraldkipp 00050 * Header file moved. 00051 * 00052 * Revision 1.1 2005/07/26 18:02:26 haraldkipp 00053 * Moved from dev. 00054 * 00055 * Revision 1.2 2005/07/20 09:17:26 haraldkipp 00056 * Default NUT_CPU_FREQ and NUT_TICK_FREQ added. 00057 * NutTimerIntr() removed, because we can use the hardware independent code. 00058 * 00059 * Revision 1.1 2005/05/27 17:16:40 drsung 00060 * Moved the file. 00061 * 00062 * Revision 1.5 2005/04/05 17:50:46 haraldkipp 00063 * Use register names in gba.h. 00064 * 00065 * Revision 1.4 2004/11/08 19:16:37 haraldkipp 00066 * Hacked in Gameboy timer support 00067 * 00068 * Revision 1.3 2004/10/03 18:42:21 haraldkipp 00069 * No GBA support yet, but let the compiler run through 00070 * 00071 * Revision 1.2 2004/09/08 10:19:39 haraldkipp 00072 * Running on AT91 and S3C, thanks to James Tyou 00073 * 00074 */ 00075 00076 #include <cfg/arch.h> 00077 #if defined(MCU_AT91R40008) 00078 #include <arch/arm/at91.h> 00079 00080 #elif defined(MCU_S3C4510B) 00081 #include <arch/arm.h> 00082 #include <dev/s3c4510b_hw.h> 00083 #include <dev/s3c4510b_irqs.h> 00084 00085 #elif defined(MCU_GBA) 00086 #include <arch/gba.h> 00087 #include <dev/irqreg.h> 00088 00089 #endif 00090 00091 #ifndef NUT_CPU_FREQ 00092 #define NUT_CPU_FREQ 1000000UL 00093 #endif 00094 00095 #ifndef NUT_TICK_FREQ 00096 #define NUT_TICK_FREQ 1000UL 00097 #endif 00098 00099 #if defined(MCU_AT91R40008) 00100 static int dummy; 00101 #endif 00102 00103 static void (*os_handler) (void *); 00104 00108 #if defined(MCU_AT91R40008) 00109 void Timer0Entry(void) __attribute__ ((naked)); 00110 void Timer0Entry(void) 00111 { 00112 IRQ_ENTRY(); 00113 dummy = inr(TC0_SR); 00114 os_handler(0); 00115 IRQ_EXIT(); 00116 } 00117 00118 #elif defined(MCU_GBA) 00119 00120 void Timer3Entry(void *arg) 00121 { 00122 outw(REG_IF, INT_TMR3); 00123 os_handler(0); 00124 } 00125 00126 #endif 00127 00139 void NutRegisterTimer(void (*handler) (void *)) 00140 { 00141 os_handler = handler; 00142 00143 #if defined(MCU_AT91R40008) 00144 00145 /* Disable the Clock Counter */ 00146 outr(TC0_CCR, TC_CLKDIS); 00147 /* Disable all interrupts */ 00148 outr(TC0_IDR, 0xFFFFFFFF); 00149 /* Clear the status register. */ 00150 dummy = inr(TC0_SR); 00151 /* Select divider and compare trigger */ 00152 outr(TC0_CMR, TC_CLKS_MCK32 | TC_CPCTRG); 00153 /* Enable the Clock counter */ 00154 outr(TC0_CCR, TC_CLKEN); 00155 /* Validate the RC compare interrupt */ 00156 outr(TC0_IER, TC_CPCS); 00157 00158 /* Disable timer 0 interrupts. */ 00159 outr(AIC_IDCR, _BV(TC0_ID)); 00160 /* Set the TC0 IRQ handler address */ 00161 outr(AIC_SVR(4), (unsigned int)Timer0Entry); 00162 /* Set the trigg and priority for timer 0 interrupt */ 00163 /* Level 7 is highest, level 0 lowest. */ 00164 outr(AIC_SMR(4), (AIC_SRCTYPE_INT_LEVEL_SENSITIVE | 0x4)); 00165 /* Clear timer 0 interrupt */ 00166 outr(AIC_ICCR, _BV(TC0_ID)); 00167 /* Enable timer 0 interrupts */ 00168 outr(AIC_IECR, _BV(TC0_ID)); 00169 00170 /* Set compare value for 1 ms. */ 00171 outr(TC0_RC, 0x80F); 00172 /* Software trigger starts the clock. */ 00173 outr(TC0_CCR, TC_SWTRG); 00174 00175 #elif defined(MCU_S3C4510B) 00176 00177 INT_DISABLE(IRQ_TIMER); 00178 CSR_WRITE(TCNT0, 0); 00179 CSR_WRITE(TDATA0, CLOCK_TICK_RATE); 00180 CSR_WRITE(TMOD, TMOD_TIMER0_VAL); 00181 00182 CLEAR_PEND_INT(IRQ_TIMER); 00183 00184 NutRegisterIrqHandler( 00185 &InterruptHandlers[IRQ_TIMER], handler, 0); 00186 00187 INT_ENABLE(IRQ_TIMER); 00188 00189 #elif defined(MCU_GBA) 00190 00191 /* Disable master interrupt. */ 00192 outw(REG_IME, 0); 00193 00194 /* Set global interrupt vector. */ 00195 NutRegisterIrqHandler(&sig_TMR3, Timer3Entry, 0); 00196 00197 /* Enable timer and timer interrupts. */ 00198 outdw(REG_TMR3CNT, TMR_IRQ_ENA | TMR_ENA | 48756); 00199 00200 /* Enable timer 3 interrupts. */ 00201 outw(REG_IE, inw(REG_IE) | INT_TMR3); 00202 00203 /* Enable master interrupt. */ 00204 outw(REG_IME, 1); 00205 00206 #else 00207 #warning "MCU not defined" 00208 #endif 00209 } 00210 00216 u_long NutGetCpuClock(void) 00217 { 00218 return NUT_CPU_FREQ; 00219 } 00220 00226 u_long NutGetTickClock(void) 00227 { 00228 return NUT_TICK_FREQ; 00229 } 00230 00234 u_long NutTimerMillisToTicks(u_long ms) 00235 { 00236 return ms * 1000L / NutGetTickClock(); 00237 } 00238 00239