ih_timer3_capt.c

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00001 /*
00002  * Copyright (C) 2001-2005 by egnite Software GmbH. All rights reserved.
00003  *
00004  * Redistribution and use in source and binary forms, with or without
00005  * modification, are permitted provided that the following conditions
00006  * are met:
00007  *
00008  * 1. Redistributions of source code must retain the above copyright
00009  *    notice, this list of conditions and the following disclaimer.
00010  * 2. Redistributions in binary form must reproduce the above copyright
00011  *    notice, this list of conditions and the following disclaimer in the
00012  *    documentation and/or other materials provided with the distribution.
00013  * 3. Neither the name of the copyright holders nor the names of
00014  *    contributors may be used to endorse or promote products derived
00015  *    from this software without specific prior written permission.
00016  *
00017  * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
00018  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00019  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00020  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
00021  * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
00022  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
00023  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
00024  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
00025  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00026  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
00027  * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
00028  * SUCH DAMAGE.
00029  *
00030  * For additional information see http://www.ethernut.de/
00031  *
00032  */
00033 
00086 #include <dev/irqreg.h>
00087 
00088 #if defined(MCU_AT90CAN128) || defined(MCU_ATMEGA2560) || defined(MCU_ATMEGA2561)
00089 #define INT_MASK_REG    TIMSK3
00090 #define INT_STATUS_REG  TIFR3
00091 #define INT_ENABLE_BIT  ICIE3
00092 #define INT_STATUS_BIT  ICF3
00093 #define INT_PRIORITY    0
00094 #else
00095 #define INT_MASK_REG    ETIMSK
00096 #define INT_STATUS_REG  ETIFR
00097 #define INT_ENABLE_BIT  TICIE3
00098 #define INT_STATUS_BIT  ICF3
00099 #define INT_PRIORITY    0
00100 #endif
00101 
00106 
00107 #if defined(SIG_INPUT_CAPTURE3) || defined(iv_TIMER3_CAPT)
00108 
00109 static int AvrTimer3InCaptIrqCtl(int cmd, void *param);
00110 
00111 IRQ_HANDLER sig_INPUT_CAPTURE3 = {
00112 #ifdef NUT_PERFMON
00113     0,                          /* Interrupt counter, ir_count. */
00114 #endif
00115     NULL,                       /* Passed argument, ir_arg. */
00116     NULL,                       /* Handler subroutine, ir_handler. */
00117     AvrTimer3InCaptIrqCtl       /* Interrupt control, ir_ctl. */
00118 };
00119 
00134 static int AvrTimer3InCaptIrqCtl(int cmd, void *param)
00135 {
00136     int rc = 0;
00137     u_int *ival = (u_int *) param;
00138     int_fast8_t enabled = bit_is_set(INT_MASK_REG, INT_ENABLE_BIT);
00139 
00140     /* Disable interrupt. */
00141     cbi(INT_MASK_REG, INT_ENABLE_BIT);
00142 
00143     switch (cmd) {
00144     case NUT_IRQCTL_INIT:
00145     case NUT_IRQCTL_CLEAR:
00146         /* Clear any pending interrupt. */
00147         outb(INT_STATUS_REG, _BV(INT_STATUS_BIT));
00148         break;
00149     case NUT_IRQCTL_STATUS:
00150         if (bit_is_set(INT_STATUS_REG, INT_STATUS_BIT)) {
00151             *ival = 1;
00152         } else {
00153             *ival = 0;
00154         }
00155         if (enabled) {
00156             *ival |= 0x80;
00157         }
00158         break;
00159     case NUT_IRQCTL_ENABLE:
00160         enabled = 1;
00161         break;
00162     case NUT_IRQCTL_DISABLE:
00163         enabled = 0;
00164         break;
00165     case NUT_IRQCTL_GETPRIO:
00166         *ival = INT_PRIORITY;
00167         break;
00168 #ifdef NUT_PERFMON
00169     case NUT_IRQCTL_GETCOUNT:
00170         *ival = (u_int) sig_INPUT_CAPTURE3.ir_count;
00171         sig_INPUT_CAPTURE3.ir_count = 0;
00172         break;
00173 #endif
00174     default:
00175         rc = -1;
00176         break;
00177     }
00178 
00179     /* Enable interrupt. */
00180     if (enabled) {
00181         sbi(INT_MASK_REG, INT_ENABLE_BIT);
00182     }
00183     return rc;
00184 }
00185 
00189 #ifdef __IMAGECRAFT__
00190 #pragma interrupt_handler SIG_INPUT_CAPTURE3:iv_TIMER3_CAPT
00191 #endif
00192 NUTSIGNAL(SIG_INPUT_CAPTURE3, sig_INPUT_CAPTURE3)
00193 #endif
00194 

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