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00047 #include <cfg/arch/avr.h>
00048 #include <cfg/audio.h>
00049
00050 #include <sys/atom.h>
00051 #include <sys/event.h>
00052 #include <sys/timer.h>
00053 #include <sys/heap.h>
00054
00055 #include <dev/irqreg.h>
00056 #include <dev/vs10xx.h>
00057
00058 #include <sys/bankmem.h>
00059
00060 #include <stddef.h>
00061
00066
00067 #if !defined(AUDIO_VS1001K) && !defined(AUDIO_VS1011E) && !defined(AUDIO_VS1002D) && !defined(AUDIO_VS1003B) && !defined(AUDIO_VS1033C)
00068 #define AUDIO_VS1001K
00069 #endif
00070
00071 #ifndef VS10XX_FREQ
00072
00073 #define VS10XX_FREQ 12288000UL
00074 #endif
00075
00076 #ifndef VS10XX_HWRST_DURATION
00077
00078 #define VS10XX_HWRST_DURATION 1
00079 #endif
00080
00081 #ifndef VS10XX_HWRST_RECOVER
00082
00083 #define VS10XX_HWRST_RECOVER 4
00084 #endif
00085
00086 #ifndef VS10XX_SWRST_RECOVER
00087
00088 #define VS10XX_SWRST_RECOVER 2
00089 #endif
00090
00091 #ifndef VS10XX_SCI_MODE
00092 #define VS10XX_SCI_MODE 0
00093 #endif
00094
00095 #ifndef VS10XX_SCI_RATE
00096 #define VS10XX_SCI_RATE (VS10XX_FREQ / 4)
00097 #endif
00098
00099 #ifndef VS10XX_SDI_MODE
00100 #define VS10XX_SDI_MODE 0
00101 #endif
00102
00103 #ifndef VS10XX_SDI_RATE
00104 #define VS10XX_SDI_RATE (VS10XX_FREQ / 4)
00105 #endif
00106
00107 #if defined(VS10XX_SCI_SPI0_DEVICE)
00108
00109 #include <dev/sppif0.h>
00110 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00111 #define SciReset(act) Sppi0ChipReset(VS10XX_SCI_SPI0_DEVICE, act)
00112 #else
00113 #define SciReset(act) Sppi0ChipReset(VS10XX_SCI_SPI0_DEVICE, !act)
00114 #endif
00115 #define SciSetMode() Sppi0SetMode(VS10XX_SCI_SPI0_DEVICE, VS10XX_SCI_MODE)
00116 #define SciSetSpeed() Sppi0SetSpeed(VS10XX_SCI_SPI0_DEVICE, VS10XX_SCI_RATE)
00117 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00118 #define SciSelect() Sppi0SelectDevice(VS10XX_SCI_SPI0_DEVICE)
00119 #define SciDeselect() Sppi0DeselectDevice(VS10XX_SCI_SPI0_DEVICE)
00120 #else
00121 #define SciSelect() Sppi0NegSelectDevice(VS10XX_SCI_SPI0_DEVICE)
00122 #define SciDeselect() Sppi0NegDeselectDevice(VS10XX_SCI_SPI0_DEVICE)
00123 #endif
00124 #define SciByte Sppi0Byte
00125
00126 #elif defined(VS10XX_SCI_SBBI0_DEVICE)
00127
00128 #include <dev/sbbif0.h>
00129 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00130 #define SciReset(act) Sbbi0ChipReset(VS10XX_SCI_SBBI0_DEVICE, act)
00131 #else
00132 #define SciReset(act) Sbbi0ChipReset(VS10XX_SCI_SBBI0_DEVICE, !act)
00133 #endif
00134 #define SciSetMode() Sbbi0SetMode(VS10XX_SCI_SBBI0_DEVICE, VS10XX_SCI_MODE)
00135 #define SciSetSpeed() Sbbi0SetSpeed(VS10XX_SCI_SBBI0_DEVICE, VS10XX_SCI_RATE)
00136 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00137 #define SciSelect() Sbbi0SelectDevice(VS10XX_SCI_SBBI0_DEVICE)
00138 #define SciDeselect() Sbbi0DeselectDevice(VS10XX_SCI_SBBI0_DEVICE)
00139 #else
00140 #define SciSelect() Sbbi0NegSelectDevice(VS10XX_SCI_SBBI0_DEVICE)
00141 #define SciDeselect() Sbbi0NegDeselectDevice(VS10XX_SCI_SBBI0_DEVICE)
00142 #endif
00143 #define SciByte Sbbi0Byte
00144
00145 #elif defined(VS10XX_SCI_SBBI1_DEVICE)
00146
00147 #include <dev/sbbif1.h>
00148 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00149 #define SciReset(act) Sbbi1ChipReset(VS10XX_SCI_SBBI1_DEVICE, act)
00150 #else
00151 #define SciReset(act) Sbbi1ChipReset(VS10XX_SCI_SBBI1_DEVICE, !act)
00152 #endif
00153 #define SciSetMode() Sbbi1SetMode(VS10XX_SCI_SBBI1_DEVICE, VS10XX_SCI_MODE)
00154 #define SciSetSpeed() Sbbi1SetSpeed(VS10XX_SCI_SBBI1_DEVICE, VS10XX_SCI_RATE)
00155 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00156 #define SciSelect() Sbbi1SelectDevice(VS10XX_SCI_SBBI1_DEVICE)
00157 #define SciDeselect() Sbbi1DeselectDevice(VS10XX_SCI_SBBI1_DEVICE)
00158 #else
00159 #define SciSelect() Sbbi1NegSelectDevice(VS10XX_SCI_SBBI1_DEVICE)
00160 #define SciDeselect() Sbbi1NegDeselectDevice(VS10XX_SCI_SBBI1_DEVICE)
00161 #endif
00162 #define SciByte Sbbi1Byte
00163
00164 #elif defined(VS10XX_SCI_SBBI2_DEVICE)
00165
00166 #include <dev/sbbif2.h>
00167 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00168 #define SciReset(act) Sbbi2ChipReset(VS10XX_SCI_SBBI2_DEVICE, act)
00169 #else
00170 #define SciReset(act) Sbbi2ChipReset(VS10XX_SCI_SBBI2_DEVICE, !act)
00171 #endif
00172 #define SciSetMode() Sbbi2SetMode(VS10XX_SCI_SBBI2_DEVICE, VS10XX_SCI_MODE)
00173 #define SciSetSpeed() Sbbi2SetSpeed(VS10XX_SCI_SBBI2_DEVICE, VS10XX_SCI_RATE)
00174 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00175 #define SciSelect() Sbbi2SelectDevice(VS10XX_SCI_SBBI2_DEVICE)
00176 #define SciDeselect() Sbbi2DeselectDevice(VS10XX_SCI_SBBI2_DEVICE)
00177 #else
00178 #define SciSelect() Sbbi2NegSelectDevice(VS10XX_SCI_SBBI2_DEVICE)
00179 #define SciDeselect() Sbbi2NegDeselectDevice(VS10XX_SCI_SBBI2_DEVICE)
00180 #endif
00181 #define SciByte Sbbi2Byte
00182
00183 #elif defined(VS10XX_SCI_SBBI3_DEVICE)
00184
00185 #include <dev/sbbif3.h>
00186 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00187 #define SciReset(act) Sbbi3ChipReset(VS10XX_SCI_SBBI3_DEVICE, act)
00188 #else
00189 #define SciReset(act) Sbbi3ChipReset(VS10XX_SCI_SBBI3_DEVICE, !act)
00190 #endif
00191 #define SciSetMode() Sbbi3SetMode(VS10XX_SCI_SBBI3_DEVICE, VS10XX_SCI_MODE)
00192 #define SciSetSpeed() Sbbi3SetSpeed(VS10XX_SCI_SBBI3_DEVICE, VS10XX_SCI_RATE)
00193 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00194 #define SciSelect() Sbbi3SelectDevice(VS10XX_SCI_SBBI3_DEVICE)
00195 #define SciDeselect() Sbbi3DeselectDevice(VS10XX_SCI_SBBI3_DEVICE)
00196 #else
00197 #define SciSelect() Sbbi3NegSelectDevice(VS10XX_SCI_SBBI3_DEVICE)
00198 #define SciDeselect() Sbbi3NegDeselectDevice(VS10XX_SCI_SBBI3_DEVICE)
00199 #endif
00200 #define SciByte Sbbi3Byte
00201
00202 #endif
00203
00204
00205 #if defined(VS10XX_SDI_SPI0_DEVICE)
00206
00207 #include <dev/sppif0.h>
00208 #define SdiSetMode() Sppi0SetMode(VS10XX_SDI_SPI0_DEVICE, VS10XX_SDI_MODE)
00209 #define SdiSetSpeed() Sppi0SetSpeed(VS10XX_SDI_SPI0_DEVICE, VS10XX_SDI_RATE)
00210 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00211 #define SdiSelect() Sppi0SelectDevice(VS10XX_SDI_SPI0_DEVICE)
00212 #define SdiDeselect() Sppi0DeselectDevice(VS10XX_SDI_SPI0_DEVICE)
00213 #else
00214 #define SdiSelect() Sppi0NegSelectDevice(VS10XX_SDI_SPI0_DEVICE)
00215 #define SdiDeselect() Sppi0NegDeselectDevice(VS10XX_SDI_SPI0_DEVICE)
00216 #endif
00217 #define SdiByte Sppi0Byte
00218
00219 #elif defined(VS10XX_SDI_SBBI0_DEVICE)
00220
00221 #include <dev/sbbif0.h>
00222 #define SdiSetMode() Sbbi0SetMode(VS10XX_SDI_SBBI0_DEVICE, VS10XX_SDI_MODE)
00223 #define SdiSetSpeed() Sbbi0SetSpeed(VS10XX_SDI_SBBI0_DEVICE, VS10XX_SDI_RATE)
00224 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00225 #define SdiSelect() Sbbi0SelectDevice(VS10XX_SDI_SBBI0_DEVICE)
00226 #define SdiDeselect() Sbbi0DeselectDevice(VS10XX_SDI_SBBI0_DEVICE)
00227 #else
00228 #define SdiSelect() Sbbi0NegSelectDevice(VS10XX_SDI_SBBI0_DEVICE)
00229 #define SdiDeselect() Sbbi0NegDeselectDevice(VS10XX_SDI_SBBI0_DEVICE)
00230 #endif
00231 #define SdiByte Sbbi0Byte
00232
00233 #elif defined(VS10XX_SDI_SBBI1_DEVICE)
00234
00235 #include <dev/sbbif1.h>
00236 #define SdiSetMode() Sbbi1SetMode(VS10XX_SDI_SBBI1_DEVICE, VS10XX_SDI_MODE)
00237 #define SdiSetSpeed() Sbbi1SetSpeed(VS10XX_SDI_SBBI1_DEVICE, VS10XX_SDI_RATE)
00238 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00239 #define SdiSelect() Sbbi1SelectDevice(VS10XX_SDI_SBBI1_DEVICE)
00240 #define SdiDeselect() Sbbi1DeselectDevice(VS10XX_SDI_SBBI1_DEVICE)
00241 #else
00242 #define SdiSelect() Sbbi1NegSelectDevice(VS10XX_SDI_SBBI1_DEVICE)
00243 #define SdiDeselect() Sbbi1NegDeselectDevice(VS10XX_SDI_SBBI1_DEVICE)
00244 #endif
00245 #define SdiByte Sbbi1Byte
00246
00247 #elif defined(VS10XX_SDI_SBBI2_DEVICE)
00248
00249 #include <dev/sbbif2.h>
00250 #define SdiSetMode() Sbbi2SetMode(VS10XX_SDI_SBBI2_DEVICE, VS10XX_SDI_MODE)
00251 #define SdiSetSpeed() Sbbi2SetSpeed(VS10XX_SDI_SBBI2_DEVICE, VS10XX_SDI_RATE)
00252 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00253 #define SdiSelect() Sbbi2SelectDevice(VS10XX_SDI_SBBI2_DEVICE)
00254 #define SdiDeselect() Sbbi2DeselectDevice(VS10XX_SDI_SBBI2_DEVICE)
00255 #else
00256 #define SdiSelect() Sbbi2NegSelectDevice(VS10XX_SDI_SBBI2_DEVICE)
00257 #define SdiDeselect() Sbbi2NegDeselectDevice(VS10XX_SDI_SBBI2_DEVICE)
00258 #endif
00259 #define SdiByte Sbbi2Byte
00260
00261 #elif defined(VS10XX_SDI_SBBI3_DEVICE)
00262
00263 #include <dev/sbbif3.h>
00264 #define SdiSetMode() Sbbi3SetMode(VS10XX_SDI_SBBI3_DEVICE, VS10XX_SDI_MODE)
00265 #define SdiSetSpeed() Sbbi3SetSpeed(VS10XX_SDI_SBBI3_DEVICE, VS10XX_SDI_RATE)
00266 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00267 #define SdiSelect() Sbbi3SelectDevice(VS10XX_SDI_SBBI3_DEVICE)
00268 #define SdiDeselect() Sbbi3DeselectDevice(VS10XX_SDI_SBBI3_DEVICE)
00269 #else
00270 #define SdiSelect() Sbbi3NegSelectDevice(VS10XX_SDI_SBBI3_DEVICE)
00271 #define SdiDeselect() Sbbi3NegDeselectDevice(VS10XX_SDI_SBBI3_DEVICE)
00272 #endif
00273 #define SdiByte Sbbi3Byte
00274
00275 #endif
00276
00277
00278
00279
00280 #if defined (MCU_AT91R40008) || defined (MCU_AT91SAM7X256) || defined (MCU_AT91SAM9260)
00281
00282 #if VS10XX_DREQ_BIT == 9
00283 #define VS10XX_SIGNAL sig_INTERRUPT0
00284 #else
00285 #define VS10XX_SIGNAL sig_INTERRUPT2
00286 #endif
00287
00288 #if defined(VS10XX_XCS_BIT)
00289
00290 #if !defined(VS10XX_XCS_PIO_ID)
00291 #define VS10XX_XCS_PE_REG PIO_PER
00292 #define VS10XX_XCS_OE_REG PIO_OER
00293 #define VS10XX_XCS_COD_REG PIO_CODR
00294 #define VS10XX_XCS_SOD_REG PIO_SODR
00295 #elif VS10XX_XCS_PIO_ID == PIOA_ID
00296 #define VS10XX_XCS_PE_REG PIOA_PER
00297 #define VS10XX_XCS_OE_REG PIOA_OER
00298 #define VS10XX_XCS_COD_REG PIOA_CODR
00299 #define VS10XX_XCS_SOD_REG PIOA_SODR
00300 #elif VS10XX_XCS_PIO_ID == PIOB_ID
00301 #define VS10XX_XCS_PE_REG PIOB_PER
00302 #define VS10XX_XCS_OE_REG PIOB_OER
00303 #define VS10XX_XCS_COD_REG PIOB_CODR
00304 #define VS10XX_XCS_SOD_REG PIOB_SODR
00305 #elif VS10XX_XCS_PIO_ID == PIOC_ID
00306 #define VS10XX_XCS_PE_REG PIOC_PER
00307 #define VS10XX_XCS_OE_REG PIOC_OER
00308 #define VS10XX_XCS_COD_REG PIOC_CODR
00309 #define VS10XX_XCS_SOD_REG PIOC_SODR
00310 #endif
00311 #define VS10XX_XCS_ENA() \
00312 outr(VS10XX_XCS_PE_REG, _BV(VS10XX_XCS_BIT)); \
00313 outr(VS10XX_XCS_OE_REG, _BV(VS10XX_XCS_BIT))
00314 #define VS10XX_XCS_CLR() outr(VS10XX_XCS_COD_REG, _BV(VS10XX_XCS_BIT))
00315 #define VS10XX_XCS_SET() outr(VS10XX_XCS_SOD_REG, _BV(VS10XX_XCS_BIT))
00316
00317 #else
00318
00319 #define VS10XX_XCS_ENA()
00320 #define VS10XX_XCS_CLR()
00321 #define VS10XX_XCS_SET()
00322
00323 #endif
00324
00325 #if defined(VS10XX_XDCS_BIT)
00326
00327 #if !defined(VS10XX_XDCS_PIO_ID)
00328 #define VS10XX_XDCS_PE_REG PIO_PER
00329 #define VS10XX_XDCS_OE_REG PIO_OER
00330 #define VS10XX_XDCS_COD_REG PIO_CODR
00331 #define VS10XX_XDCS_SOD_REG PIO_SODR
00332 #elif VS10XX_XDCS_PIO_ID == PIOA_ID
00333 #define VS10XX_XDCS_PE_REG PIOA_PER
00334 #define VS10XX_XDCS_OE_REG PIOA_OER
00335 #define VS10XX_XDCS_COD_REG PIOA_CODR
00336 #define VS10XX_XDCS_SOD_REG PIOA_SODR
00337 #elif VS10XX_XDCS_PIO_ID == PIOB_ID
00338 #define VS10XX_XDCS_PE_REG PIOB_PER
00339 #define VS10XX_XDCS_OE_REG PIOB_OER
00340 #define VS10XX_XDCS_COD_REG PIOB_CODR
00341 #define VS10XX_XDCS_SOD_REG PIOB_SODR
00342 #elif VS10XX_XDCS_PIO_ID == PIOC_ID
00343 #define VS10XX_XDCS_PE_REG PIOC_PER
00344 #define VS10XX_XDCS_OE_REG PIOC_OER
00345 #define VS10XX_XDCS_COD_REG PIOC_CODR
00346 #define VS10XX_XDCS_SOD_REG PIOC_SODR
00347 #endif
00348 #define VS10XX_XDCS_ENA() \
00349 outr(VS10XX_XDCS_PE_REG, _BV(VS10XX_XDCS_BIT)); \
00350 outr(VS10XX_XDCS_OE_REG, _BV(VS10XX_XDCS_BIT))
00351 #define VS10XX_XDCS_CLR() outr(VS10XX_XDCS_COD_REG, _BV(VS10XX_XDCS_BIT))
00352 #define VS10XX_XDCS_SET() outr(VS10XX_XDCS_SOD_REG, _BV(VS10XX_XDCS_BIT))
00353
00354 #else
00355
00356 #define VS10XX_XDCS_ENA()
00357 #define VS10XX_XDCS_CLR()
00358 #define VS10XX_XDCS_SET()
00359
00360 #endif
00361
00362 #if defined(VS10XX_DREQ_BIT)
00363
00364 #if !defined(VS10XX_DREQ_PIO_ID)
00365 #define VS10XX_DREQ_PE_REG PIO_PER
00366 #define VS10XX_DREQ_OD_REG PIO_ODR
00367 #define VS10XX_DREQ_PDS_REG PIO_PDSR
00368 #elif VS10XX_DREQ_PIO_ID == PIOA_ID
00369 #define VS10XX_DREQ_PE_REG PIOA_PER
00370 #define VS10XX_DREQ_OD_REG PIOA_ODR
00371 #define VS10XX_DREQ_PDS_REG PIOA_PDSR
00372 #elif VS10XX_DREQ_PIO_ID == PIOB_ID
00373 #define VS10XX_DREQ_PE_REG PIOB_PER
00374 #define VS10XX_DREQ_OD_REG PIOB_ODR
00375 #define VS10XX_DREQ_PDS_REG PIOB_PDSR
00376 #elif VS10XX_DREQ_PIO_ID == PIOC_ID
00377 #define VS10XX_DREQ_PE_REG PIOC_PER
00378 #define VS10XX_DREQ_OD_REG PIOC_ODR
00379 #define VS10XX_DREQ_PDS_REG PIOC_PDSR
00380 #endif
00381
00382 #define VS10XX_DREQ_PD_REG PIO_PDR
00383 #define VS10XX_DREQ_OD_REG PIO_ODR
00384 #define VS10XX_DREQ_PDS_REG PIO_PDSR
00385 #define VS10XX_DREQ_ENA() \
00386 outr(VS10XX_DREQ_PD_REG, _BV(VS10XX_DREQ_BIT)); \
00387 outr(VS10XX_DREQ_OD_REG, _BV(VS10XX_DREQ_BIT))
00388 #define VS10XX_DREQ_TST() ((inr(VS10XX_DREQ_PDS_REG) & _BV(VS10XX_DREQ_BIT)) == _BV(VS10XX_DREQ_BIT))
00389
00390 #else
00391
00392 #define VS10XX_DREQ_ENA()
00393 #define VS10XX_DREQ_TST() 0
00394
00395 #endif
00396
00397 #ifdef VS10XX_BSYNC_BIT
00398
00399 #if !defined(VS10XX_BSYNC_PIO_ID)
00400 #define VS10XX_BSYNC_PE_REG PIO_PER
00401 #define VS10XX_BSYNC_OE_REG PIO_OER
00402 #define VS10XX_BSYNC_COD_REG PIO_CODR
00403 #define VS10XX_BSYNC_SOD_REG PIO_SODR
00404 #elif VS10XX_BSYNC_PIO_ID == PIOA_ID
00405 #define VS10XX_BSYNC_PE_REG PIOA_PER
00406 #define VS10XX_BSYNC_OE_REG PIOA_OER
00407 #define VS10XX_BSYNC_COD_REG PIOA_CODR
00408 #define VS10XX_BSYNC_SOD_REG PIOA_SODR
00409 #elif VS10XX_BSYNC_PIO_ID == PIOB_ID
00410 #define VS10XX_BSYNC_PE_REG PIOB_PER
00411 #define VS10XX_BSYNC_OE_REG PIOB_OER
00412 #define VS10XX_BSYNC_COD_REG PIOB_CODR
00413 #define VS10XX_BSYNC_SOD_REG PIOB_SODR
00414 #elif VS10XX_BSYNC_PIO_ID == PIOC_ID
00415 #define VS10XX_BSYNC_PE_REG PIOC_PER
00416 #define VS10XX_BSYNC_OE_REG PIOC_OER
00417 #define VS10XX_BSYNC_COD_REG PIOC_CODR
00418 #define VS10XX_BSYNC_SOD_REG PIOC_SODR
00419 #endif
00420 #define VS10XX_BSYNC_ENA() \
00421 outr(VS10XX_BSYNC_PE_REG, _BV(VS10XX_BSYNC_BIT)); \
00422 outr(VS10XX_BSYNC_OE_REG, _BV(VS10XX_BSYNC_BIT))
00423 #define VS10XX_BSYNC_CLR() outr(VS10XX_BSYNC_COD_REG, _BV(VS10XX_BSYNC_BIT))
00424 #define VS10XX_BSYNC_SET() outr(VS10XX_BSYNC_SOD_REG, _BV(VS10XX_BSYNC_BIT))
00425
00426 #else
00427
00428 #define VS10XX_BSYNC_ENA()
00429 #define VS10XX_BSYNC_CLR()
00430 #define VS10XX_BSYNC_SET()
00431
00432 #endif
00433
00434
00435
00436
00437
00438 #elif defined(__AVR__)
00439
00440 #if !defined(VS10XX_SIGNAL_IRQ)
00441 #define VS10XX_SIGNAL_IRQ INT6
00442 #endif
00443
00444 #if (VS10XX_SIGNAL_IRQ == INT0)
00445 #define VS10XX_SIGNAL sig_INTERRUPT0
00446 #define VS10XX_DREQ_BIT 0
00447 #define VS10XX_DREQ_PDS_REG PIND
00448 #define VS10XX_DREQ_PUE_REG PORTD
00449 #define VS10XX_DREQ_OE_REG DDRD
00450
00451 #elif (VS10XX_SIGNAL_IRQ == INT1)
00452 #define VS10XX_SIGNAL sig_INTERRUPT1
00453 #define VS10XX_DREQ_BIT 1
00454 #define VS10XX_DREQ_PDS_REG PIND
00455 #define VS10XX_DREQ_PUE_REG PORTD
00456 #define VS10XX_DREQ_OE_REG DDRD
00457
00458 #elif (VS10XX_SIGNAL_IRQ == INT2)
00459 #define VS10XX_SIGNAL sig_INTERRUPT2
00460 #define VS10XX_DREQ_BIT 2
00461 #define VS10XX_DREQ_PDS_REG PIND
00462 #define VS10XX_DREQ_PUE_REG PORTD
00463 #define VS10XX_DREQ_OE_REG DDRD
00464
00465 #elif (VS10XX_SIGNAL_IRQ == INT3)
00466 #define VS10XX_SIGNAL sig_INTERRUPT3
00467 #define VS10XX_DREQ_BIT 3
00468 #define VS10XX_DREQ_PDS_REG PIND
00469 #define VS10XX_DREQ_PUE_REG PORTD
00470 #define VS10XX_DREQ_OE_REG DDRD
00471
00472 #elif (VS10XX_SIGNAL_IRQ == INT4)
00473 #define VS10XX_SIGNAL sig_INTERRUPT4
00474 #define VS10XX_DREQ_BIT 4
00475 #define VS10XX_DREQ_PDS_REG PINE
00476 #define VS10XX_DREQ_PUE_REG PORTE
00477 #define VS10XX_DREQ_OE_REG DDRE
00478
00479 #elif (VS10XX_SIGNAL_IRQ == INT5)
00480 #define VS10XX_SIGNAL sig_INTERRUPT5
00481 #define VS10XX_DREQ_BIT 5
00482 #define VS10XX_DREQ_PDS_REG PINE
00483 #define VS10XX_DREQ_PUE_REG PORTE
00484 #define VS10XX_DREQ_OE_REG DDRE
00485
00486 #elif (VS10XX_SIGNAL_IRQ == INT7)
00487 #define VS10XX_SIGNAL sig_INTERRUPT7
00488 #define VS10XX_DREQ_BIT 7
00489 #define VS10XX_DREQ_PDS_REG PINE
00490 #define VS10XX_DREQ_PUE_REG PORTE
00491 #define VS10XX_DREQ_OE_REG DDRE
00492
00493 #else
00494 #define VS10XX_SIGNAL sig_INTERRUPT6
00495 #define VS10XX_DREQ_BIT 6
00496 #define VS10XX_DREQ_PDS_REG PINE
00497 #define VS10XX_DREQ_PUE_REG PORTE
00498 #define VS10XX_DREQ_OE_REG DDRE
00499
00500 #endif
00501
00502 #define VS10XX_DREQ_ENA() \
00503 cbi(VS10XX_DREQ_OE_REG, VS10XX_DREQ_BIT); \
00504 sbi(VS10XX_DREQ_PUE_REG, VS10XX_DREQ_BIT)
00505 #define VS10XX_DREQ_TST() ((inb(VS10XX_DREQ_PDS_REG) & _BV(VS10XX_DREQ_BIT)) == _BV(VS10XX_DREQ_BIT))
00506
00507
00508 #if defined(VS10XX_XCS_BIT)
00509
00510 #if (VS10XX_XCS_AVRPORT == AVRPORTA)
00511 #define VS10XX_XCS_SOD_REG PORTA
00512 #define VS10XX_XCS_OE_REG DDRA
00513 #elif (VS10XX_XCS_AVRPORT == AVRPORTB)
00514 #define VS10XX_XCS_SOD_REG PORTB
00515 #define VS10XX_XCS_OE_REG DDRB
00516 #elif (VS10XX_XCS_AVRPORT == AVRPORTD)
00517 #define VS10XX_XCS_SOD_REG PORTD
00518 #define VS10XX_XCS_OE_REG DDRD
00519 #elif (VS10XX_XCS_AVRPORT == AVRPORTE)
00520 #define VS10XX_XCS_SOD_REG PORTE
00521 #define VS10XX_XCS_OE_REG DDRE
00522 #elif (VS10XX_XCS_AVRPORT == AVRPORTF)
00523 #define VS10XX_XCS_SOD_REG PORTF
00524 #define VS10XX_XCS_OE_REG DDRF
00525 #elif (VS10XX_XCS_AVRPORT == AVRPORTG)
00526 #define VS10XX_XCS_SOD_REG PORTG
00527 #define VS10XX_XCS_OE_REG DDRG
00528 #elif (VS10XX_XCS_AVRPORT == AVRPORTH)
00529 #define VS10XX_XCS_SOD_REG PORTH
00530 #define VS10XX_XCS_OE_REG DDRH
00531 #endif
00532 #define VS10XX_XCS_ENA() sbi(VS10XX_XCS_OE_REG, VS10XX_XCS_BIT)
00533 #define VS10XX_XCS_CLR() cbi(VS10XX_XCS_SOD_REG, VS10XX_XCS_BIT)
00534 #define VS10XX_XCS_SET() sbi(VS10XX_XCS_SOD_REG, VS10XX_XCS_BIT)
00535
00536 #else
00537
00538 #define VS10XX_XCS_ENA()
00539 #define VS10XX_XCS_CLR()
00540 #define VS10XX_XCS_SET()
00541
00542 #endif
00543
00544 #if defined(VS10XX_XDCS_BIT)
00545
00546 #if (VS10XX_XDCS_AVRPORT == AVRPORTA)
00547 #define VS10XX_XDCS_SOD_REG PORTA
00548 #define VS10XX_XDCS_OE_REG DDRA
00549 #elif (VS10XX_XDCS_AVRPORT == AVRPORTB)
00550 #define VS10XX_XDCS_SOD_REG PORTB
00551 #define VS10XX_XDCS_OE_REG DDRB
00552 #elif (VS10XX_XDCS_AVRPORT == AVRPORTD)
00553 #define VS10XX_XDCS_SOD_REG PORTD
00554 #define VS10XX_XDCS_OE_REG DDRD
00555 #elif (VS10XX_XDCS_AVRPORT == AVRPORTE)
00556 #define VS10XX_XDCS_SOD_REG PORTE
00557 #define VS10XX_XDCS_OE_REG DDRE
00558 #elif (VS10XX_XDCS_AVRPORT == AVRPORTF)
00559 #define VS10XX_XDCS_SOD_REG PORTF
00560 #define VS10XX_XDCS_OE_REG DDRF
00561 #elif (VS10XX_XDCS_AVRPORT == AVRPORTG)
00562 #define VS10XX_XDCS_SOD_REG PORTG
00563 #define VS10XX_XDCS_OE_REG DDRG
00564 #elif (VS10XX_XDCS_AVRPORT == AVRPORTH)
00565 #define VS10XX_XDCS_SOD_REG PORTH
00566 #define VS10XX_XDCS_OE_REG DDRH
00567 #endif
00568 #define VS10XX_XDCS_ENA() sbi(VS10XX_XDCS_OE_REG, VS10XX_XDCS_BIT)
00569 #define VS10XX_XDCS_CLR() cbi(VS10XX_XDCS_SOD_REG, VS10XX_XDCS_BIT)
00570 #define VS10XX_XDCS_SET() sbi(VS10XX_XDCS_SOD_REG, VS10XX_XDCS_BIT)
00571
00572 #else
00573
00574 #define VS10XX_XDCS_ENA()
00575 #define VS10XX_XDCS_CLR()
00576 #define VS10XX_XDCS_SET()
00577
00578 #endif
00579
00580
00581 #if defined(VS10XX_BSYNC_BIT)
00582
00583 #if (VS10XX_BSYNC_AVRPORT == AVRPORTA)
00584 #define VS10XX_BSYNC_SOD_REG PORTA
00585 #define VS10XX_BSYNC_OE_REG DDRA
00586 #elif (VS10XX_BSYNC_AVRPORT == AVRPORTB)
00587 #define VS10XX_BSYNC_SOD_REG PORTB
00588 #define VS10XX_BSYNC_OE_REG DDRB
00589 #elif (VS10XX_BSYNC_AVRPORT == AVRPORTD)
00590 #define VS10XX_BSYNC_SOD_REG PORTD
00591 #define VS10XX_BSYNC_OE_REG DDRD
00592 #elif (VS10XX_BSYNC_AVRPORT == AVRPORTE)
00593 #define VS10XX_BSYNC_SOD_REG PORTE
00594 #define VS10XX_BSYNC_OE_REG DDRE
00595 #elif (VS10XX_BSYNC_AVRPORT == AVRPORTF)
00596 #define VS10XX_BSYNC_SOD_REG PORTF
00597 #define VS10XX_BSYNC_OE_REG DDRF
00598 #elif (VS10XX_BSYNC_AVRPORT == AVRPORTG)
00599 #define VS10XX_BSYNC_SOD_REG PORTG
00600 #define VS10XX_BSYNC_OE_REG DDRG
00601 #elif (VS10XX_BSYNC_AVRPORT == AVRPORTH)
00602 #define VS10XX_BSYNC_SOD_REG PORTH
00603 #define VS10XX_BSYNC_OE_REG DDRH
00604 #endif
00605 #define VS10XX_BSYNC_ENA() sbi(VS10XX_BSYNC_OE_REG, VS10XX_BSYNC_BIT)
00606 #define VS10XX_BSYNC_CLR() cbi(VS10XX_BSYNC_SOD_REG, VS10XX_BSYNC_BIT)
00607 #define VS10XX_BSYNC_SET() sbi(VS10XX_BSYNC_SOD_REG, VS10XX_BSYNC_BIT)
00608
00609 #else
00610
00611 #define VS10XX_BSYNC_ENA()
00612 #define VS10XX_BSYNC_CLR()
00613 #define VS10XX_BSYNC_SET()
00614
00615 #endif
00616
00617
00618
00619
00620
00621 #endif
00622
00623
00624 static volatile ureg_t vs_status = VS_STATUS_STOPPED;
00625 static volatile u_int vs_flush;
00626
00627
00628
00629
00630
00631
00632
00633
00634
00635 static INLINE void VsSdiPutByte(ureg_t b)
00636 {
00637 #if defined(VS10XX_BSYNC_BIT)
00638
00639 #if defined(VS10XX_SDI_SBBI0_DEVICE)
00640 ureg_t mask;
00641
00642 VS10XX_BSYNC_SET();
00643
00644 for (mask = 0x80; mask; mask >>= 1) {
00645 SBBI0_SCK_CLR();
00646 if (b & mask) {
00647 SBBI0_MOSI_SET();
00648 }
00649 else {
00650 SBBI0_MOSI_CLR();
00651 }
00652 SBBI0_SCK_SET();
00653 if (mask & 0x40) {
00654 VS10XX_BSYNC_CLR();
00655 }
00656 }
00657 SBBI0_SCK_CLR();
00658 #elif defined(VS10XX_SDI_SBBI1_DEVICE)
00659 ureg_t mask;
00660
00661 VS10XX_BSYNC_SET();
00662
00663 for (mask = 0x80; mask; mask >>= 1) {
00664 SBBI1_SCK_CLR();
00665 if (b & mask) {
00666 SBBI1_MOSI_SET();
00667 }
00668 else {
00669 SBBI1_MOSI_CLR();
00670 }
00671 SBBI1_SCK_SET();
00672 if (mask & 0x40) {
00673 VS10XX_BSYNC_CLR();
00674 }
00675 }
00676 SBBI1_SCK_CLR();
00677 #elif defined(VS10XX_SDI_SBBI2_DEVICE)
00678 ureg_t mask;
00679
00680 VS10XX_BSYNC_SET();
00681
00682 for (mask = 0x80; mask; mask >>= 1) {
00683 SBBI2_SCK_CLR();
00684 if (b & mask) {
00685 SBBI2_MOSI_SET();
00686 }
00687 else {
00688 SBBI2_MOSI_CLR();
00689 }
00690 SBBI2_SCK_SET();
00691 if (mask & 0x40) {
00692 VS10XX_BSYNC_CLR();
00693 }
00694 }
00695 SBBI2_SCK_CLR();
00696 #elif defined(VS10XX_SDI_SBBI3_DEVICE)
00697 ureg_t mask;
00698
00699 VS10XX_BSYNC_SET();
00700
00701 for (mask = 0x80; mask; mask >>= 1) {
00702 SBBI3_SCK_CLR();
00703 if (b & mask) {
00704 SBBI3_MOSI_SET();
00705 }
00706 else {
00707 SBBI3_MOSI_CLR();
00708 }
00709 SBBI3_SCK_SET();
00710 if (mask & 0x40) {
00711 VS10XX_BSYNC_CLR();
00712 }
00713 }
00714 SBBI3_SCK_CLR();
00715 #elif defined(VS10XX_SDI_SPI0_DEVICE)
00716 VS10XX_BSYNC_SET();
00717
00718 outb(SPDR, b);
00719
00720 _NOP();
00721 _NOP();
00722 _NOP();
00723 _NOP();
00724 VS10XX_BSYNC_CLR();
00725
00726
00727 loop_until_bit_is_set(SPSR, SPIF);
00728 #endif
00729
00730 #else
00731
00732 SdiByte(b);
00733
00734 #endif
00735
00736 }
00737
00749 ureg_t VsPlayerInterrupts(ureg_t enable)
00750 {
00751 static ureg_t is_enabled = 0;
00752 ureg_t rc;
00753
00754 rc = is_enabled;
00755 if(enable) {
00756 VS10XX_DREQ_ENA();
00757 NutIrqEnable(&VS10XX_SIGNAL);
00758 }
00759 else {
00760 NutIrqDisable(&VS10XX_SIGNAL);
00761 }
00762 is_enabled = enable;
00763
00764 return rc;
00765 }
00766
00791 ureg_t VsPlayerThrottle(ureg_t on)
00792 {
00793 static ureg_t is_throttled = 0;
00794 ureg_t rc;
00795
00796 rc = is_throttled;
00797 if(on) {
00798 VS10XX_XDCS_SET();
00799 SdiDeselect();
00800 }
00801 else {
00802 VS10XX_XDCS_CLR();
00803 SdiSelect();
00804 }
00805 is_throttled = on;
00806
00807 return rc;
00808 }
00809
00813 static void VsSciSelect(ureg_t on)
00814 {
00815 if (on) {
00816
00817 SdiDeselect();
00818
00819 #if defined(VS10XX_SDI_SPI0_DEVICE) && !defined(VS10XX_SCI_SPI0_DEVICE)
00820
00821
00822
00823 cbi(SPCR, SPE);
00824 #endif
00825
00826
00827 VS10XX_XDCS_SET();
00828
00829 VS10XX_XCS_CLR();
00830
00831 SciSelect();
00832 }
00833 else {
00834
00835 SciDeselect();
00836
00837 VS10XX_XCS_SET();
00838
00839 VS10XX_XDCS_CLR();
00840
00841 SdiSelect();
00842 }
00843 }
00844
00851 static int VsWaitReady(void)
00852 {
00853 int tmo;
00854
00855 for (tmo = 0; tmo < 5000; tmo++) {
00856 if (VS10XX_DREQ_TST()) {
00857 return 0;
00858 }
00859 }
00860 return -1;
00861 }
00862
00863
00864
00865
00866
00867
00868
00869 static int VsSdiWrite(CONST uint8_t * data, size_t len)
00870 {
00871 while (len--) {
00872 if (!VS10XX_DREQ_TST() && VsWaitReady()) {
00873 return -1;
00874 }
00875 VsSdiPutByte(*data);
00876 data++;
00877 }
00878 return 0;
00879 }
00880
00881
00882
00883
00884
00885
00886
00887
00888 static int VsSdiWrite_P(PGM_P data, size_t len)
00889 {
00890 while (len--) {
00891 if (!VS10XX_DREQ_TST() && VsWaitReady()) {
00892 return -1;
00893 }
00894 VsSdiPutByte(PRG_RDB(data));
00895 data++;
00896 }
00897 return 0;
00898 }
00899
00900
00901
00902
00903
00904
00905 static void VsRegWrite(ureg_t reg, uint16_t data)
00906 {
00907
00908 VsWaitReady();
00909 VsSciSelect(1);
00910
00911
00912
00913
00914
00915
00916 SciByte(VS_OPCODE_WRITE);
00917 SciByte((uint8_t) reg);
00918 SciByte((uint8_t) (data >> 8));
00919 SciByte((uint8_t) data);
00920
00921
00922 VsSciSelect(0);
00923 }
00924
00925
00926
00927
00928
00929
00930
00931
00932 static uint16_t VsRegRead(ureg_t reg)
00933 {
00934 uint16_t data;
00935
00936
00937 VsWaitReady();
00938 VsSciSelect(1);
00939
00940 SciByte(VS_OPCODE_READ);
00941 SciByte((uint8_t) reg);
00942 data = (uint16_t)SciByte(0) << 8;
00943 data |= SciByte(0);
00944
00945
00946 VsSciSelect(0);
00947
00948 return data;
00949 }
00950
00951
00952
00953
00954
00955
00956
00957
00958 static void VsPlayerFeed(void *arg)
00959 {
00960 ureg_t j = 32;
00961 size_t total = 0;
00962
00963 if (!VS10XX_DREQ_TST()) {
00964 return;
00965 }
00966
00967
00968
00969
00970 if (vs_status == VS_STATUS_RUNNING) {
00971 char *bp = 0;
00972 size_t consumed = 0;
00973 size_t available = 0;
00974 do {
00975 if(consumed >= available) {
00976
00977 if(consumed) {
00978 NutSegBufReadCommit(consumed);
00979 consumed = 0;
00980 }
00981
00982 bp = NutSegBufReadRequest(&available);
00983 if(available == 0) {
00984
00985 vs_status = VS_STATUS_EOF;
00986 break;
00987 }
00988 }
00989
00990 VsSdiPutByte(*bp);
00991 bp++;
00992 consumed++;
00993 total++;
00994 if (total > 4096) {
00995 vs_status = VS_STATUS_EOF;
00996 break;
00997 }
00998
00999
01000
01001 if (VS10XX_DREQ_TST()) {
01002 j = 32;
01003 }
01004 } while(j--);
01005
01006
01007 NutSegBufReadLast(consumed);
01008 }
01009
01010
01011
01012
01013 if(vs_status != VS_STATUS_RUNNING && vs_flush) {
01014 do {
01015 VsSdiPutByte(0);
01016 if (--vs_flush == 0) {
01017
01018 vs_status = VS_STATUS_EMPTY;
01019 break;
01020 }
01021
01022
01023 if (VS10XX_DREQ_TST()) {
01024 j = 32;
01025 }
01026 } while(j--);
01027 }
01028 }
01029
01041 int VsPlayerKick(void)
01042 {
01043
01044
01045
01046 VsPlayerInterrupts(0);
01047 vs_status = VS_STATUS_RUNNING;
01048 VsPlayerFeed(NULL);
01049 VsPlayerInterrupts(1);
01050
01051 return 0;
01052 }
01053
01062 int VsPlayerStop(void)
01063 {
01064 ureg_t ief;
01065
01066 ief = VsPlayerInterrupts(0);
01067
01068 if (vs_status == VS_STATUS_RUNNING) {
01069 vs_status = VS_STATUS_STOPPED;
01070 }
01071 VsPlayerInterrupts(ief);
01072
01073 return 0;
01074 }
01075
01076
01089 int VsPlayerFlush(void)
01090 {
01091 VsPlayerInterrupts(0);
01092
01093 if (vs_status != VS_STATUS_EMPTY || NutSegBufUsed()) {
01094 if (vs_flush == 0) {
01095 vs_flush = VS_FLUSH_BYTES;
01096 }
01097
01098 if (vs_status != VS_STATUS_RUNNING) {
01099 VsPlayerKick();
01100 }
01101 }
01102 VsPlayerInterrupts(1);
01103
01104 return 0;
01105 }
01106
01112 int VsPlayerInit(void)
01113 {
01114
01115 VsPlayerInterrupts(0);
01116
01117
01118 SciReset(1);
01119
01120
01121 if (SciSetMode()) {
01122 return -1;
01123 }
01124 SciSetSpeed();
01125 SciDeselect();
01126
01127
01128 if (SdiSetMode()) {
01129 return -1;
01130 }
01131 SdiSetSpeed();
01132 SdiDeselect();
01133
01134
01135 VS10XX_BSYNC_CLR();
01136 VS10XX_BSYNC_ENA();
01137
01138
01139 VS10XX_XDCS_SET();
01140 VS10XX_XDCS_ENA();
01141
01142
01143 VS10XX_XCS_SET();
01144 VS10XX_XCS_ENA();
01145
01146
01147 VS10XX_DREQ_ENA();
01148
01149
01150 if (NutRegisterIrqHandler(&VS10XX_SIGNAL, VsPlayerFeed, NULL)) {
01151 return -1;
01152 }
01153
01154
01155 NutIrqSetMode(&VS10XX_SIGNAL, NUT_IRQMODE_RISINGEDGE);
01156
01157
01158 SciReset(0);
01159 NutDelay(VS10XX_HWRST_RECOVER);
01160
01161 return VsPlayerReset(0);
01162 }
01163
01190 int VsPlayerReset(uint16_t mode)
01191 {
01192
01193 VsPlayerInterrupts(0);
01194 vs_status = VS_STATUS_STOPPED;
01195
01196
01197 #if defined(VS10XX_BSYNC_BIT)
01198 VsRegWrite(VS_MODE_REG, VS_SM_RESET | mode);
01199 #else
01200 VsRegWrite(VS_MODE_REG, VS_SM_RESET | VS_SM_SDINEW | mode);
01201 #endif
01202
01203 NutDelay(VS10XX_SWRST_RECOVER);
01204
01205
01206
01207
01208 if ((mode & VS_SM_RESET) != 0 || !VS10XX_DREQ_TST()) {
01209
01210 SciReset(1);
01211
01212 NutDelay(VS10XX_HWRST_DURATION);
01213 SciReset(0);
01214
01215 NutDelay(VS10XX_HWRST_RECOVER);
01216
01217
01218 #if defined(VS10XX_BSYNC_BIT)
01219 VsRegWrite(VS_MODE_REG, VS_SM_RESET | mode);
01220 #else
01221 VsRegWrite(VS_MODE_REG, VS_SM_RESET | VS_SM_SDINEW | mode);
01222 #endif
01223 NutDelay(VS10XX_SWRST_RECOVER);
01224 if (!VS10XX_DREQ_TST()) {
01225 return -1;
01226 }
01227 }
01228
01229 #if VS10XX_FREQ < 20000000UL
01230 VsRegWrite(VS_CLOCKF_REG, (uint16_t)(VS_CF_DOUBLER | (VS10XX_FREQ / 2000UL)));
01231 #else
01232 VsRegWrite(VS_CLOCKF_REG, (uint16_t)(VS10XX_FREQ / 2000UL));
01233 #endif
01234 #if defined(AUDIO_VS1001K)
01235
01236 xVsRegWrite(VS_INT_FCTLH_REG, 0x8008);
01237 #endif
01238 NutDelay(1);
01239
01240 #if defined(VS10XX_SDI_SPI0_DEVICE) || defined(VS10XX_SCI_SPI0_DEVICE)
01241
01242 outb(EIFR, BV(VS10XX_DREQ_BIT));
01243 #endif
01244
01245 return 0;
01246 }
01247
01271 int VsPlayerSetMode(uint16_t mode)
01272 {
01273 ureg_t ief;
01274
01275 ief = VsPlayerInterrupts(0);
01276 #if defined(VS10XX_BSYNC_BIT)
01277 VsRegWrite(VS_MODE_REG, mode);
01278 #else
01279 VsRegWrite(VS_MODE_REG, VS_SM_SDINEW | mode);
01280 #endif
01281 VsPlayerInterrupts(ief);
01282
01283 return 0;
01284 }
01285
01291 uint16_t VsPlayTime(void)
01292 {
01293 uint16_t rc;
01294 ureg_t ief;
01295
01296 ief = VsPlayerInterrupts(0);
01297 rc = VsRegRead(VS_DECODE_TIME_REG);
01298 VsPlayerInterrupts(ief);
01299
01300 return rc;
01301 }
01302
01312 u_int VsGetStatus(void)
01313 {
01314 return vs_status;
01315 }
01316
01317 #ifdef __GNUC__
01318
01326 int VsGetHeaderInfo(VS_HEADERINFO * vshi)
01327 {
01328 uint16_t *usp = (uint16_t *) vshi;
01329 ureg_t ief;
01330
01331 ief = VsPlayerInterrupts(0);
01332 *usp = VsRegRead(VS_HDAT1_REG);
01333 *++usp = VsRegRead(VS_HDAT0_REG);
01334 VsPlayerInterrupts(ief);
01335
01336 return 0;
01337 }
01338 #endif
01339
01352 uint16_t VsMemoryTest(void)
01353 {
01354 uint16_t rc;
01355 ureg_t ief;
01356 static prog_char mtcmd[] = { 0x4D, 0xEA, 0x6D, 0x54, 0x00, 0x00, 0x00, 0x00 };
01357
01358 ief = VsPlayerInterrupts(0);
01359 #if defined(VS10XX_BSYNC_BIT)
01360 VsRegWrite(VS_MODE_REG, VS_SM_TESTS);
01361 #else
01362 VsRegWrite(VS_MODE_REG, VS_SM_TESTS | VS_SM_SDINEW);
01363 #endif
01364 VsSdiWrite_P(mtcmd, sizeof(mtcmd));
01365 while(((rc = VsRegRead(VS_HDAT0_REG)) & 0x8000) == 0) {
01366 NutDelay(1);
01367 }
01368 #if defined(VS10XX_BSYNC_BIT)
01369 VsRegWrite(VS_MODE_REG, 0);
01370 #else
01371 VsRegWrite(VS_MODE_REG, VS_SM_SDINEW);
01372 #endif
01373 VsPlayerInterrupts(ief);
01374
01375 return rc;
01376 }
01377
01387 int VsSetVolume(ureg_t left, ureg_t right)
01388 {
01389 ureg_t ief;
01390
01391 ief = VsPlayerInterrupts(0);
01392 VsRegWrite(VS_VOL_REG, ((uint16_t)left << VS_VOL_LEFT_LSB) | ((uint16_t)right << VS_VOL_RIGHT_LSB));
01393 VsPlayerInterrupts(ief);
01394
01395 return 0;
01396 }
01397
01406 int VsBeep(uint8_t fsin, uint8_t ms)
01407 {
01408 ureg_t ief;
01409 static prog_char on[] = { 0x53, 0xEF, 0x6E };
01410 static prog_char off[] = { 0x45, 0x78, 0x69, 0x74 };
01411 static prog_char end[] = { 0x00, 0x00, 0x00, 0x00 };
01412
01413
01414 ief = VsPlayerInterrupts(0);
01415
01416 #if defined(VS10XX_BSYNC_BIT)
01417 VsRegWrite(VS_MODE_REG, VS_SM_TESTS);
01418 #else
01419 VsRegWrite(VS_MODE_REG, VS_SM_TESTS | VS_SM_SDINEW);
01420 #endif
01421
01422 fsin = 56 + (fsin & 7) * 9;
01423 VsSdiWrite_P(on, sizeof(on));
01424 VsSdiWrite(&fsin, 1);
01425 VsSdiWrite_P(end, sizeof(end));
01426 NutDelay(ms);
01427 VsSdiWrite_P(off, sizeof(off));
01428 VsSdiWrite_P(end, sizeof(end));
01429
01430 #if defined(VS10XX_BSYNC_BIT)
01431 VsRegWrite(VS_MODE_REG, 0);
01432 #else
01433 VsRegWrite(VS_MODE_REG, VS_SM_SDINEW);
01434 #endif
01435
01436
01437 VsPlayerInterrupts(ief);
01438
01439 return 0;
01440 }
01441
01442