ih_timer1_capt.c

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00001 /*
00002  * Copyright (C) 2001-2005 by egnite Software GmbH. All rights reserved.
00003  *
00004  * Redistribution and use in source and binary forms, with or without
00005  * modification, are permitted provided that the following conditions
00006  * are met:
00007  *
00008  * 1. Redistributions of source code must retain the above copyright
00009  *    notice, this list of conditions and the following disclaimer.
00010  * 2. Redistributions in binary form must reproduce the above copyright
00011  *    notice, this list of conditions and the following disclaimer in the
00012  *    documentation and/or other materials provided with the distribution.
00013  * 3. Neither the name of the copyright holders nor the names of
00014  *    contributors may be used to endorse or promote products derived
00015  *    from this software without specific prior written permission.
00016  *
00017  * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
00018  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00019  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00020  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
00021  * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
00022  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
00023  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
00024  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
00025  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00026  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
00027  * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
00028  * SUCH DAMAGE.
00029  *
00030  * For additional information see http://www.ethernut.de/
00031  *
00032  */
00033 
00080 #include <dev/irqreg.h>
00081 
00082 #if defined(MCU_AT90CAN128) || defined(MCU_ATMEGA2560) || defined(MCU_ATMEGA2561)
00083 #define INT_MASK_REG    TIMSK1
00084 #define INT_STATUS_REG  TIFR1
00085 #define INT_ENABLE_BIT  ICIE1
00086 #define INT_STATUS_BIT  ICF1
00087 #define INT_PRIORITY    10
00088 #else
00089 #define INT_MASK_REG    TIMSK
00090 #define INT_STATUS_REG  TIFR
00091 #define INT_ENABLE_BIT  TICIE1
00092 #define INT_STATUS_BIT  ICF1
00093 #define INT_PRIORITY    10
00094 #endif
00095 
00100 
00101 static int AvrTimer1CaptIrqCtl(int cmd, void *param);
00102 
00103 IRQ_HANDLER sig_INPUT_CAPTURE1 = {
00104 #ifdef NUT_PERFMON
00105     0,                          /* Interrupt counter, ir_count. */
00106 #endif
00107     NULL,                       /* Passed argument, ir_arg. */
00108     NULL,                       /* Handler subroutine, ir_handler. */
00109     AvrTimer1CaptIrqCtl         /* Interrupt control, ir_ctl. */
00110 };
00111 
00127 static int AvrTimer1CaptIrqCtl(int cmd, void *param)
00128 {
00129     int rc = 0;
00130     u_int *ival = (u_int *) param;
00131     int_fast8_t enabled = bit_is_set(INT_MASK_REG, INT_ENABLE_BIT);
00132 
00133     /* Disable interrupt. */
00134     cbi(INT_MASK_REG, INT_ENABLE_BIT);
00135 
00136     switch (cmd) {
00137     case NUT_IRQCTL_INIT:
00138         enabled = 0;
00139     case NUT_IRQCTL_CLEAR:
00140         /* Clear any pending interrupt. */
00141         outb(INT_STATUS_REG, _BV(INT_STATUS_BIT));
00142         break;
00143     case NUT_IRQCTL_STATUS:
00144         if (bit_is_set(INT_STATUS_REG, INT_STATUS_BIT)) {
00145             *ival = 1;
00146         } else {
00147             *ival = 0;
00148         }
00149         if (enabled) {
00150             *ival |= 0x80;
00151         }
00152         break;
00153     case NUT_IRQCTL_ENABLE:
00154         enabled = 1;
00155         break;
00156     case NUT_IRQCTL_DISABLE:
00157         enabled = 0;
00158         break;
00159     case NUT_IRQCTL_GETPRIO:
00160         *ival = INT_PRIORITY;
00161         break;
00162 #ifdef NUT_PERFMON
00163     case NUT_IRQCTL_GETCOUNT:
00164         *ival = (u_int) sig_INPUT_CAPTURE1.ir_count;
00165         sig_INPUT_CAPTURE1.ir_count = 0;
00166         break;
00167 #endif
00168     default:
00169         rc = -1;
00170         break;
00171     }
00172 
00173     /* Enable interrupt. */
00174     if (enabled) {
00175         sbi(INT_MASK_REG, INT_ENABLE_BIT);
00176     }
00177     return rc;
00178 }
00179 
00183 #ifdef __IMAGECRAFT__
00184 #pragma interrupt_handler SIG_INPUT_CAPTURE1:iv_TIMER1_CAPT
00185 #endif
00186 NUTSIGNAL(SIG_INPUT_CAPTURE1, sig_INPUT_CAPTURE1)
00187 
00188 
00189 

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