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00053 #include <cfg/arch/avr.h>
00054 #include <cfg/audio.h>
00055
00056 #include <sys/atom.h>
00057 #include <sys/event.h>
00058 #include <sys/timer.h>
00059 #include <sys/heap.h>
00060
00061 #include <dev/irqreg.h>
00062 #include <dev/vs10xx.h>
00063
00064 #include <sys/bankmem.h>
00065
00066 #include <stddef.h>
00067
00072
00073 #if !defined(AUDIO_VS1001K) && !defined(AUDIO_VS1011E) && !defined(AUDIO_VS1002D) && !defined(AUDIO_VS1003B) && !defined(AUDIO_VS1033C)
00074 #define AUDIO_VS1001K
00075 #endif
00076
00077 #ifndef VS10XX_FREQ
00078
00079 #define VS10XX_FREQ 12288000UL
00080 #endif
00081
00082 #ifndef VS10XX_HWRST_DURATION
00083
00084 #define VS10XX_HWRST_DURATION 1
00085 #endif
00086
00087 #ifndef VS10XX_HWRST_RECOVER
00088
00089 #define VS10XX_HWRST_RECOVER 4
00090 #endif
00091
00092 #ifndef VS10XX_SWRST_RECOVER
00093
00094 #define VS10XX_SWRST_RECOVER 2
00095 #endif
00096
00097 #ifndef VS10XX_SCI_MODE
00098 #define VS10XX_SCI_MODE 0
00099 #endif
00100
00101 #ifndef VS10XX_SCI_RATE
00102 #define VS10XX_SCI_RATE (VS10XX_FREQ / 4)
00103 #endif
00104
00105 #ifndef VS10XX_SDI_MODE
00106 #define VS10XX_SDI_MODE 0
00107 #endif
00108
00109 #ifndef VS10XX_SDI_RATE
00110 #define VS10XX_SDI_RATE (VS10XX_FREQ / 4)
00111 #endif
00112
00113 #if defined(VS10XX_SCI_SPI0_DEVICE)
00114
00115 #include <dev/sppif0.h>
00116 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00117 #define SciReset(act) Sppi0ChipReset(VS10XX_SCI_SPI0_DEVICE, act)
00118 #else
00119 #define SciReset(act) Sppi0ChipReset(VS10XX_SCI_SPI0_DEVICE, !act)
00120 #endif
00121 #define SciSetMode() Sppi0SetMode(VS10XX_SCI_SPI0_DEVICE, VS10XX_SCI_MODE)
00122 #define SciSetSpeed() Sppi0SetSpeed(VS10XX_SCI_SPI0_DEVICE, VS10XX_SCI_RATE)
00123 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00124 #define SciSelect() Sppi0SelectDevice(VS10XX_SCI_SPI0_DEVICE)
00125 #define SciDeselect() Sppi0DeselectDevice(VS10XX_SCI_SPI0_DEVICE)
00126 #else
00127 #define SciSelect() Sppi0NegSelectDevice(VS10XX_SCI_SPI0_DEVICE)
00128 #define SciDeselect() Sppi0NegDeselectDevice(VS10XX_SCI_SPI0_DEVICE)
00129 #endif
00130 #define SciByte(b) Sppi0Byte(b)
00131
00132 #elif defined(VS10XX_SCI_SBBI0_DEVICE)
00133
00134 #include <dev/sbbif0.h>
00135 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00136 #define SciReset(act) Sbbi0ChipReset(VS10XX_SCI_SBBI0_DEVICE, act)
00137 #else
00138 #define SciReset(act) Sbbi0ChipReset(VS10XX_SCI_SBBI0_DEVICE, !act)
00139 #endif
00140 #define SciSetMode() Sbbi0SetMode(VS10XX_SCI_SBBI0_DEVICE, VS10XX_SCI_MODE)
00141 #define SciSetSpeed() Sbbi0SetSpeed(VS10XX_SCI_SBBI0_DEVICE, VS10XX_SCI_RATE)
00142 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00143 #define SciSelect() Sbbi0SelectDevice(VS10XX_SCI_SBBI0_DEVICE)
00144 #define SciDeselect() Sbbi0DeselectDevice(VS10XX_SCI_SBBI0_DEVICE)
00145 #else
00146 #define SciSelect() Sbbi0NegSelectDevice(VS10XX_SCI_SBBI0_DEVICE)
00147 #define SciDeselect() Sbbi0NegDeselectDevice(VS10XX_SCI_SBBI0_DEVICE)
00148 #endif
00149 #define SciByte(b) Sbbi0Byte(b)
00150
00151 #elif defined(VS10XX_SCI_SBBI1_DEVICE)
00152
00153 #include <dev/sbbif1.h>
00154 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00155 #define SciReset(act) Sbbi1ChipReset(VS10XX_SCI_SBBI1_DEVICE, act)
00156 #else
00157 #define SciReset(act) Sbbi1ChipReset(VS10XX_SCI_SBBI1_DEVICE, !act)
00158 #endif
00159 #define SciSetMode() Sbbi1SetMode(VS10XX_SCI_SBBI1_DEVICE, VS10XX_SCI_MODE)
00160 #define SciSetSpeed() Sbbi1SetSpeed(VS10XX_SCI_SBBI1_DEVICE, VS10XX_SCI_RATE)
00161 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00162 #define SciSelect() Sbbi1SelectDevice(VS10XX_SCI_SBBI1_DEVICE)
00163 #define SciDeselect() Sbbi1DeselectDevice(VS10XX_SCI_SBBI1_DEVICE)
00164 #else
00165 #define SciSelect() Sbbi1NegSelectDevice(VS10XX_SCI_SBBI1_DEVICE)
00166 #define SciDeselect() Sbbi1NegDeselectDevice(VS10XX_SCI_SBBI1_DEVICE)
00167 #endif
00168 #define SciByte(b) Sbbi1Byte(b)
00169
00170 #elif defined(VS10XX_SCI_SBBI2_DEVICE)
00171
00172 #include <dev/sbbif2.h>
00173 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00174 #define SciReset(act) Sbbi2ChipReset(VS10XX_SCI_SBBI2_DEVICE, act)
00175 #else
00176 #define SciReset(act) Sbbi2ChipReset(VS10XX_SCI_SBBI2_DEVICE, !act)
00177 #endif
00178 #define SciSetMode() Sbbi2SetMode(VS10XX_SCI_SBBI2_DEVICE, VS10XX_SCI_MODE)
00179 #define SciSetSpeed() Sbbi2SetSpeed(VS10XX_SCI_SBBI2_DEVICE, VS10XX_SCI_RATE)
00180 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00181 #define SciSelect() Sbbi2SelectDevice(VS10XX_SCI_SBBI2_DEVICE)
00182 #define SciDeselect() Sbbi2DeselectDevice(VS10XX_SCI_SBBI2_DEVICE)
00183 #else
00184 #define SciSelect() Sbbi2NegSelectDevice(VS10XX_SCI_SBBI2_DEVICE)
00185 #define SciDeselect() Sbbi2NegDeselectDevice(VS10XX_SCI_SBBI2_DEVICE)
00186 #endif
00187 #define SciByte(b) Sbbi2Byte(b)
00188
00189 #elif defined(VS10XX_SCI_SBBI3_DEVICE)
00190
00191 #include <dev/sbbif3.h>
00192 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00193 #define SciReset(act) Sbbi3ChipReset(VS10XX_SCI_SBBI3_DEVICE, act)
00194 #else
00195 #define SciReset(act) Sbbi3ChipReset(VS10XX_SCI_SBBI3_DEVICE, !act)
00196 #endif
00197 #define SciSetMode() Sbbi3SetMode(VS10XX_SCI_SBBI3_DEVICE, VS10XX_SCI_MODE)
00198 #define SciSetSpeed() Sbbi3SetSpeed(VS10XX_SCI_SBBI3_DEVICE, VS10XX_SCI_RATE)
00199 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00200 #define SciSelect() Sbbi3SelectDevice(VS10XX_SCI_SBBI3_DEVICE)
00201 #define SciDeselect() Sbbi3DeselectDevice(VS10XX_SCI_SBBI3_DEVICE)
00202 #else
00203 #define SciSelect() Sbbi3NegSelectDevice(VS10XX_SCI_SBBI3_DEVICE)
00204 #define SciDeselect() Sbbi3NegDeselectDevice(VS10XX_SCI_SBBI3_DEVICE)
00205 #endif
00206 #define SciByte(b) Sbbi3Byte(b)
00207
00208 #else
00209
00210 #define SciReset(act)
00211 #define SciSetMode() (-1)
00212 #define SciSetSpeed()
00213 #define SciSelect()
00214 #define SciDeselect()
00215 #define SciByte(b) 0
00216
00217 #endif
00218
00219
00220 #if defined(VS10XX_SDI_SPI0_DEVICE)
00221
00222 #include <dev/sppif0.h>
00223 #define SdiSetMode() Sppi0SetMode(VS10XX_SDI_SPI0_DEVICE, VS10XX_SDI_MODE)
00224 #define SdiSetSpeed() Sppi0SetSpeed(VS10XX_SDI_SPI0_DEVICE, VS10XX_SDI_RATE)
00225 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00226 #define SdiSelect() Sppi0SelectDevice(VS10XX_SDI_SPI0_DEVICE)
00227 #define SdiDeselect() Sppi0DeselectDevice(VS10XX_SDI_SPI0_DEVICE)
00228 #else
00229 #define SdiSelect() Sppi0NegSelectDevice(VS10XX_SDI_SPI0_DEVICE)
00230 #define SdiDeselect() Sppi0NegDeselectDevice(VS10XX_SDI_SPI0_DEVICE)
00231 #endif
00232 #define SdiByte(b) Sppi0Byte(b)
00233
00234 #elif defined(VS10XX_SDI_SBBI0_DEVICE)
00235
00236 #include <dev/sbbif0.h>
00237 #define SdiSetMode() Sbbi0SetMode(VS10XX_SDI_SBBI0_DEVICE, VS10XX_SDI_MODE)
00238 #define SdiSetSpeed() Sbbi0SetSpeed(VS10XX_SDI_SBBI0_DEVICE, VS10XX_SDI_RATE)
00239 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00240 #define SdiSelect() Sbbi0SelectDevice(VS10XX_SDI_SBBI0_DEVICE)
00241 #define SdiDeselect() Sbbi0DeselectDevice(VS10XX_SDI_SBBI0_DEVICE)
00242 #else
00243 #define SdiSelect() Sbbi0NegSelectDevice(VS10XX_SDI_SBBI0_DEVICE)
00244 #define SdiDeselect() Sbbi0NegDeselectDevice(VS10XX_SDI_SBBI0_DEVICE)
00245 #endif
00246 #define SdiByte(b) Sbbi0Byte(b)
00247
00248 #elif defined(VS10XX_SDI_SBBI1_DEVICE)
00249
00250 #include <dev/sbbif1.h>
00251 #define SdiSetMode() Sbbi1SetMode(VS10XX_SDI_SBBI1_DEVICE, VS10XX_SDI_MODE)
00252 #define SdiSetSpeed() Sbbi1SetSpeed(VS10XX_SDI_SBBI1_DEVICE, VS10XX_SDI_RATE)
00253 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00254 #define SdiSelect() Sbbi1SelectDevice(VS10XX_SDI_SBBI1_DEVICE)
00255 #define SdiDeselect() Sbbi1DeselectDevice(VS10XX_SDI_SBBI1_DEVICE)
00256 #else
00257 #define SdiSelect() Sbbi1NegSelectDevice(VS10XX_SDI_SBBI1_DEVICE)
00258 #define SdiDeselect() Sbbi1NegDeselectDevice(VS10XX_SDI_SBBI1_DEVICE)
00259 #endif
00260 #define SdiByte(b) Sbbi1Byte(b)
00261
00262 #elif defined(VS10XX_SDI_SBBI2_DEVICE)
00263
00264 #include <dev/sbbif2.h>
00265 #define SdiSetMode() Sbbi2SetMode(VS10XX_SDI_SBBI2_DEVICE, VS10XX_SDI_MODE)
00266 #define SdiSetSpeed() Sbbi2SetSpeed(VS10XX_SDI_SBBI2_DEVICE, VS10XX_SDI_RATE)
00267 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00268 #define SdiSelect() Sbbi2SelectDevice(VS10XX_SDI_SBBI2_DEVICE)
00269 #define SdiDeselect() Sbbi2DeselectDevice(VS10XX_SDI_SBBI2_DEVICE)
00270 #else
00271 #define SdiSelect() Sbbi2NegSelectDevice(VS10XX_SDI_SBBI2_DEVICE)
00272 #define SdiDeselect() Sbbi2NegDeselectDevice(VS10XX_SDI_SBBI2_DEVICE)
00273 #endif
00274 #define SdiByte(b) Sbbi2Byte(b)
00275
00276 #elif defined(VS10XX_SDI_SBBI3_DEVICE)
00277
00278 #include <dev/sbbif3.h>
00279 #define SdiSetMode() Sbbi3SetMode(VS10XX_SDI_SBBI3_DEVICE, VS10XX_SDI_MODE)
00280 #define SdiSetSpeed() Sbbi3SetSpeed(VS10XX_SDI_SBBI3_DEVICE, VS10XX_SDI_RATE)
00281 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00282 #define SdiSelect() Sbbi3SelectDevice(VS10XX_SDI_SBBI3_DEVICE)
00283 #define SdiDeselect() Sbbi3DeselectDevice(VS10XX_SDI_SBBI3_DEVICE)
00284 #else
00285 #define SdiSelect() Sbbi3NegSelectDevice(VS10XX_SDI_SBBI3_DEVICE)
00286 #define SdiDeselect() Sbbi3NegDeselectDevice(VS10XX_SDI_SBBI3_DEVICE)
00287 #endif
00288 #define SdiByte(b) Sbbi3Byte(b)
00289
00290 #else
00291
00292 #define SdiSetMode() (-1)
00293 #define SdiSetSpeed()
00294 #define SdiSelect()
00295 #define SdiDeselect()
00296 #define SdiByte(b) 0
00297
00298 #endif
00299
00300
00301
00302
00303 #if MCU_AT91
00304
00305 #if (VS10XX_SIGNAL_IRQ == INT0)
00306 #define VS10XX_SIGNAL sig_INTERRUPT0
00307 #elif (VS10XX_SIGNAL_IRQ == INT1)
00308 #define VS10XX_SIGNAL sig_INTERRUPT1
00309 #elif (VS10XX_SIGNAL_IRQ == INT2)
00310 #define VS10XX_SIGNAL sig_INTERRUPT2
00311 #endif
00312
00313 #if defined(VS10XX_XCS_BIT)
00314
00315 #if !defined(VS10XX_XCS_PORT)
00316 #define VS10XX_XCS_PE_REG PIO_PER
00317 #define VS10XX_XCS_OE_REG PIO_OER
00318 #define VS10XX_XCS_COD_REG PIO_CODR
00319 #define VS10XX_XCS_SOD_REG PIO_SODR
00320 #elif VS10XX_XCS_PORT == PIOA_ID
00321 #define VS10XX_XCS_PE_REG PIOA_PER
00322 #define VS10XX_XCS_OE_REG PIOA_OER
00323 #define VS10XX_XCS_COD_REG PIOA_CODR
00324 #define VS10XX_XCS_SOD_REG PIOA_SODR
00325 #elif VS10XX_XCS_PORT == PIOB_ID
00326 #define VS10XX_XCS_PE_REG PIOB_PER
00327 #define VS10XX_XCS_OE_REG PIOB_OER
00328 #define VS10XX_XCS_COD_REG PIOB_CODR
00329 #define VS10XX_XCS_SOD_REG PIOB_SODR
00330 #elif VS10XX_XCS_PORT == PIOC_ID
00331 #define VS10XX_XCS_PE_REG PIOC_PER
00332 #define VS10XX_XCS_OE_REG PIOC_OER
00333 #define VS10XX_XCS_COD_REG PIOC_CODR
00334 #define VS10XX_XCS_SOD_REG PIOC_SODR
00335 #endif
00336 #define VS10XX_XCS_ENA() \
00337 outr(VS10XX_XCS_PE_REG, _BV(VS10XX_XCS_BIT)); \
00338 outr(VS10XX_XCS_OE_REG, _BV(VS10XX_XCS_BIT))
00339 #define VS10XX_XCS_CLR() outr(VS10XX_XCS_COD_REG, _BV(VS10XX_XCS_BIT))
00340 #define VS10XX_XCS_SET() outr(VS10XX_XCS_SOD_REG, _BV(VS10XX_XCS_BIT))
00341
00342 #else
00343
00344 #define VS10XX_XCS_ENA()
00345 #define VS10XX_XCS_CLR()
00346 #define VS10XX_XCS_SET()
00347
00348 #endif
00349
00350 #if defined(VS10XX_XDCS_BIT)
00351
00352 #if !defined(VS10XX_XDCS_PORT)
00353 #define VS10XX_XDCS_PE_REG PIO_PER
00354 #define VS10XX_XDCS_OE_REG PIO_OER
00355 #define VS10XX_XDCS_COD_REG PIO_CODR
00356 #define VS10XX_XDCS_SOD_REG PIO_SODR
00357 #elif VS10XX_XDCS_PORT == PIOA_ID
00358 #define VS10XX_XDCS_PE_REG PIOA_PER
00359 #define VS10XX_XDCS_OE_REG PIOA_OER
00360 #define VS10XX_XDCS_COD_REG PIOA_CODR
00361 #define VS10XX_XDCS_SOD_REG PIOA_SODR
00362 #elif VS10XX_XDCS_PORT == PIOB_ID
00363 #define VS10XX_XDCS_PE_REG PIOB_PER
00364 #define VS10XX_XDCS_OE_REG PIOB_OER
00365 #define VS10XX_XDCS_COD_REG PIOB_CODR
00366 #define VS10XX_XDCS_SOD_REG PIOB_SODR
00367 #elif VS10XX_XDCS_PORT == PIOC_ID
00368 #define VS10XX_XDCS_PE_REG PIOC_PER
00369 #define VS10XX_XDCS_OE_REG PIOC_OER
00370 #define VS10XX_XDCS_COD_REG PIOC_CODR
00371 #define VS10XX_XDCS_SOD_REG PIOC_SODR
00372 #endif
00373 #define VS10XX_XDCS_ENA() \
00374 outr(VS10XX_XDCS_PE_REG, _BV(VS10XX_XDCS_BIT)); \
00375 outr(VS10XX_XDCS_OE_REG, _BV(VS10XX_XDCS_BIT))
00376 #define VS10XX_XDCS_CLR() outr(VS10XX_XDCS_COD_REG, _BV(VS10XX_XDCS_BIT))
00377 #define VS10XX_XDCS_SET() outr(VS10XX_XDCS_SOD_REG, _BV(VS10XX_XDCS_BIT))
00378
00379 #else
00380
00381 #define VS10XX_XDCS_ENA()
00382 #define VS10XX_XDCS_CLR()
00383 #define VS10XX_XDCS_SET()
00384
00385 #endif
00386
00387 #if defined(VS10XX_DREQ_BIT)
00388
00389 #if !defined(VS10XX_DREQ_PIO_ID)
00390 #define VS10XX_DREQ_PE_REG PIO_PER
00391 #define VS10XX_DREQ_OD_REG PIO_ODR
00392 #define VS10XX_DREQ_PDS_REG PIO_PDSR
00393 #elif VS10XX_DREQ_PIO_ID == PIOA_ID
00394 #define VS10XX_DREQ_PE_REG PIOA_PER
00395 #define VS10XX_DREQ_OD_REG PIOA_ODR
00396 #define VS10XX_DREQ_PDS_REG PIOA_PDSR
00397 #elif VS10XX_DREQ_PIO_ID == PIOB_ID
00398 #define VS10XX_DREQ_PE_REG PIOB_PER
00399 #define VS10XX_DREQ_OD_REG PIOB_ODR
00400 #define VS10XX_DREQ_PDS_REG PIOB_PDSR
00401 #elif VS10XX_DREQ_PIO_ID == PIOC_ID
00402 #define VS10XX_DREQ_PE_REG PIOC_PER
00403 #define VS10XX_DREQ_OD_REG PIOC_ODR
00404 #define VS10XX_DREQ_PDS_REG PIOC_PDSR
00405 #endif
00406
00407 #define VS10XX_DREQ_PD_REG PIO_PDR
00408 #define VS10XX_DREQ_OD_REG PIO_ODR
00409 #define VS10XX_DREQ_PDS_REG PIO_PDSR
00410 #define VS10XX_DREQ_ENA() \
00411 outr(VS10XX_DREQ_PD_REG, _BV(VS10XX_DREQ_BIT)); \
00412 outr(VS10XX_DREQ_OD_REG, _BV(VS10XX_DREQ_BIT))
00413 #define VS10XX_DREQ_TST() ((inr(VS10XX_DREQ_PDS_REG) & _BV(VS10XX_DREQ_BIT)) == _BV(VS10XX_DREQ_BIT))
00414
00415 #else
00416
00417 #define VS10XX_DREQ_ENA()
00418 #define VS10XX_DREQ_TST() 0
00419
00420 #endif
00421
00422 #ifdef VS10XX_BSYNC_BIT
00423
00424 #if !defined(VS10XX_BSYNC_PIO_ID)
00425 #define VS10XX_BSYNC_PE_REG PIO_PER
00426 #define VS10XX_BSYNC_OE_REG PIO_OER
00427 #define VS10XX_BSYNC_COD_REG PIO_CODR
00428 #define VS10XX_BSYNC_SOD_REG PIO_SODR
00429 #elif VS10XX_BSYNC_PIO_ID == PIOA_ID
00430 #define VS10XX_BSYNC_PE_REG PIOA_PER
00431 #define VS10XX_BSYNC_OE_REG PIOA_OER
00432 #define VS10XX_BSYNC_COD_REG PIOA_CODR
00433 #define VS10XX_BSYNC_SOD_REG PIOA_SODR
00434 #elif VS10XX_BSYNC_PIO_ID == PIOB_ID
00435 #define VS10XX_BSYNC_PE_REG PIOB_PER
00436 #define VS10XX_BSYNC_OE_REG PIOB_OER
00437 #define VS10XX_BSYNC_COD_REG PIOB_CODR
00438 #define VS10XX_BSYNC_SOD_REG PIOB_SODR
00439 #elif VS10XX_BSYNC_PIO_ID == PIOC_ID
00440 #define VS10XX_BSYNC_PE_REG PIOC_PER
00441 #define VS10XX_BSYNC_OE_REG PIOC_OER
00442 #define VS10XX_BSYNC_COD_REG PIOC_CODR
00443 #define VS10XX_BSYNC_SOD_REG PIOC_SODR
00444 #endif
00445 #define VS10XX_BSYNC_ENA() \
00446 outr(VS10XX_BSYNC_PE_REG, _BV(VS10XX_BSYNC_BIT)); \
00447 outr(VS10XX_BSYNC_OE_REG, _BV(VS10XX_BSYNC_BIT))
00448 #define VS10XX_BSYNC_CLR() outr(VS10XX_BSYNC_COD_REG, _BV(VS10XX_BSYNC_BIT))
00449 #define VS10XX_BSYNC_SET() outr(VS10XX_BSYNC_SOD_REG, _BV(VS10XX_BSYNC_BIT))
00450
00451 #else
00452
00453 #define VS10XX_BSYNC_ENA()
00454 #define VS10XX_BSYNC_CLR()
00455 #define VS10XX_BSYNC_SET()
00456
00457 #endif
00458
00459
00460
00461
00462
00463 #elif defined(__AVR__)
00464
00465 #if !defined(VS10XX_SIGNAL_IRQ)
00466 #define VS10XX_SIGNAL_IRQ INT6
00467 #endif
00468
00469 #if (VS10XX_SIGNAL_IRQ == INT0)
00470 #define VS10XX_SIGNAL sig_INTERRUPT0
00471 #define VS10XX_DREQ_BIT 0
00472 #define VS10XX_DREQ_PDS_REG PIND
00473 #define VS10XX_DREQ_PUE_REG PORTD
00474 #define VS10XX_DREQ_OE_REG DDRD
00475
00476 #elif (VS10XX_SIGNAL_IRQ == INT1)
00477 #define VS10XX_SIGNAL sig_INTERRUPT1
00478 #define VS10XX_DREQ_BIT 1
00479 #define VS10XX_DREQ_PDS_REG PIND
00480 #define VS10XX_DREQ_PUE_REG PORTD
00481 #define VS10XX_DREQ_OE_REG DDRD
00482
00483 #elif (VS10XX_SIGNAL_IRQ == INT2)
00484 #define VS10XX_SIGNAL sig_INTERRUPT2
00485 #define VS10XX_DREQ_BIT 2
00486 #define VS10XX_DREQ_PDS_REG PIND
00487 #define VS10XX_DREQ_PUE_REG PORTD
00488 #define VS10XX_DREQ_OE_REG DDRD
00489
00490 #elif (VS10XX_SIGNAL_IRQ == INT3)
00491 #define VS10XX_SIGNAL sig_INTERRUPT3
00492 #define VS10XX_DREQ_BIT 3
00493 #define VS10XX_DREQ_PDS_REG PIND
00494 #define VS10XX_DREQ_PUE_REG PORTD
00495 #define VS10XX_DREQ_OE_REG DDRD
00496
00497 #elif (VS10XX_SIGNAL_IRQ == INT4)
00498 #define VS10XX_SIGNAL sig_INTERRUPT4
00499 #define VS10XX_DREQ_BIT 4
00500 #define VS10XX_DREQ_PDS_REG PINE
00501 #define VS10XX_DREQ_PUE_REG PORTE
00502 #define VS10XX_DREQ_OE_REG DDRE
00503
00504 #elif (VS10XX_SIGNAL_IRQ == INT5)
00505 #define VS10XX_SIGNAL sig_INTERRUPT5
00506 #define VS10XX_DREQ_BIT 5
00507 #define VS10XX_DREQ_PDS_REG PINE
00508 #define VS10XX_DREQ_PUE_REG PORTE
00509 #define VS10XX_DREQ_OE_REG DDRE
00510
00511 #elif (VS10XX_SIGNAL_IRQ == INT7)
00512 #define VS10XX_SIGNAL sig_INTERRUPT7
00513 #define VS10XX_DREQ_BIT 7
00514 #define VS10XX_DREQ_PDS_REG PINE
00515 #define VS10XX_DREQ_PUE_REG PORTE
00516 #define VS10XX_DREQ_OE_REG DDRE
00517
00518 #else
00519 #define VS10XX_SIGNAL sig_INTERRUPT6
00520 #define VS10XX_DREQ_BIT 6
00521 #define VS10XX_DREQ_PDS_REG PINE
00522 #define VS10XX_DREQ_PUE_REG PORTE
00523 #define VS10XX_DREQ_OE_REG DDRE
00524
00525 #endif
00526
00527 #define VS10XX_DREQ_ENA() \
00528 cbi(VS10XX_DREQ_OE_REG, VS10XX_DREQ_BIT); \
00529 sbi(VS10XX_DREQ_PUE_REG, VS10XX_DREQ_BIT)
00530 #define VS10XX_DREQ_TST() ((inb(VS10XX_DREQ_PDS_REG) & _BV(VS10XX_DREQ_BIT)) == _BV(VS10XX_DREQ_BIT))
00531
00532
00533 #if defined(VS10XX_XCS_BIT)
00534
00535 #if (VS10XX_XCS_PORT == AVRPORTA)
00536 #define VS10XX_XCS_SOD_REG PORTA
00537 #define VS10XX_XCS_OE_REG DDRA
00538 #elif (VS10XX_XCS_PORT == AVRPORTB)
00539 #define VS10XX_XCS_SOD_REG PORTB
00540 #define VS10XX_XCS_OE_REG DDRB
00541 #elif (VS10XX_XCS_PORT == AVRPORTD)
00542 #define VS10XX_XCS_SOD_REG PORTD
00543 #define VS10XX_XCS_OE_REG DDRD
00544 #elif (VS10XX_XCS_PORT == AVRPORTE)
00545 #define VS10XX_XCS_SOD_REG PORTE
00546 #define VS10XX_XCS_OE_REG DDRE
00547 #elif (VS10XX_XCS_PORT == AVRPORTF)
00548 #define VS10XX_XCS_SOD_REG PORTF
00549 #define VS10XX_XCS_OE_REG DDRF
00550 #elif (VS10XX_XCS_PORT == AVRPORTG)
00551 #define VS10XX_XCS_SOD_REG PORTG
00552 #define VS10XX_XCS_OE_REG DDRG
00553 #elif (VS10XX_XCS_PORT == AVRPORTH)
00554 #define VS10XX_XCS_SOD_REG PORTH
00555 #define VS10XX_XCS_OE_REG DDRH
00556 #endif
00557 #define VS10XX_XCS_ENA() sbi(VS10XX_XCS_OE_REG, VS10XX_XCS_BIT)
00558 #define VS10XX_XCS_CLR() cbi(VS10XX_XCS_SOD_REG, VS10XX_XCS_BIT)
00559 #define VS10XX_XCS_SET() sbi(VS10XX_XCS_SOD_REG, VS10XX_XCS_BIT)
00560
00561 #else
00562
00563 #define VS10XX_XCS_ENA()
00564 #define VS10XX_XCS_CLR()
00565 #define VS10XX_XCS_SET()
00566
00567 #endif
00568
00569 #if defined(VS10XX_XDCS_BIT)
00570
00571 #if (VS10XX_XDCS_PORT == AVRPORTA)
00572 #define VS10XX_XDCS_SOD_REG PORTA
00573 #define VS10XX_XDCS_OE_REG DDRA
00574 #elif (VS10XX_XDCS_PORT == AVRPORTB)
00575 #define VS10XX_XDCS_SOD_REG PORTB
00576 #define VS10XX_XDCS_OE_REG DDRB
00577 #elif (VS10XX_XDCS_PORT == AVRPORTD)
00578 #define VS10XX_XDCS_SOD_REG PORTD
00579 #define VS10XX_XDCS_OE_REG DDRD
00580 #elif (VS10XX_XDCS_PORT == AVRPORTE)
00581 #define VS10XX_XDCS_SOD_REG PORTE
00582 #define VS10XX_XDCS_OE_REG DDRE
00583 #elif (VS10XX_XDCS_PORT == AVRPORTF)
00584 #define VS10XX_XDCS_SOD_REG PORTF
00585 #define VS10XX_XDCS_OE_REG DDRF
00586 #elif (VS10XX_XDCS_PORT == AVRPORTG)
00587 #define VS10XX_XDCS_SOD_REG PORTG
00588 #define VS10XX_XDCS_OE_REG DDRG
00589 #elif (VS10XX_XDCS_PORT == AVRPORTH)
00590 #define VS10XX_XDCS_SOD_REG PORTH
00591 #define VS10XX_XDCS_OE_REG DDRH
00592 #endif
00593 #define VS10XX_XDCS_ENA() sbi(VS10XX_XDCS_OE_REG, VS10XX_XDCS_BIT)
00594 #define VS10XX_XDCS_CLR() cbi(VS10XX_XDCS_SOD_REG, VS10XX_XDCS_BIT)
00595 #define VS10XX_XDCS_SET() sbi(VS10XX_XDCS_SOD_REG, VS10XX_XDCS_BIT)
00596
00597 #else
00598
00599 #define VS10XX_XDCS_ENA()
00600 #define VS10XX_XDCS_CLR()
00601 #define VS10XX_XDCS_SET()
00602
00603 #endif
00604
00605
00606 #if defined(VS10XX_BSYNC_BIT)
00607
00608 #if (VS10XX_BSYNC_AVRPORT == AVRPORTA)
00609 #define VS10XX_BSYNC_SOD_REG PORTA
00610 #define VS10XX_BSYNC_OE_REG DDRA
00611 #elif (VS10XX_BSYNC_AVRPORT == AVRPORTB)
00612 #define VS10XX_BSYNC_SOD_REG PORTB
00613 #define VS10XX_BSYNC_OE_REG DDRB
00614 #elif (VS10XX_BSYNC_AVRPORT == AVRPORTD)
00615 #define VS10XX_BSYNC_SOD_REG PORTD
00616 #define VS10XX_BSYNC_OE_REG DDRD
00617 #elif (VS10XX_BSYNC_AVRPORT == AVRPORTE)
00618 #define VS10XX_BSYNC_SOD_REG PORTE
00619 #define VS10XX_BSYNC_OE_REG DDRE
00620 #elif (VS10XX_BSYNC_AVRPORT == AVRPORTF)
00621 #define VS10XX_BSYNC_SOD_REG PORTF
00622 #define VS10XX_BSYNC_OE_REG DDRF
00623 #elif (VS10XX_BSYNC_AVRPORT == AVRPORTG)
00624 #define VS10XX_BSYNC_SOD_REG PORTG
00625 #define VS10XX_BSYNC_OE_REG DDRG
00626 #elif (VS10XX_BSYNC_AVRPORT == AVRPORTH)
00627 #define VS10XX_BSYNC_SOD_REG PORTH
00628 #define VS10XX_BSYNC_OE_REG DDRH
00629 #endif
00630 #define VS10XX_BSYNC_ENA() sbi(VS10XX_BSYNC_OE_REG, VS10XX_BSYNC_BIT)
00631 #define VS10XX_BSYNC_CLR() cbi(VS10XX_BSYNC_SOD_REG, VS10XX_BSYNC_BIT)
00632 #define VS10XX_BSYNC_SET() sbi(VS10XX_BSYNC_SOD_REG, VS10XX_BSYNC_BIT)
00633
00634 #else
00635
00636 #define VS10XX_BSYNC_ENA()
00637 #define VS10XX_BSYNC_CLR()
00638 #define VS10XX_BSYNC_SET()
00639
00640 #endif
00641
00642
00643
00644
00645
00646 #endif
00647
00648
00649 static volatile ureg_t vs_status = VS_STATUS_STOPPED;
00650 static volatile u_int vs_flush;
00651
00652
00653
00654
00655
00656
00657
00658
00659
00660 static INLINE void VsSdiPutByte(ureg_t b)
00661 {
00662 #if defined(VS10XX_BSYNC_BIT)
00663
00664 #if defined(VS10XX_SDI_SBBI0_DEVICE)
00665 ureg_t mask;
00666
00667 VS10XX_BSYNC_SET();
00668
00669 for (mask = 0x80; mask; mask >>= 1) {
00670 SBBI0_SCK_CLR();
00671 if (b & mask) {
00672 SBBI0_MOSI_SET();
00673 }
00674 else {
00675 SBBI0_MOSI_CLR();
00676 }
00677 SBBI0_SCK_SET();
00678 if (mask & 0x40) {
00679 VS10XX_BSYNC_CLR();
00680 }
00681 }
00682 SBBI0_SCK_CLR();
00683 #elif defined(VS10XX_SDI_SBBI1_DEVICE)
00684 ureg_t mask;
00685
00686 VS10XX_BSYNC_SET();
00687
00688 for (mask = 0x80; mask; mask >>= 1) {
00689 SBBI1_SCK_CLR();
00690 if (b & mask) {
00691 SBBI1_MOSI_SET();
00692 }
00693 else {
00694 SBBI1_MOSI_CLR();
00695 }
00696 SBBI1_SCK_SET();
00697 if (mask & 0x40) {
00698 VS10XX_BSYNC_CLR();
00699 }
00700 }
00701 SBBI1_SCK_CLR();
00702 #elif defined(VS10XX_SDI_SBBI2_DEVICE)
00703 ureg_t mask;
00704
00705 VS10XX_BSYNC_SET();
00706
00707 for (mask = 0x80; mask; mask >>= 1) {
00708 SBBI2_SCK_CLR();
00709 if (b & mask) {
00710 SBBI2_MOSI_SET();
00711 }
00712 else {
00713 SBBI2_MOSI_CLR();
00714 }
00715 SBBI2_SCK_SET();
00716 if (mask & 0x40) {
00717 VS10XX_BSYNC_CLR();
00718 }
00719 }
00720 SBBI2_SCK_CLR();
00721 #elif defined(VS10XX_SDI_SBBI3_DEVICE)
00722 ureg_t mask;
00723
00724 VS10XX_BSYNC_SET();
00725
00726 for (mask = 0x80; mask; mask >>= 1) {
00727 SBBI3_SCK_CLR();
00728 if (b & mask) {
00729 SBBI3_MOSI_SET();
00730 }
00731 else {
00732 SBBI3_MOSI_CLR();
00733 }
00734 SBBI3_SCK_SET();
00735 if (mask & 0x40) {
00736 VS10XX_BSYNC_CLR();
00737 }
00738 }
00739 SBBI3_SCK_CLR();
00740 #elif defined(VS10XX_SDI_SPI0_DEVICE)
00741 VS10XX_BSYNC_SET();
00742
00743 outb(SPDR, b);
00744
00745 _NOP();
00746 _NOP();
00747 _NOP();
00748 _NOP();
00749 VS10XX_BSYNC_CLR();
00750
00751
00752 loop_until_bit_is_set(SPSR, SPIF);
00753 #endif
00754
00755 #else
00756
00757 (void)SdiByte(b);
00758
00759 #endif
00760
00761 }
00762
00774 ureg_t VsPlayerInterrupts(ureg_t enable)
00775 {
00776 static ureg_t is_enabled = 0;
00777 ureg_t rc;
00778
00779 rc = is_enabled;
00780 if(enable) {
00781 VS10XX_DREQ_ENA();
00782 NutIrqEnable(&VS10XX_SIGNAL);
00783 }
00784 else {
00785 NutIrqDisable(&VS10XX_SIGNAL);
00786 }
00787 is_enabled = enable;
00788
00789 return rc;
00790 }
00791
00816 ureg_t VsPlayerThrottle(ureg_t on)
00817 {
00818 static ureg_t is_throttled = 0;
00819 ureg_t rc;
00820
00821 rc = is_throttled;
00822 if(on) {
00823 VS10XX_XDCS_SET();
00824 SdiDeselect();
00825 }
00826 else {
00827 VS10XX_XDCS_CLR();
00828 SdiSelect();
00829 }
00830 is_throttled = on;
00831
00832 return rc;
00833 }
00834
00838 static void VsSciSelect(ureg_t on)
00839 {
00840 if (on) {
00841
00842 SdiDeselect();
00843
00844 #if defined(VS10XX_SDI_SPI0_DEVICE) && !defined(VS10XX_SCI_SPI0_DEVICE)
00845
00846
00847
00848 cbi(SPCR, SPE);
00849 #endif
00850
00851
00852 VS10XX_XDCS_SET();
00853
00854 VS10XX_XCS_CLR();
00855
00856 SciSelect();
00857 }
00858 else {
00859
00860 SciDeselect();
00861
00862 VS10XX_XCS_SET();
00863
00864 VS10XX_XDCS_CLR();
00865
00866 SdiSelect();
00867 }
00868 }
00869
00876 static int VsWaitReady(void)
00877 {
00878 int tmo;
00879
00880 for (tmo = 0; tmo < 5000; tmo++) {
00881 if (VS10XX_DREQ_TST()) {
00882 return 0;
00883 }
00884 }
00885 return -1;
00886 }
00887
00888
00889
00890
00891
00892
00893
00894 static int VsSdiWrite(CONST uint8_t * data, size_t len)
00895 {
00896 while (len--) {
00897 if (!VS10XX_DREQ_TST() && VsWaitReady()) {
00898 return -1;
00899 }
00900 VsSdiPutByte(*data);
00901 data++;
00902 }
00903 return 0;
00904 }
00905
00906
00907
00908
00909
00910
00911
00912
00913 static int VsSdiWrite_P(PGM_P data, size_t len)
00914 {
00915 while (len--) {
00916 if (!VS10XX_DREQ_TST() && VsWaitReady()) {
00917 return -1;
00918 }
00919 VsSdiPutByte(PRG_RDB(data));
00920 data++;
00921 }
00922 return 0;
00923 }
00924
00925
00926
00927
00928
00929
00930 static void VsRegWrite(ureg_t reg, uint16_t data)
00931 {
00932
00933 VsWaitReady();
00934 VsSciSelect(1);
00935
00936
00937
00938
00939
00940
00941 (void)SciByte(VS_OPCODE_WRITE);
00942 (void)SciByte((uint8_t) reg);
00943 (void)SciByte((uint8_t) (data >> 8));
00944 (void)SciByte((uint8_t) data);
00945
00946
00947 VsSciSelect(0);
00948 }
00949
00950
00951
00952
00953
00954
00955
00956
00957 static uint16_t VsRegRead(ureg_t reg)
00958 {
00959 uint16_t data;
00960
00961
00962 VsWaitReady();
00963 VsSciSelect(1);
00964
00965 (void)SciByte(VS_OPCODE_READ);
00966 (void)SciByte((uint8_t) reg);
00967 data = (uint16_t)SciByte(0) << 8;
00968 data |= SciByte(0);
00969
00970
00971 VsSciSelect(0);
00972
00973 return data;
00974 }
00975
00976
00977
00978
00979
00980
00981
00982
00983 static void VsPlayerFeed(void *arg)
00984 {
00985 ureg_t j = 32;
00986 size_t total = 0;
00987
00988 if (!VS10XX_DREQ_TST()) {
00989 return;
00990 }
00991
00992
00993
00994
00995 if (vs_status == VS_STATUS_RUNNING) {
00996 char *bp = 0;
00997 size_t consumed = 0;
00998 size_t available = 0;
00999 do {
01000 if(consumed >= available) {
01001
01002 if(consumed) {
01003 NutSegBufReadCommit(consumed);
01004 consumed = 0;
01005 }
01006
01007 bp = NutSegBufReadRequest(&available);
01008 if(available == 0) {
01009
01010 vs_status = VS_STATUS_EOF;
01011 break;
01012 }
01013 }
01014
01015 VsSdiPutByte(*bp);
01016 bp++;
01017 consumed++;
01018 total++;
01019 if (total > 4096) {
01020 vs_status = VS_STATUS_EOF;
01021 break;
01022 }
01023
01024
01025
01026 if (VS10XX_DREQ_TST()) {
01027 j = 32;
01028 }
01029 } while(j--);
01030
01031
01032 NutSegBufReadLast(consumed);
01033 }
01034
01035
01036
01037
01038 if(vs_status != VS_STATUS_RUNNING && vs_flush) {
01039 do {
01040 VsSdiPutByte(0);
01041 if (--vs_flush == 0) {
01042
01043 vs_status = VS_STATUS_EMPTY;
01044 break;
01045 }
01046
01047
01048 if (VS10XX_DREQ_TST()) {
01049 j = 32;
01050 }
01051 } while(j--);
01052 }
01053 }
01054
01066 int VsPlayerKick(void)
01067 {
01068
01069
01070
01071 VsPlayerInterrupts(0);
01072 vs_status = VS_STATUS_RUNNING;
01073 VsPlayerFeed(NULL);
01074 VsPlayerInterrupts(1);
01075
01076 return 0;
01077 }
01078
01087 int VsPlayerStop(void)
01088 {
01089 ureg_t ief;
01090
01091 ief = VsPlayerInterrupts(0);
01092
01093 if (vs_status == VS_STATUS_RUNNING) {
01094 vs_status = VS_STATUS_STOPPED;
01095 }
01096 VsPlayerInterrupts(ief);
01097
01098 return 0;
01099 }
01100
01101
01114 int VsPlayerFlush(void)
01115 {
01116 VsPlayerInterrupts(0);
01117
01118 if (vs_status != VS_STATUS_EMPTY || NutSegBufUsed()) {
01119 if (vs_flush == 0) {
01120 vs_flush = VS_FLUSH_BYTES;
01121 }
01122
01123 if (vs_status != VS_STATUS_RUNNING) {
01124 VsPlayerKick();
01125 }
01126 }
01127 VsPlayerInterrupts(1);
01128
01129 return 0;
01130 }
01131
01137 int VsPlayerInit(void)
01138 {
01139
01140 VsPlayerInterrupts(0);
01141
01142
01143 SciReset(1);
01144
01145
01146 if (SciSetMode()) {
01147 return -1;
01148 }
01149 SciSetSpeed();
01150 SciDeselect();
01151
01152
01153 if (SdiSetMode()) {
01154 return -1;
01155 }
01156 SdiSetSpeed();
01157 SdiDeselect();
01158
01159
01160 VS10XX_BSYNC_CLR();
01161 VS10XX_BSYNC_ENA();
01162
01163
01164 VS10XX_XDCS_SET();
01165 VS10XX_XDCS_ENA();
01166
01167
01168 VS10XX_XCS_SET();
01169 VS10XX_XCS_ENA();
01170
01171
01172 VS10XX_DREQ_ENA();
01173
01174
01175 if (NutRegisterIrqHandler(&VS10XX_SIGNAL, VsPlayerFeed, NULL)) {
01176 return -1;
01177 }
01178
01179
01180 NutIrqSetMode(&VS10XX_SIGNAL, NUT_IRQMODE_RISINGEDGE);
01181
01182
01183 SciReset(0);
01184 NutDelay(VS10XX_HWRST_RECOVER);
01185
01186 return VsPlayerReset(0);
01187 }
01188
01215 int VsPlayerReset(uint16_t mode)
01216 {
01217
01218 VsPlayerInterrupts(0);
01219 vs_status = VS_STATUS_STOPPED;
01220
01221
01222 #if defined(VS10XX_BSYNC_BIT)
01223 VsRegWrite(VS_MODE_REG, VS_SM_RESET | mode);
01224 #else
01225 VsRegWrite(VS_MODE_REG, VS_SM_RESET | VS_SM_SDINEW | mode);
01226 #endif
01227
01228 NutDelay(VS10XX_SWRST_RECOVER);
01229
01230
01231
01232
01233 if ((mode & VS_SM_RESET) != 0 || !VS10XX_DREQ_TST()) {
01234
01235 SciReset(1);
01236
01237 NutDelay(VS10XX_HWRST_DURATION);
01238 SciReset(0);
01239
01240 NutDelay(VS10XX_HWRST_RECOVER);
01241
01242
01243 #if defined(VS10XX_BSYNC_BIT)
01244 VsRegWrite(VS_MODE_REG, VS_SM_RESET | mode);
01245 #else
01246 VsRegWrite(VS_MODE_REG, VS_SM_RESET | VS_SM_SDINEW | mode);
01247 #endif
01248 NutDelay(VS10XX_SWRST_RECOVER);
01249 if (!VS10XX_DREQ_TST()) {
01250 return -1;
01251 }
01252 }
01253
01254 #if VS10XX_FREQ < 20000000UL
01255 VsRegWrite(VS_CLOCKF_REG, (uint16_t)(VS_CF_DOUBLER | (VS10XX_FREQ / 2000UL)));
01256 #else
01257 VsRegWrite(VS_CLOCKF_REG, (uint16_t)(VS10XX_FREQ / 2000UL));
01258 #endif
01259 #if defined(AUDIO_VS1001K)
01260
01261 VsRegWrite(VS_INT_FCTLH_REG, 0x8008);
01262 #endif
01263 NutDelay(1);
01264
01265 #if defined(VS10XX_SDI_SPI0_DEVICE) || defined(VS10XX_SCI_SPI0_DEVICE)
01266
01267 outb(EIFR, BV(VS10XX_DREQ_BIT));
01268 #endif
01269
01270 return 0;
01271 }
01272
01296 int VsPlayerSetMode(uint16_t mode)
01297 {
01298 ureg_t ief;
01299
01300 ief = VsPlayerInterrupts(0);
01301 #if defined(VS10XX_BSYNC_BIT)
01302 VsRegWrite(VS_MODE_REG, mode);
01303 #else
01304 VsRegWrite(VS_MODE_REG, VS_SM_SDINEW | mode);
01305 #endif
01306 VsPlayerInterrupts(ief);
01307
01308 return 0;
01309 }
01310
01316 uint16_t VsPlayTime(void)
01317 {
01318 uint16_t rc;
01319 ureg_t ief;
01320
01321 ief = VsPlayerInterrupts(0);
01322 rc = VsRegRead(VS_DECODE_TIME_REG);
01323 VsPlayerInterrupts(ief);
01324
01325 return rc;
01326 }
01327
01337 u_int VsGetStatus(void)
01338 {
01339 return vs_status;
01340 }
01341
01342 #ifdef __GNUC__
01343
01351 int VsGetHeaderInfo(VS_HEADERINFO * vshi)
01352 {
01353 uint16_t *usp = (uint16_t *) vshi;
01354 ureg_t ief;
01355
01356 ief = VsPlayerInterrupts(0);
01357 *usp = VsRegRead(VS_HDAT1_REG);
01358 *++usp = VsRegRead(VS_HDAT0_REG);
01359 VsPlayerInterrupts(ief);
01360
01361 return 0;
01362 }
01363 #endif
01364
01377 uint16_t VsMemoryTest(void)
01378 {
01379 uint16_t rc;
01380 ureg_t ief;
01381 static prog_char mtcmd[] = { 0x4D, 0xEA, 0x6D, 0x54, 0x00, 0x00, 0x00, 0x00 };
01382
01383 ief = VsPlayerInterrupts(0);
01384 #if defined(VS10XX_BSYNC_BIT)
01385 VsRegWrite(VS_MODE_REG, VS_SM_TESTS);
01386 #else
01387 VsRegWrite(VS_MODE_REG, VS_SM_TESTS | VS_SM_SDINEW);
01388 #endif
01389 VsSdiWrite_P(mtcmd, sizeof(mtcmd));
01390 while(((rc = VsRegRead(VS_HDAT0_REG)) & 0x8000) == 0) {
01391 NutDelay(1);
01392 }
01393 #if defined(VS10XX_BSYNC_BIT)
01394 VsRegWrite(VS_MODE_REG, 0);
01395 #else
01396 VsRegWrite(VS_MODE_REG, VS_SM_SDINEW);
01397 #endif
01398 VsPlayerInterrupts(ief);
01399
01400 return rc;
01401 }
01402
01412 int VsSetVolume(ureg_t left, ureg_t right)
01413 {
01414 ureg_t ief;
01415
01416 ief = VsPlayerInterrupts(0);
01417 VsRegWrite(VS_VOL_REG, ((uint16_t)left << VS_VOL_LEFT_LSB) | ((uint16_t)right << VS_VOL_RIGHT_LSB));
01418 VsPlayerInterrupts(ief);
01419
01420 return 0;
01421 }
01422
01431 int VsBeep(uint8_t fsin, uint8_t ms)
01432 {
01433 ureg_t ief;
01434 static prog_char on[] = { 0x53, 0xEF, 0x6E };
01435 static prog_char off[] = { 0x45, 0x78, 0x69, 0x74 };
01436 static prog_char end[] = { 0x00, 0x00, 0x00, 0x00 };
01437
01438
01439 ief = VsPlayerInterrupts(0);
01440
01441 #if defined(VS10XX_BSYNC_BIT)
01442 VsRegWrite(VS_MODE_REG, VS_SM_TESTS);
01443 #else
01444 VsRegWrite(VS_MODE_REG, VS_SM_TESTS | VS_SM_SDINEW);
01445 #endif
01446
01447 fsin = 56 + (fsin & 7) * 9;
01448 VsSdiWrite_P(on, sizeof(on));
01449 VsSdiWrite(&fsin, 1);
01450 VsSdiWrite_P(end, sizeof(end));
01451 NutDelay(ms);
01452 VsSdiWrite_P(off, sizeof(off));
01453 VsSdiWrite_P(end, sizeof(end));
01454
01455 #if defined(VS10XX_BSYNC_BIT)
01456 VsRegWrite(VS_MODE_REG, 0);
01457 #else
01458 VsRegWrite(VS_MODE_REG, VS_SM_SDINEW);
01459 #endif
01460
01461
01462 VsPlayerInterrupts(ief);
01463
01464 return 0;
01465 }
01466
01467