00001 #ifndef _ARCH_ARM_SAM7S_H_
00002 #define _ARCH_ARM_SAM7S_H_
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00051 #define FLASH_BASE 0x100000UL
00052 #define RAM_BASE 0x200000UL
00053
00054 #define TC_BASE 0xFFFA0000
00055 #define UDP_BASE 0xFFFB0000
00056 #define TWI_BASE 0xFFFB8000
00057 #define USART0_BASE 0xFFFC0000
00058 #define USART1_BASE 0xFFFC4000
00059 #define PWMC_BASE 0xFFFCC000
00060 #define SSC_BASE 0xFFFD4000
00061 #define ADC_BASE 0xFFFD8000
00062 #define SPI0_BASE 0xFFFE0000
00064 #define AIC_BASE 0xFFFFF000
00065 #define DBGU_BASE 0xFFFFF200
00066 #define PIOA_BASE 0xFFFFF400
00067 #define PMC_BASE 0xFFFFFC00
00068 #define RSTC_BASE 0xFFFFFD00
00069 #define RTT_BASE 0xFFFFFD20
00070 #define PIT_BASE 0xFFFFFD30
00071 #define WDT_BASE 0xFFFFFD40
00072 #define VREG_BASE 0xFFFFFD60
00073 #define MC_BASE 0xFFFFFF00
00075 #define PERIPH_RPR_OFF 0x00000100
00076 #define PERIPH_RCR_OFF 0x00000104
00077 #define PERIPH_TPR_OFF 0x00000108
00078 #define PERIPH_TCR_OFF 0x0000010C
00079 #define PERIPH_RNPR_OFF 0x00000110
00080 #define PERIPH_RNCR_OFF 0x00000114
00081 #define PERIPH_TNPR_OFF 0x00000118
00082 #define PERIPH_TNCR_OFF 0x0000011C
00083 #define PERIPH_PTCR_OFF 0x00000120
00084 #define PERIPH_PTSR_OFF 0x00000124
00086 #define PDC_RXTEN 0x00000001
00087 #define PDC_RXTDIS 0x00000002
00088 #define PDC_TXTEN 0x00000100
00089 #define PDC_TXTDIS 0x00000200
00091 #define DBGU_HAS_PDC
00092 #define SPI_HAS_PDC
00093 #define SSC_HAS_PDC
00094 #define USART_HAS_PDC
00095 #define USART_HAS_MODE
00096
00097 #define PIO_HAS_MULTIDRIVER
00098 #define PIO_HAS_PULLUP
00099 #define PIO_HAS_PERIPHERALSELECT
00100 #define PIO_HAS_OUTPUTWRITEENABLE
00101
00102 #include <arch/arm/at91_tc.h>
00103 #include <arch/arm/at91_us.h>
00104 #include <arch/arm/at91_dbgu.h>
00105 #include <arch/arm/at91_spi.h>
00106 #include <arch/arm/at91_aic.h>
00107 #include <arch/arm/at91_pio.h>
00108 #include <arch/arm/at91_pmc.h>
00109 #include <arch/arm/at91_rstc.h>
00110 #include <arch/arm/at91_wdt.h>
00111 #include <arch/arm/at91_pit.h>
00112 #include <arch/arm/at91_mc.h>
00113 #include <arch/arm/at91_ssc.h>
00114 #include <arch/arm/at91_twi.h>
00115 #include <arch/arm/at91_adc.h>
00116
00119
00122 #define FIQ_ID 0
00123 #define SYSC_ID 1
00124 #define PIOA_ID 2
00125
00126 #define ADC_ID 4
00127 #define SPI0_ID 5
00128 #define US0_ID 6
00129 #define US1_ID 7
00130 #define SSC_ID 8
00131 #define TWI_ID 9
00132 #define PWMC_ID 10
00133 #define UDP_ID 11
00134 #define TC0_ID 12
00135 #define TC1_ID 13
00136 #define TC2_ID 14
00137
00138 #define IRQ0_ID 30
00139 #define IRQ1_ID 31
00141
00142
00144 #define SPI0_NPCS0_PA11A 11
00145 #define SPI0_NPCS1_PA09B 9
00146 #define SPI0_NPCS1_PA31A 31
00147 #define SPI0_NPCS2_PA10B 10
00148 #define SPI0_NPCS2_PA30B 30
00149 #define SPI0_NPCS3_PA03B 3
00150 #define SPI0_NPCS3_PA05B 5
00151 #define SPI0_NPCS3_PA22B 22
00152 #define SPI0_MISO_PA12A 12
00153 #define SPI0_MOSI_PA13A 13
00154 #define SPI0_SPCK_PA14A 14
00156
00157
00159 #define PA5_RXD0_A 5
00160 #define PA6_TXD0_A 6
00161 #define PA2_SCK0_B 2
00162 #define PA7_RTS0_A 7
00163 #define PA8_CTS0_A 8
00164
00165 #define PA21_RXD1_A 21
00166 #define PA22_TXD1_A 22
00167 #define PA23_SCK1_A 23
00168 #define PA24_RTS1_A 24
00169 #define PA25_CTS1_A 25
00170 #define PB26_DCD1_A 26
00171 #define PB28_DSR1_A 28
00172 #define PB27_DTR1_A 27
00173 #define PB29_RI1_A 29
00174
00178 #define PA12_SPI0_MISO_A 12
00179 #define PA13_SPI0_MOSI_A 13
00180 #define PA14_SPI0_SPCK_A 14
00181 #define PA11_SPI0_NPCS0_A 11
00182 #define PA9_SPI0_NPCS1_B 9
00183 #define PA31_SPI0_NPCS1_A 31
00184 #define PA10_SPI0_NPCS2_B 10
00185 #define PB30_SPI0_NPCS2_B 30
00186 #define PA3_SPI0_NPCS3_B 3
00187 #define PA5_SPI0_NPCS3_B 5
00188 #define PA22_SPI0_NPCS3_B 22
00189
00190 #define SPI0_PINS _BV(PA12_SPI0_MISO_A) | _BV(PA13_SPI0_MOSI_A) | _BV(PA14_SPI0_SPCK_A)
00191 #define SPI0_PIO_BASE PIOA_BASE
00192 #define SPI0_PSR_OFF PIO_ASR_OFF
00193
00194 #define SPI0_CS0_PIN _BV(PA11_SPI0_NPCS0_A)
00195 #define SPI0_CS0_PIO_BASE PIOA_BASE
00196 #define SPI0_CS0_PSR_OFF PIO_ASR_OFF
00197
00198 #ifndef SPI0_CS1_PIN
00199 #define SPI0_CS1_PIN _BV(PA9_SPI0_NPCS1_B)
00200 #define SPI0_CS1_PIO_BASE PIOA_BASE
00201 #define SPI0_CS1_PSR_OFF PIO_ASR_OFF
00202 #endif
00203
00204 #ifndef SPI0_CS2_PIN
00205 #define SPI0_CS2_PIN _BV(PA10_SPI0_NPCS2_B)
00206 #define SPI0_CS2_PIO_BASE PIOA_BASE
00207 #define SPI0_CS2_PSR_OFF PIO_ASR_OFF
00208 #endif
00209
00210 #ifndef SPI0_CS3_PIN
00211 #define SPI0_CS3_PIN _BV(PA3_SPI0_NPCS3_B)
00212 #define SPI0_CS3_PIO_BASE PIOA_BASE
00213 #define SPI0_CS3_PSR_OFF PIO_ASR_OFF
00214 #endif
00215
00220 #define PA9_DRXD_A 9
00221 #define PA10_DTXD_A 10
00222
00226 #define PA17_TD_A 17
00227 #define PA18_RD_A 18
00228 #define PA16_TK_A 16
00229 #define PA19_RK_A 19
00230 #define PA15_TF_A 15
00231 #define PA20_RF_A 20
00233
00234
00236 #define PA3_TWD_A 3
00237 #define PA4_TWCK_A 4
00239
00240
00242 #define PA0_TIOA0_B 0
00243 #define PA1_TIOB0_B 1
00244 #define PA4_TCLK0_B 4
00245
00246 #define PA15_TIOA1_B 15
00247 #define PA16_TIOB1_B 16
00248 #define PA28_TCLK1_B 28
00249
00250 #define PA26_TIOA2_B 26
00251 #define PA27_TIOB2_B 27
00252 #define PA29_TCLK2_B 29
00253
00257 #define PA6_PCK0_B 6
00258 #define PA17_PCK1_B 17
00259 #define PA21_PCK1_B 21
00260 #define PA18_PCK2_B 18
00261 #define PA31_PCK2_B 31
00262
00266 #define PA19_FIQ_B 19
00267 #define PA20_IRQ0_B 20
00268 #define PA30_IRQ1_A 30
00269
00273 #define PA8_ADTRG_B 8
00275
00276
00278 #define PA0_PWM0_A 0
00279 #define PA23_PWM0_B 23
00280 #define PA1_PWM1_A 1
00281 #define PA24_PWM1_B 24
00282 #define PA2_PWM2_A 2
00283 #define PA13_PWM2_B 13
00284 #define PA25_PWM2_B 25
00285 #define PA7_PWM3_B 7
00286 #define PA14_PWM3_B 14
00287
00289
00291 #endif