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PWMC Mode Register |
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#define | PWMC_MR_OFF 0x00000000 |
| Mode register offset.
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#define | PWMC_MR (PWMC_BASE + PWMC_MR_OFF) |
| Mode register address.
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#define | PWMC_DIVA 0x000000FF |
| Clock divider A mask.
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#define | PWMC_DIVA_LSB 0 |
| Clock divider A LSB.
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#define | PWMC_PREA 0x00000F00 |
| Prescaler A clock selection mask.
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#define | PWMC_PREA_MCK2 0x00000100 |
| Selects prescaler A MCK / 2.
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#define | PWMC_PREA_MCK4 0x00000200 |
| Selects prescaler A MCK / 4.
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#define | PWMC_PREA_MCK8 0x00000300 |
| Selects prescaler A MCK / 8.
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#define | PWMC_PREA_MCK16 0x00000400 |
| Selects prescaler A MCK / 16.
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#define | PWMC_PREA_MCK32 0x00000500 |
| Selects prescaler A MCK / 32.
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#define | PWMC_PREA_MCK64 0x00000600 |
| Selects prescaler A MCK / 64.
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#define | PWMC_PREA_MCK128 0x00000700 |
| Selects prescaler A MCK / 128.
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#define | PWMC_PREA_MCK256 0x00000800 |
| Selects prescaler A MCK / 256.
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#define | PWMC_PREA_MCK512 0x00000900 |
| Selects prescaler A MCK / 512.
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#define | PWMC_PREA_MCK1024 0x00000A00 |
| Selects prescaler A MCK / 1024.
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#define | PWMC_DIVB 0x00FF0000 |
| Clock divider B mask.
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#define | PWMC_DIVB_LSB 16 |
| Clock divider B LSB.
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#define | PWMC_PREB 0x0F000000 |
| Prescaler B clock selection mask.
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#define | PWMC_PREB_MCK2 0x01000000 |
| Selects prescaler B MCK / 2.
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#define | PWMC_PREB_MCK4 0x02000000 |
| Selects prescaler B MCK / 4.
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#define | PWMC_PREB_MCK8 0x03000000 |
| Selects prescaler B MCK / 8.
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#define | PWMC_PREB_MCK16 0x04000000 |
| Selects prescaler B MCK / 16.
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#define | PWMC_PREB_MCK32 0x05000000 |
| Selects prescaler B MCK / 32.
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#define | PWMC_PREB_MCK64 0x06000000 |
| Selects prescaler B MCK / 64.
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#define | PWMC_PREB_MCK128 0x07000000 |
| Selects prescaler B MCK / 128.
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#define | PWMC_PREB_MCK256 0x08000000 |
| Selects prescaler B MCK / 256.
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#define | PWMC_PREB_MCK512 0x09000000 |
| Selects prescaler B MCK / 512.
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#define | PWMC_PREB_MCK1024 0x0A000000 |
| Selects prescaler B MCK / 1024.
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PWMC Enable/Disable Registers |
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#define | PWMC_ENA_OFF 0x00000004 |
| Enable register offset.
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#define | PWMC_ENA (PWMC_BASE + PWMC_ENA_OFF) |
| Enable register address.
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#define | PWMC_DIS_OFF 0x00000008 |
| Disable register offset.
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#define | PWMC_DIS (PWMC_BASE + PWMC_DIS_OFF) |
| Disable register address.
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#define | PWMC_SR_OFF 0x0000000C |
| Status register offset.
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#define | PWMC_SR (PWMC_BASE + PWMC_SR_OFF) |
| Status register address.
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#define | PWMC_IER_OFF 0x00000010 |
| Interrupt enable register offset.
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#define | PWMC_IER (PWMC_BASE + PWMC_IER_OFF) |
| Interrupt enable register address.
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#define | PWMC_IDR_OFF 0x00000014 |
| Interrupt disable register offset.
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#define | PWMC_IDR (PWMC_BASE + PWMC_IDR_OFF) |
| Interrupt disable register address.
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#define | PWMC_IMR_OFF 0x00000018 |
| Interrupt mask register offset.
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#define | PWMC_IMR (PWMC_BASE + PWMC_IMR_OFF) |
| Interrupt mask register address.
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#define | PWMC_ISR_OFF 0x0000001C |
| Interrupt status register offset.
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#define | PWMC_ISR (PWMC_BASE + PWMC_ISR_OFF) |
| Interrupt status register address.
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#define | PWMC_CHID0 0x00000001 |
| Channel 0 ID.
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#define | PWMC_CHID1 0x00000002 |
| Channel 1 ID.
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#define | PWMC_CHID2 0x00000004 |
| Channel 2 ID.
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#define | PWMC_CHID3 0x00000008 |
| Channel 3 ID.
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PWM Channel Mode Registers |
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#define | PWMC_CMR_OFF 0x00000200 |
| Channel mode register offset.
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#define | PWMC_CMR(i) (PWMC_BASE + ((i) * 32) + PWMC_CMR_OFF) |
| Channel mode register addresses.
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#define | PWMC_CPRE 0x0000000F |
| Channel prescaler clock selection mask.
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#define | PWMC_CPRE_MCK2 0x00000001 |
| Selects channel prescaler MCK / 2.
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#define | PWMC_CPRE_MCK4 0x00000002 |
| Selects channel prescaler MCK / 4.
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#define | PWMC_CPRE_MCK8 0x00000003 |
| Selects channel prescaler MCK / 8.
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#define | PWMC_CPRE_MCK16 0x00000004 |
| Selects channel prescaler MCK / 16.
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#define | PWMC_CPRE_MCK32 0x00000005 |
| Selects channel prescaler MCK / 32.
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#define | PWMC_CPRE_MCK64 0x00000006 |
| Selects channel prescaler MCK / 64.
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#define | PWMC_CPRE_MCK128 0x00000007 |
| Selects channel prescaler MCK / 128.
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#define | PWMC_CPRE_MCK256 0x00000008 |
| Selects channel prescaler MCK / 256.
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#define | PWMC_CPRE_MCK512 0x00000009 |
| Selects channel prescaler MCK / 512.
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#define | PWMC_CPRE_MCK1024 0x0000000A |
| Selects channel prescaler MCK / 1024.
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#define | PWMC_CPRE_CLKA 0x0000000B |
| Selects channel prescaler CLKA.
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#define | PWMC_CPRE_CLKB 0x0000000C |
| Selects channel prescaler CLKB.
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#define | PWMC_CALG 0x00000100 |
| Center aligned channel period.
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#define | PWMC_CPOL 0x00000200 |
| Output waveform starts at a high level.
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#define | PWMC_CPD 0x00000400 |
| Channel update period.
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PWM Channel Duty Cycle Registers |
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#define | PWMC_CDTY_OFF 0x00000204 |
| Channel duty cycle register offset.
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#define | PWMC_CDTY(i) (PWMC_BASE + PWMC_CDTY_OFF + ((i) * 32)) |
| Channel duty cycle register addresses.
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PWM Channel Period Registers |
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#define | PWMC_CPRD_OFF 0x00000208 |
| Channel period register offset.
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#define | PWMC_CPRD(i) (PWMC_BASE + PWMC_CPRD_OFF + ((i) * 32)) |
| Channel period register addresses.
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PWM Channel Counter Registers |
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#define | PWMC_CCNT_OFF 0x0000020C |
| Channel counter register offset.
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#define | PWMC_CCNT(i) (PWMC_BASE + PWMC_CCNT_OFF + ((i) * 32)) |
| Channel counter register addresses.
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PWM Channel Update Registers |
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#define | PWMC_CUPD_OFF 0x00000210 |
| Channel update register offset.
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#define | PWMC_CUPD(i) (PWMC_BASE + PWMC_CUPD_OFF + ((i) * 32)) |
| Channel update register addresses.
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