LAN91C111 registers
[SMSC LAN91C111]

Collaboration diagram for LAN91C111 registers:
SMSC LAN91C111 register definitions. More...

Data Structures

struct  _NICINFO
 Network interface controller information structure. More...
struct  _NICINFO
 Network interface controller information structure. More...

Defines

#define NIC_BSR   (LANC111_BASE_ADDR + 0x0E)
 Bank select register.
#define NIC_TCR   (LANC111_BASE_ADDR + 0x00)
 Bank 0 - Transmit control register.
#define TCR_SWFDUP   0x8000
#define TCR_EPH_LOOP   0x2000
#define TCR_STP_SQET   0x1000
#define TCR_FDUPLX   0x0800
#define TCR_MON_CSN   0x0400
#define TCR_NOCRC   0x0100
#define TCR_PAD_EN   0x0080
#define TCR_FORCOL   0x0004
#define TCR_LOOP   0x0002
#define TCR_TXENA   0x0001
#define NIC_EPHSR   (LANC111_BASE_ADDR + 0x02)
 Bank 0 - EPH status register.
#define NIC_RCR   (LANC111_BASE_ADDR + 0x04)
 Bank 0 - Receive control register.
#define RCR_SOFT_RST   0x8000
#define RCR_FILT_CAR   0x4000
#define RCR_ABORT_ENB   0x2000
#define RCR_STRIP_CRC   0x0200
#define RCR_RXEN   0x0100
#define RCR_ALMUL   0x0004
#define RCR_PRMS   0x0002
#define RCR_RX_ABORT   0x0001
#define NIC_ECR   (LANC111_BASE_ADDR + 0x06)
 Bank 0 - Counter register.
#define NIC_MIR   (LANC111_BASE_ADDR + 0x08)
 Bank 0 - Memory information register.
#define NIC_RPCR   (LANC111_BASE_ADDR + 0x0A)
 Bank 0 - Receive / PHY control register.
#define RPCR_SPEED   0x2000
#define RPCR_DPLX   0x1000
#define RPCR_ANEG   0x0800
#define RPCR_LEDA_PAT   0x0000
#define RPCR_LEDB_PAT   0x0010
#define NIC_CR   (LANC111_BASE_ADDR + 0x00)
 Bank 1 - Configuration register.
#define CR_EPH_EN   0x8000
#define NIC_BAR   (LANC111_BASE_ADDR + 0x02)
 Bank 1 - Base address register.
#define NIC_IAR   (LANC111_BASE_ADDR + 0x04)
 Bank 1 - Individual address register.
#define NIC_GPR   (LANC111_BASE_ADDR + 0x0A)
 Bank 1 - General purpose register.
#define NIC_CTR   (LANC111_BASE_ADDR + 0x0C)
 Bank 1 - Control register.
#define CTR_RCV_BAD   0x4000
#define CTR_AUTO_RELEASE   0x0800
#define NIC_MMUCR   (LANC111_BASE_ADDR + 0x00)
 Bank 2 - MMU command register.
#define MMUCR_BUSY   0x0001
#define MMU_NOP   0
#define MMU_ALO   (1<<5)
#define MMU_RST   (2<<5)
#define MMU_REM   (3<<5)
#define MMU_TOP   (4<<5)
#define MMU_PKT   (5<<5)
#define MMU_ENQ   (6<<5)
#define MMU_RTX   (7<<5)
#define NIC_PNR   (LANC111_BASE_ADDR + 0x02)
 Bank 2 - Packet number register.
#define NIC_ARR   (LANC111_BASE_ADDR + 0x03)
 Bank 2 - Allocation result register.
#define ARR_FAILED   0x80
#define NIC_FIFO   (LANC111_BASE_ADDR + 0x04)
 Bank 2 - FIFO ports register.
#define NIC_PTR   (LANC111_BASE_ADDR + 0x06)
 Bank 2 - Pointer register.
#define PTR_RCV   0x8000
#define PTR_AUTO_INCR   0x4000
#define PTR_READ   0x2000
#define PTR_ETEN   0x1000
#define PTR_NOT_EMPTY   0x0800
#define NIC_DATA   (LANC111_BASE_ADDR + 0x08)
 Bank 2 - Data register.
#define NIC_IST   (LANC111_BASE_ADDR + 0x0C)
 Bank 2 - Interrupt status register.
#define NIC_ACK   (LANC111_BASE_ADDR + 0x0C)
 Bank 2 - Interrupt acknowledge register.
#define NIC_MSK   (LANC111_BASE_ADDR + 0x0D)
 Bank 2 - Interrupt mask register.
#define INT_MD   0x80
 PHY state change interrupt bit mask.
#define INT_ERCV   0x40
 Early receive interrupt bit mask.
#define INT_EPH   0x20
 Ethernet protocol interrupt bit mask.
#define INT_RX_OVRN   0x10
 Receive overrun interrupt bit mask.
#define INT_ALLOC   0x08
 Transmit allocation interrupt bit mask.
#define INT_TX_EMPTY   0x04
 Transmitter empty interrupt bit mask.
#define INT_TX   0x02
 Transmit complete interrupt bit mask.
#define INT_RCV   0x01
 Receive interrupt bit mask.
#define NIC_MT   (LANC111_BASE_ADDR + 0x00)
 Bank 3 - Multicast table register.
#define NIC_MGMT   (LANC111_BASE_ADDR + 0x08)
 Bank 3 - Management interface register.
#define MGMT_MDOE   0x08
#define MGMT_MCLK   0x04
#define MGMT_MDI   0x02
#define MGMT_MDO   0x01
#define NIC_REV   (LANC111_BASE_ADDR + 0x0A)
 Bank 3 - Revision register.
#define NIC_ERCV   (LANC111_BASE_ADDR + 0x0C)
 Bank 3 - Early RCV register.
#define NIC_PHYCR   0
 PHY control register.
#define PHYCR_RST   0x8000
#define PHYCR_LPBK   0x4000
#define PHYCR_SPEED   0x2000
#define PHYCR_ANEG_EN   0x1000
#define PHYCR_PDN   0x0800
#define PHYCR_MII_DIS   0x0400
#define PHYCR_ANEG_RST   0x0200
#define PHYCR_DPLX   0x0100
#define PHYCR_COLST   0x0080
#define NIC_PHYSR   1
 PHY status register.
#define PHYSR_CAP_T4   0x8000
#define PHYSR_CAP_TXF   0x4000
#define PHYSR_CAP_TXH   0x2000
#define PHYSR_CAP_TF   0x1000
#define PHYSR_CAP_TH   0x0800
#define PHYSR_CAP_SUPR   0x0040
#define PHYSR_ANEG_ACK   0x0020
#define PHYSR_REM_FLT   0x0010
#define PHYSR_CAP_ANEG   0x0008
#define PHYSR_LINK   0x0004
#define PHYSR_JAB   0x0002
#define PHYSR_EXREG   0x0001
#define NIC_PHYID1   2
 PHY identifier register 1.
#define NIC_PHYID2   3
 PHY identifier register 1.
#define NIC_PHYANAD   4
 PHY auto-negotiation advertisement register.
#define PHYANAD_NP   0x8000
#define PHYANAD_ACK   0x4000
#define PHYANAD_RF   0x2000
#define PHYANAD_T4   0x0200
#define PHYANAD_TX_FDX   0x0100
#define PHYANAD_TX_HDX   0x0080
#define PHYANAD_10FDX   0x0040
#define PHYANAD_10_HDX   0x0020
#define PHYANAD_CSMA   0x0001
#define NIC_PHYANRC   5
 PHY auto-negotiation remote end capability register.
#define NIC_PHYCFR1   16
 PHY configuration register 1.
#define NIC_PHYCFR2   17
 PHY configuration register 2.
#define NIC_PHYSOR   18
 PHY status output register.
#define PHYSOR_INT   0x8000
#define PHYSOR_LNKFAIL   0x4000
#define PHYSOR_LOSSSYNC   0x2000
#define PHYSOR_CWRD   0x1000
#define PHYSOR_SSD   0x0800
#define PHYSOR_ESD   0x0400
#define PHYSOR_RPOL   0x0200
#define PHYSOR_JAB   0x0100
#define PHYSOR_SPDDET   0x0080
#define PHYSOR_DPLXDET   0x0040
#define NIC_PHYMSK   19
 PHY mask register.
#define PHYMSK_MINT   0x8000
#define PHYMSK_MLNKFAIL   0x4000
#define PHYMSK_MLOSSSYN   0x2000
#define PHYMSK_MCWRD   0x1000
#define PHYMSK_MSSD   0x0800
#define PHYMSK_MESD   0x0400
#define PHYMSK_MRPOL   0x0200
#define PHYMSK_MJAB   0x0100
#define PHYMSK_MSPDDT   0x0080
#define PHYMSK_MDPLDT   0x0040
#define MSBV(bit)   (1 << ((bit) - 8))
#define nic_outlb(addr, val)   (*(volatile uint8_t *)(addr) = (val))
#define nic_outhb(addr, val)   (*(volatile uint8_t *)((addr) + 1) = (val))
#define nic_outwx(addr, val)   (*(volatile uint16_t *)(addr) = (val))
#define nic_outw(addr, val)
#define nic_inlb(addr)   (*(volatile uint8_t *)(addr))
#define nic_inhb(addr)   (*(volatile uint8_t *)((addr) + 1))
#define nic_inw(addr)   (*(volatile uint16_t *)(addr))
#define nic_bs(bank)   nic_outlb(NIC_BSR, bank)

Typedefs

typedef struct _NICINFO NICINFO
 Network interface controller information type.

Detailed Description

SMSC LAN91C111 register definitions.


Define Documentation

#define NIC_BSR   (LANC111_BASE_ADDR + 0x0E)

Bank select register.

Definition at line 215 of file lanc111.c.

#define NIC_TCR   (LANC111_BASE_ADDR + 0x00)

Bank 0 - Transmit control register.

Definition at line 220 of file lanc111.c.

#define TCR_SWFDUP   0x8000

NIC_TCR bit mask, enables full duplex.

Definition at line 222 of file lanc111.c.

#define TCR_EPH_LOOP   0x2000

NIC_TCR bit mask, enables internal loopback.

Definition at line 223 of file lanc111.c.

#define TCR_STP_SQET   0x1000

NIC_TCR bit mask, enables transmission stop on SQET error.

Definition at line 224 of file lanc111.c.

#define TCR_FDUPLX   0x0800

NIC_TCR bit mask, enables receiving own frames.

Definition at line 225 of file lanc111.c.

#define TCR_MON_CSN   0x0400

NIC_TCR bit mask, enables carrier monitoring.

Definition at line 226 of file lanc111.c.

#define TCR_NOCRC   0x0100

NIC_TCR bit mask, disables CRC transmission.

Definition at line 227 of file lanc111.c.

#define TCR_PAD_EN   0x0080

NIC_TCR bit mask, enables automatic padding.

Definition at line 228 of file lanc111.c.

#define TCR_FORCOL   0x0004

NIC_TCR bit mask, forces collision.

Definition at line 229 of file lanc111.c.

#define TCR_LOOP   0x0002

NIC_TCR bit mask, enables PHY loopback.

Definition at line 230 of file lanc111.c.

#define TCR_TXENA   0x0001

NIC_TCR bit mask, enables transmitter.

Definition at line 231 of file lanc111.c.

#define NIC_EPHSR   (LANC111_BASE_ADDR + 0x02)

Bank 0 - EPH status register.

Definition at line 237 of file lanc111.c.

#define NIC_RCR   (LANC111_BASE_ADDR + 0x04)

Bank 0 - Receive control register.

Definition at line 242 of file lanc111.c.

#define RCR_SOFT_RST   0x8000

NIC_RCR bit mask, activates software reset.

Definition at line 244 of file lanc111.c.

#define RCR_FILT_CAR   0x4000

NIC_RCR bit mask, enables carrier filter.

Definition at line 245 of file lanc111.c.

#define RCR_ABORT_ENB   0x2000

NIC_RCR bit mask, enables receive abort on collision.

Definition at line 246 of file lanc111.c.

#define RCR_STRIP_CRC   0x0200

NIC_RCR bit mask, strips CRC.

Definition at line 247 of file lanc111.c.

#define RCR_RXEN   0x0100

NIC_RCR bit mask, enables receiver.

Definition at line 248 of file lanc111.c.

#define RCR_ALMUL   0x0004

NIC_RCR bit mask, multicast frames accepted when set.

Definition at line 249 of file lanc111.c.

#define RCR_PRMS   0x0002

NIC_RCR bit mask, enables promiscuous mode.

Definition at line 250 of file lanc111.c.

#define RCR_RX_ABORT   0x0001

NIC_RCR bit mask, set when receive was aborted.

Definition at line 251 of file lanc111.c.

#define NIC_ECR   (LANC111_BASE_ADDR + 0x06)

Bank 0 - Counter register.

Definition at line 256 of file lanc111.c.

#define NIC_MIR   (LANC111_BASE_ADDR + 0x08)

Bank 0 - Memory information register.

Definition at line 261 of file lanc111.c.

#define NIC_RPCR   (LANC111_BASE_ADDR + 0x0A)

Bank 0 - Receive / PHY control register.

Definition at line 266 of file lanc111.c.

#define RPCR_SPEED   0x2000

NIC_RPCR bit mask, PHY operates at 100 Mbps.

Definition at line 268 of file lanc111.c.

#define RPCR_DPLX   0x1000

NIC_RPCR bit mask, PHY operates at full duplex mode.

Definition at line 269 of file lanc111.c.

#define RPCR_ANEG   0x0800

NIC_RPCR bit mask, sets PHY in auto-negotiation mode.

Definition at line 270 of file lanc111.c.

#define RPCR_LEDA_PAT   0x0000

NIC_RPCR bit mask for LEDA mode.

Definition at line 271 of file lanc111.c.

#define RPCR_LEDB_PAT   0x0010

NIC_RPCR bit mask for LEDB mode.

Definition at line 272 of file lanc111.c.

#define NIC_CR   (LANC111_BASE_ADDR + 0x00)

Bank 1 - Configuration register.

Definition at line 277 of file lanc111.c.

#define CR_EPH_EN   0x8000

NIC_CR bit mask, .

Definition at line 279 of file lanc111.c.

#define NIC_BAR   (LANC111_BASE_ADDR + 0x02)

Bank 1 - Base address register.

Definition at line 284 of file lanc111.c.

#define NIC_IAR   (LANC111_BASE_ADDR + 0x04)

Bank 1 - Individual address register.

Definition at line 289 of file lanc111.c.

#define NIC_GPR   (LANC111_BASE_ADDR + 0x0A)

Bank 1 - General purpose register.

Definition at line 294 of file lanc111.c.

#define NIC_CTR   (LANC111_BASE_ADDR + 0x0C)

Bank 1 - Control register.

Definition at line 299 of file lanc111.c.

#define CTR_RCV_BAD   0x4000

NIC_CTR bit mask.

Definition at line 301 of file lanc111.c.

#define CTR_AUTO_RELEASE   0x0800

NIC_CTR bit mask, transmit packets automatically released.

Definition at line 302 of file lanc111.c.

#define NIC_MMUCR   (LANC111_BASE_ADDR + 0x00)

Bank 2 - MMU command register.

Definition at line 307 of file lanc111.c.

#define MMUCR_BUSY   0x0001

Definition at line 309 of file lanc111.c.

#define MMU_NOP   0

Definition at line 311 of file lanc111.c.

#define MMU_ALO   (1<<5)

Definition at line 312 of file lanc111.c.

#define MMU_RST   (2<<5)

Definition at line 313 of file lanc111.c.

#define MMU_REM   (3<<5)

Definition at line 314 of file lanc111.c.

#define MMU_TOP   (4<<5)

Definition at line 315 of file lanc111.c.

#define MMU_PKT   (5<<5)

Definition at line 316 of file lanc111.c.

#define MMU_ENQ   (6<<5)

Definition at line 317 of file lanc111.c.

#define MMU_RTX   (7<<5)

Definition at line 318 of file lanc111.c.

#define NIC_PNR   (LANC111_BASE_ADDR + 0x02)

Bank 2 - Packet number register.

This byte register specifies the accessible transmit packet number.

Definition at line 325 of file lanc111.c.

#define NIC_ARR   (LANC111_BASE_ADDR + 0x03)

Bank 2 - Allocation result register.

This byte register is updated upon a MMU_ALO command.

Definition at line 332 of file lanc111.c.

#define ARR_FAILED   0x80

Definition at line 334 of file lanc111.c.

#define NIC_FIFO   (LANC111_BASE_ADDR + 0x04)

Bank 2 - FIFO ports register.

Definition at line 339 of file lanc111.c.

#define NIC_PTR   (LANC111_BASE_ADDR + 0x06)

Bank 2 - Pointer register.

Definition at line 344 of file lanc111.c.

#define PTR_RCV   0x8000

Definition at line 346 of file lanc111.c.

#define PTR_AUTO_INCR   0x4000

Definition at line 347 of file lanc111.c.

#define PTR_READ   0x2000

Definition at line 348 of file lanc111.c.

#define PTR_ETEN   0x1000

Definition at line 349 of file lanc111.c.

#define PTR_NOT_EMPTY   0x0800

Definition at line 350 of file lanc111.c.

#define NIC_DATA   (LANC111_BASE_ADDR + 0x08)

Bank 2 - Data register.

Definition at line 355 of file lanc111.c.

#define NIC_IST   (LANC111_BASE_ADDR + 0x0C)

Bank 2 - Interrupt status register.

Definition at line 360 of file lanc111.c.

#define NIC_ACK   (LANC111_BASE_ADDR + 0x0C)

Bank 2 - Interrupt acknowledge register.

Definition at line 365 of file lanc111.c.

#define NIC_MSK   (LANC111_BASE_ADDR + 0x0D)

Bank 2 - Interrupt mask register.

Definition at line 370 of file lanc111.c.

Referenced by NicRxLanc().

#define INT_MD   0x80

PHY state change interrupt bit mask.

Definition at line 372 of file lanc111.c.

#define INT_ERCV   0x40

Early receive interrupt bit mask.

Definition at line 373 of file lanc111.c.

#define INT_EPH   0x20

Ethernet protocol interrupt bit mask.

Definition at line 374 of file lanc111.c.

#define INT_RX_OVRN   0x10

Receive overrun interrupt bit mask.

Definition at line 375 of file lanc111.c.

#define INT_ALLOC   0x08

Transmit allocation interrupt bit mask.

Definition at line 376 of file lanc111.c.

#define INT_TX_EMPTY   0x04

Transmitter empty interrupt bit mask.

Definition at line 377 of file lanc111.c.

#define INT_TX   0x02

Transmit complete interrupt bit mask.

Definition at line 378 of file lanc111.c.

#define INT_RCV   0x01

Receive interrupt bit mask.

Definition at line 379 of file lanc111.c.

#define NIC_MT   (LANC111_BASE_ADDR + 0x00)

Bank 3 - Multicast table register.

Definition at line 384 of file lanc111.c.

#define NIC_MGMT   (LANC111_BASE_ADDR + 0x08)

Bank 3 - Management interface register.

Definition at line 389 of file lanc111.c.

#define MGMT_MDOE   0x08

NIC_MGMT bit mask, enables MDO pin.

Definition at line 391 of file lanc111.c.

#define MGMT_MCLK   0x04

NIC_MGMT bit mask, drives MDCLK pin.

Definition at line 392 of file lanc111.c.

#define MGMT_MDI   0x02

NIC_MGMT bit mask, reflects MDI pin status.

Definition at line 393 of file lanc111.c.

#define MGMT_MDO   0x01

NIC_MGMT bit mask, drives MDO pin.

Definition at line 394 of file lanc111.c.

#define NIC_REV   (LANC111_BASE_ADDR + 0x0A)

Bank 3 - Revision register.

Definition at line 399 of file lanc111.c.

#define NIC_ERCV   (LANC111_BASE_ADDR + 0x0C)

Bank 3 - Early RCV register.

Definition at line 404 of file lanc111.c.

#define NIC_PHYCR   0

PHY control register.

Definition at line 409 of file lanc111.c.

#define PHYCR_RST   0x8000

NIC_PHYCR bit mask, resets PHY.

Definition at line 411 of file lanc111.c.

#define PHYCR_LPBK   0x4000

NIC_PHYCR bit mask, .

Definition at line 412 of file lanc111.c.

#define PHYCR_SPEED   0x2000

NIC_PHYCR bit mask, .

Definition at line 413 of file lanc111.c.

#define PHYCR_ANEG_EN   0x1000

NIC_PHYCR bit mask, .

Definition at line 414 of file lanc111.c.

#define PHYCR_PDN   0x0800

NIC_PHYCR bit mask, .

Definition at line 415 of file lanc111.c.

#define PHYCR_MII_DIS   0x0400

NIC_PHYCR bit mask, .

Definition at line 416 of file lanc111.c.

#define PHYCR_ANEG_RST   0x0200

NIC_PHYCR bit mask, .

Definition at line 417 of file lanc111.c.

#define PHYCR_DPLX   0x0100

NIC_PHYCR bit mask, .

Definition at line 418 of file lanc111.c.

#define PHYCR_COLST   0x0080

NIC_PHYCR bit mask, .

Definition at line 419 of file lanc111.c.

#define NIC_PHYSR   1

PHY status register.

Definition at line 425 of file lanc111.c.

#define PHYSR_CAP_T4   0x8000

NIC_PHYSR bit mask, indicates 100BASE-T4 capability.

Definition at line 427 of file lanc111.c.

#define PHYSR_CAP_TXF   0x4000

NIC_PHYSR bit mask, indicates 100BASE-TX full duplex capability.

Definition at line 428 of file lanc111.c.

#define PHYSR_CAP_TXH   0x2000

NIC_PHYSR bit mask, indicates 100BASE-TX half duplex capability.

Definition at line 429 of file lanc111.c.

#define PHYSR_CAP_TF   0x1000

NIC_PHYSR bit mask, indicates 10BASE-T full duplex capability.

Definition at line 430 of file lanc111.c.

#define PHYSR_CAP_TH   0x0800

NIC_PHYSR bit mask, indicates 10BASE-T half duplex capability.

Definition at line 431 of file lanc111.c.

#define PHYSR_CAP_SUPR   0x0040

NIC_PHYSR bit mask, indicates preamble suppression capability.

Definition at line 432 of file lanc111.c.

#define PHYSR_ANEG_ACK   0x0020

NIC_PHYSR bit mask, auto-negotiation completed.

Definition at line 433 of file lanc111.c.

#define PHYSR_REM_FLT   0x0010

NIC_PHYSR bit mask, remote fault detected.

Definition at line 434 of file lanc111.c.

#define PHYSR_CAP_ANEG   0x0008

NIC_PHYSR bit mask, indicates auto-negotiation capability.

Definition at line 435 of file lanc111.c.

#define PHYSR_LINK   0x0004

NIC_PHYSR bit mask, valid link status.

Definition at line 436 of file lanc111.c.

#define PHYSR_JAB   0x0002

NIC_PHYSR bit mask, jabber collision detected.

Definition at line 437 of file lanc111.c.

#define PHYSR_EXREG   0x0001

NIC_PHYSR bit mask, extended capabilities available.

Definition at line 438 of file lanc111.c.

#define NIC_PHYID1   2

PHY identifier register 1.

Definition at line 444 of file lanc111.c.

#define NIC_PHYID2   3

PHY identifier register 1.

Definition at line 449 of file lanc111.c.

#define NIC_PHYANAD   4

PHY auto-negotiation advertisement register.

Definition at line 454 of file lanc111.c.

#define PHYANAD_NP   0x8000

NIC_PHYANAD bit mask, exchanging next page information.

Definition at line 456 of file lanc111.c.

#define PHYANAD_ACK   0x4000

NIC_PHYANAD bit mask, acknowledged.

Definition at line 457 of file lanc111.c.

#define PHYANAD_RF   0x2000

NIC_PHYANAD bit mask, remote fault.

Definition at line 458 of file lanc111.c.

#define PHYANAD_T4   0x0200

NIC_PHYANAD bit mask, indicates 100BASE-T4 capability.

Definition at line 459 of file lanc111.c.

#define PHYANAD_TX_FDX   0x0100

NIC_PHYANAD bit mask, indicates 100BASE-TX full duplex capability.

Definition at line 460 of file lanc111.c.

#define PHYANAD_TX_HDX   0x0080

NIC_PHYANAD bit mask, indicates 100BASE-TX half duplex capability.

Definition at line 461 of file lanc111.c.

#define PHYANAD_10FDX   0x0040

NIC_PHYANAD bit mask, indicates 10BASE-T full duplex capability.

Definition at line 462 of file lanc111.c.

#define PHYANAD_10_HDX   0x0020

NIC_PHYANAD bit mask, indicates 10BASE-T half duplex capability.

Definition at line 463 of file lanc111.c.

#define PHYANAD_CSMA   0x0001

NIC_PHYANAD bit mask, indicates 802.3 CSMA capability.

Definition at line 464 of file lanc111.c.

#define NIC_PHYANRC   5

PHY auto-negotiation remote end capability register.

Definition at line 469 of file lanc111.c.

#define NIC_PHYCFR1   16

PHY configuration register 1.

Definition at line 474 of file lanc111.c.

#define NIC_PHYCFR2   17

PHY configuration register 2.

Definition at line 479 of file lanc111.c.

#define NIC_PHYSOR   18

PHY status output register.

Definition at line 484 of file lanc111.c.

#define PHYSOR_INT   0x8000

NIC_PHYSOR bit mask, interrupt bits changed.

Definition at line 486 of file lanc111.c.

#define PHYSOR_LNKFAIL   0x4000

NIC_PHYSOR bit mask, link failure detected.

Definition at line 487 of file lanc111.c.

#define PHYSOR_LOSSSYNC   0x2000

NIC_PHYSOR bit mask, descrambler sync lost detected.

Definition at line 488 of file lanc111.c.

#define PHYSOR_CWRD   0x1000

NIC_PHYSOR bit mask, code word error detected.

Definition at line 489 of file lanc111.c.

#define PHYSOR_SSD   0x0800

NIC_PHYSOR bit mask, start of stream error detected.

Definition at line 490 of file lanc111.c.

#define PHYSOR_ESD   0x0400

NIC_PHYSOR bit mask, end of stream error detected.

Definition at line 491 of file lanc111.c.

#define PHYSOR_RPOL   0x0200

NIC_PHYSOR bit mask, reverse polarity detected.

Definition at line 492 of file lanc111.c.

#define PHYSOR_JAB   0x0100

NIC_PHYSOR bit mask, jabber detected.

Definition at line 493 of file lanc111.c.

#define PHYSOR_SPDDET   0x0080

NIC_PHYSOR bit mask, 100/10 speed detected.

Definition at line 494 of file lanc111.c.

#define PHYSOR_DPLXDET   0x0040

NIC_PHYSOR bit mask, duplex detected.

Definition at line 495 of file lanc111.c.

#define NIC_PHYMSK   19

PHY mask register.

Definition at line 500 of file lanc111.c.

#define PHYMSK_MINT   0x8000

NIC_PHYMSK bit mask, enables PHYSOR_INT interrupt.

Definition at line 502 of file lanc111.c.

#define PHYMSK_MLNKFAIL   0x4000

NIC_PHYMSK bit mask, enables PHYSOR_LNKFAIL interrupt.

Definition at line 503 of file lanc111.c.

#define PHYMSK_MLOSSSYN   0x2000

NIC_PHYMSK bit mask, enables PHYSOR_LOSSSYNC interrupt.

Definition at line 504 of file lanc111.c.

#define PHYMSK_MCWRD   0x1000

NIC_PHYMSK bit mask, enables PHYSOR_CWRD interrupt.

Definition at line 505 of file lanc111.c.

#define PHYMSK_MSSD   0x0800

NIC_PHYMSK bit mask, enables PHYSOR_SSD interrupt.

Definition at line 506 of file lanc111.c.

#define PHYMSK_MESD   0x0400

NIC_PHYMSK bit mask, enables PHYSOR_ESD interrupt.

Definition at line 507 of file lanc111.c.

#define PHYMSK_MRPOL   0x0200

NIC_PHYMSK bit mask, enables PHYSOR_RPOL interrupt.

Definition at line 508 of file lanc111.c.

#define PHYMSK_MJAB   0x0100

NIC_PHYMSK bit mask, enables PHYSOR_JAB interrupt.

Definition at line 509 of file lanc111.c.

#define PHYMSK_MSPDDT   0x0080

NIC_PHYMSK bit mask, enables PHYSOR_SPDDET interrupt.

Definition at line 510 of file lanc111.c.

#define PHYMSK_MDPLDT   0x0040

NIC_PHYMSK bit mask, enables PHYSOR_DPLXDET interrupt.

Definition at line 511 of file lanc111.c.

#define MSBV ( bit   )     (1 << ((bit) - 8))

Definition at line 515 of file lanc111.c.

#define nic_outlb ( addr,
val   )     (*(volatile uint8_t *)(addr) = (val))

Definition at line 517 of file lanc111.c.

Referenced by NicRxLanc().

#define nic_outhb ( addr,
val   )     (*(volatile uint8_t *)((addr) + 1) = (val))

Definition at line 518 of file lanc111.c.

#define nic_outwx ( addr,
val   )     (*(volatile uint16_t *)(addr) = (val))

Definition at line 519 of file lanc111.c.

#define nic_outw ( addr,
val   ) 

Value:

{ \
    *(volatile uint8_t *)(addr) = (uint8_t)(val); \
    *((volatile uint8_t *)(addr) + 1) = (uint8_t)((val) >> 8); \
}

Definition at line 520 of file lanc111.c.

#define nic_inlb ( addr   )     (*(volatile uint8_t *)(addr))

Definition at line 525 of file lanc111.c.

Referenced by NicRxLanc().

#define nic_inhb ( addr   )     (*(volatile uint8_t *)((addr) + 1))

Definition at line 526 of file lanc111.c.

#define nic_inw ( addr   )     (*(volatile uint16_t *)(addr))

Definition at line 527 of file lanc111.c.

#define nic_bs ( bank   )     nic_outlb(NIC_BSR, bank)

Definition at line 529 of file lanc111.c.


Typedef Documentation

typedef struct _NICINFO NICINFO

Network interface controller information type.

Definition at line 550 of file lanc111.c.


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