dm9000e.c

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00001 /*
00002  * Copyright (C) 2008 by egnite GmbH. All rights reserved.
00003  * Copyright (C) 2003-2005 by egnite Software GmbH. All rights reserved.
00004  *
00005  * Redistribution and use in source and binary forms, with or without
00006  * modification, are permitted provided that the following conditions
00007  * are met:
00008  *
00009  * 1. Redistributions of source code must retain the above copyright
00010  *    notice, this list of conditions and the following disclaimer.
00011  * 2. Redistributions in binary form must reproduce the above copyright
00012  *    notice, this list of conditions and the following disclaimer in the
00013  *    documentation and/or other materials provided with the distribution.
00014  * 3. Neither the name of the copyright holders nor the names of
00015  *    contributors may be used to endorse or promote products derived
00016  *    from this software without specific prior written permission.
00017  *
00018  * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
00019  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00020  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00021  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
00022  * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
00023  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
00024  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
00025  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
00026  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00027  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
00028  * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
00029  * SUCH DAMAGE.
00030  *
00031  * For additional information see http://www.ethernut.de/
00032  *
00033  */
00034 
00035 /*
00036  * $Log$
00037  * Revision 1.12  2009/02/06 15:37:39  haraldkipp
00038  * Added stack space multiplier and addend. Adjusted stack space.
00039  *
00040  * Revision 1.11  2008/08/28 11:12:15  haraldkipp
00041  * Added interface flags, which will be required to implement Ethernet ioctl
00042  * functions.
00043  *
00044  * Revision 1.10  2008/08/11 06:59:07  haraldkipp
00045  * BSD types replaced by stdint types (feature request #1282721).
00046  *
00047  * Revision 1.9  2008/02/15 17:09:44  haraldkipp
00048  * Added support for the Elektor Internet Radio.
00049  *
00050  * Revision 1.8  2007/08/17 11:43:46  haraldkipp
00051  * Enable multicast.
00052  *
00053  * Revision 1.7  2007/05/24 07:26:44  haraldkipp
00054  * Added some delay befor reading the status of the received packet. Fixes
00055  * bug #1672527, thanks to Andreas Helmcke.
00056  *
00057  * Revision 1.6  2007/05/02 11:22:51  haraldkipp
00058  * Added multicast table entry.
00059  *
00060  * Revision 1.5  2006/06/28 17:10:15  haraldkipp
00061  * Include more general header file for ARM.
00062  *
00063  * Revision 1.4  2006/03/16 19:04:48  haraldkipp
00064  * Adding a short delay before reading the status word makes it work with
00065  * compiler optimization. On receiver overflow interrupts the chip is
00066  * declared insane. The output routine will no more enter NutEventWait()
00067  * on insane chips.
00068  *
00069  * Revision 1.3  2006/03/02 19:51:16  haraldkipp
00070  * Replaced GCC specific inline specifications with their portable
00071  * counterparts.
00072  *
00073  * Revision 1.2  2006/01/23 17:33:14  haraldkipp
00074  * Possible memory alignment problem may start network interface too early.
00075  *
00076  * Revision 1.1  2005/10/24 08:49:05  haraldkipp
00077  * Initial check in.
00078  *
00079  */
00080 
00081 #include <cfg/os.h>
00082 #include <arch/arm.h>
00083 
00084 #include <string.h>
00085 
00086 #include <sys/atom.h>
00087 #include <sys/heap.h>
00088 #include <sys/thread.h>
00089 #include <sys/event.h>
00090 #include <sys/timer.h>
00091 #include <sys/confnet.h>
00092 
00093 #include <netinet/if_ether.h>
00094 #include <net/ether.h>
00095 #include <net/if_var.h>
00096 
00097 #include <dev/irqreg.h>
00098 #include <dev/dm9000e.h>
00099 
00100 #ifdef NUTDEBUG
00101 #include <stdio.h>
00102 #endif
00103 
00104 #ifndef NUT_THREAD_NICRXSTACK
00105 /* arm-elf-gcc size optimized code used 160 bytes. */
00106 #define NUT_THREAD_NICRXSTACK   384
00107 #endif
00108 
00109 /*
00110  * Determine ports, which had not been explicitely configured.
00111  */
00112 #if defined(ETHERNUT3)
00113 
00114 #ifndef NIC_BASE_ADDR
00115 #define NIC_BASE_ADDR   0x20000000
00116 #endif
00117 
00118 #ifndef NIC_SIGNAL_IRQ
00119 #define NIC_SIGNAL_IRQ  INT1
00120 #endif
00121 
00122 #ifndef NIC_SIGNAL_PDR
00123 #define NIC_SIGNAL_PDR  PIO_PDR
00124 #endif
00125 
00126 #ifndef NIC_SIGNAL_BIT
00127 #define NIC_SIGNAL_BIT  10
00128 #endif
00129 
00130 #elif defined(ELEKTOR_IR1)
00131 
00132 #ifndef NIC_BASE_ADDR
00133 #define NIC_BASE_ADDR   0x30000000
00134 #endif
00135 
00136 #ifndef NIC_SIGNAL_IRQ
00137 #define NIC_SIGNAL_IRQ  INT0
00138 #endif
00139 
00140 #ifndef NIC_SIGNAL_PDR
00141 #define NIC_SIGNAL_PDR  PIOB_PDR
00142 #endif
00143 
00144 #ifndef NIC_SIGNAL_XSR
00145 #define NIC_SIGNAL_XSR  PIOB_ASR
00146 #endif
00147 
00148 #ifndef NIC_SIGNAL_BIT
00149 #define NIC_SIGNAL_BIT  PB20_IRQ0_A
00150 #endif
00151 
00152 #endif
00153 
00154 #ifdef NIC_BASE_ADDR
00155 
00156 #ifndef NIC_DATA_ADDR
00157 #define NIC_DATA_ADDR   (NIC_BASE_ADDR + 4)
00158 #endif
00159 
00160 #define INT0    0
00161 #define INT1    1
00162 #define INT2    2
00163 #define INT3    3
00164 #define INT4    4
00165 #define INT5    5
00166 #define INT6    6
00167 #define INT7    7
00168 
00169 #ifdef NIC_RESET_BIT
00170 
00171 #if (NIC_RESET_AVRPORT == AVRPORTB)
00172 #define NIC_RESET_PORT   PORTB
00173 #define NIC_RESET_DDR    DDRB
00174 
00175 #elif (NIC_RESET_AVRPORT == AVRPORTD)
00176 #define NIC_RESET_PORT   PORTD
00177 #define NIC_RESET_DDR    DDRD
00178 
00179 #elif (NIC_RESET_AVRPORT == AVRPORTE)
00180 #define NIC_RESET_PORT   PORTE
00181 #define NIC_RESET_DDR    DDRE
00182 
00183 #elif (NIC_RESET_AVRPORT == AVRPORTF)
00184 #define NIC_RESET_PORT   PORTF
00185 #define NIC_RESET_DDR    DDRF
00186 
00187 #endif                          /* NIC_RESET_AVRPORT */
00188 
00189 #endif                          /* NIC_RESET_BIT */
00190 
00191 /*
00192  * Determine interrupt settings.
00193  * DOES NOT WORK
00194  */
00195 #if (NIC_SIGNAL_IRQ == INT0)
00196 #define NIC_SIGNAL          sig_INTERRUPT0
00197 
00198 #elif (NIC_SIGNAL_IRQ == INT2)
00199 #define NIC_SIGNAL          sig_INTERRUPT2
00200 
00201 #elif (NIC_SIGNAL_IRQ == INT3)
00202 #define NIC_SIGNAL          sig_INTERRUPT3
00203 
00204 #elif (NIC_SIGNAL_IRQ == INT4)
00205 #define NIC_SIGNAL          sig_INTERRUPT4
00206 
00207 #elif (NIC_SIGNAL_IRQ == INT5)
00208 #define NIC_SIGNAL          sig_INTERRUPT5
00209 
00210 #elif (NIC_SIGNAL_IRQ == INT6)
00211 #define NIC_SIGNAL          sig_INTERRUPT6
00212 
00213 #elif (NIC_SIGNAL_IRQ == INT7)
00214 #define NIC_SIGNAL          sig_INTERRUPT7
00215 
00216 #else
00217 #define NIC_SIGNAL          sig_INTERRUPT1
00218 
00219 #endif
00220 
00225 
00226 #define NIC_NCR     0x00        /* Network control register (0x00). */
00227 #define NIC_NCR_LBM     0x06    /* Loopback mode. */
00228 #define NIC_NCR_LBNORM  0x00    /* Normal mode. */
00229 #define NIC_NCR_LBMAC   0x02    /* MAC loopback. */
00230 #define NIC_NCR_LBPHY   0x04    /* PHY loopback. */
00231 #define NIC_NCR_RST     0x01    /* Software reset, auto clear. */
00232 
00233 #define NIC_NSR     0x01        /* Network status register (0x00). */
00234 #define NIC_NSR_SPEED   0x80
00235 #define NIC_NSR_LINKST  0x40
00236 #define NIC_NSR_WAKEST  0x20
00237 #define NIC_NSR_TX2END  0x08
00238 #define NIC_NSR_TX1END  0x04
00239 #define NIC_NSR_RXOV    0x02
00240 
00241 #define NIC_TCR     0x02        /* TX control register (0x00). */
00242 #define NIC_TCR_TXREQ    0x01   /* TX request */
00243 
00244 #define NIC_TSR1    0x03        /* TX status register I (0x00). */
00245 
00246 #define NIC_TSR2    0x04        /* TX status register II (0x00). */
00247 
00248 #define NIC_RCR     0x05        /* RX control register (0x00). */
00249 #define NIC_RCR_DIS_LONG 0x20   /* Discard long packets. */
00250 #define NIC_RCR_DIS_CRC 0x10    /* Discard CRC error packets. */
00251 #define NIC_RCR_ALL     0x08    /* Pass all multicast */
00252 #define NIC_RCR_PRMSC   0x02    /* Enable promiscuous mode. */
00253 #define NIC_RCR_RXEN    0x01    /* Enable receiver. */
00254 
00255 #define NIC_RSR     0x06        /* RX status register (0x00). */
00256 #define NIC_RSR_ERRORS  0xBF    /* Error bit mask. */
00257 #define NIC_RSR_RF      0x80    /* Runt frame. */
00258 #define NIC_RSR_MF      0x40    /* Multicast frame. */
00259 #define NIC_RSR_LCS     0x20    /* Late collision. */
00260 #define NIC_RSR_RWTO    0x10    /* Receiver watchdog time out. */
00261 #define NIC_RSR_PLE     0x08    /* Physical layer error. */
00262 #define NIC_RSR_AE      0x04    /* Alignment error. */
00263 #define NIC_RSR_CE      0x02    /* CRC error. */
00264 #define NIC_RSR_FOE     0x01    /* FIFO overflow error. */
00265 
00266 #define NIC_ROCR    0x07        /* Receive overflow counter register (0x00). */
00267 
00268 #define NIC_BPTR    0x08        /* Back pressure threshold register (0x37). */
00269 
00270 #define NIC_FCTR    0x09        /* Flow control threshold register (0x38). */
00271 
00272 #define NIC_FCR     0x0A        /* RX flow control register (0x00). */
00273 
00274 #define NIC_EPCR    0x0B        /* EEPROM and PHY control register. */
00275 
00276 #define NIC_EPAR    0x0C        /* EEPROM and PHY address register. */
00277 
00278 #define NIC_EPDRL   0x0D        /* EEPROM and PHY low byte data register. */
00279 
00280 #define NIC_EPDRH   0x0E        /* EEPROM and PHY high byte data register. */
00281 
00282 #define NIC_WCR     0x0F        /* Wake up control register (0x00). */
00283 
00284 #define NIC_PAR     0x10        /* 6 byte physical address register. */
00285 
00286 #define NIC_MAR     0x16        /* 8 byte multicast address register. */
00287 
00288 #define NIC_GPCR    0x1E        /* General purpose control register (?). */
00289 
00290 #define NIC_GPR     0x1F        /* General purpose register (?). */
00291 
00292 #define NIC_TRPA    0x22        /* 2 byte TX SRAM read pointer address, low/high (0x0000). */
00293 
00294 #define NIC_RWPA    0x24        /* 2 byte RX SRAM write pointer address, low/high (0x0000). */
00295 
00296 #define NIC_VID     0x28        /* 2 byte vendor ID (0x0A46). */
00297 
00298 #define NIC_PID     0x2A        /* 2 byte product ID (0x0900). */
00299 
00300 #define NIC_CHIPR   0x2C        /* Chip revision (0x00). */
00301 
00302 #define NIC_SMCR    0x2F        /* Special mode register (0x00). */
00303 
00304 #define NIC_MRCMDX  0xF0        /* Memory data read command w/o increment (?). */
00305 
00306 #define NIC_MRCMD   0xF2        /* Memory data read command with increment (?). */
00307 
00308 #define NIC_MRR     0xF4        /* 2 byte memory data read register, low/high (?). */
00309 
00310 #define NIC_MWCMDX  0xF6        /* Memory data write command register w/o increment (?). */
00311 
00312 #define NIC_MWCMD   0xF8        /* Memory data write command register with increment (?). */
00313 
00314 #define NIC_MWR     0xFA        /* Memory data write command register with increment (?). */
00315 
00316 #define NIC_TXPL    0xFC        /* 2 byte TX packet length register. (?). */
00317 
00318 #define NIC_ISR     0xFE        /* Interrupt status register (0x00). */
00319 #define NIC_ISR_IOM     0xC0    /* I/O mode mask */
00320 #define NIC_ISR_M16     0x00    /* 16-bit I/O mode */
00321 #define NIC_ISR_M32     0x40    /* 32-bit I/O mode */
00322 #define NIC_ISR_M8      0x80    /* 8-bit I/O mode */
00323 #define NIC_ISR_ROOS    0x08    /* Receiver overflow counter interrupt. */
00324 #define NIC_ISR_ROS     0x04    /* Receiver overflow interrupt. */
00325 #define NIC_ISR_PTS     0x02    /* Transmitter interrupt. */
00326 #define NIC_ISR_PRS     0x01    /* Receiver interrupt. */
00327 
00328 #define NIC_IMR     0xFF        /* Interrupt mask register (0x00). */
00329 #define NIC_IMR_PAR     0x80    /* Enable read/write pointer wrap around. */
00330 #define NIC_IMR_ROOM    0x08    /* Enable receiver overflow counter interrupts. */
00331 #define NIC_IMR_ROM     0x04    /* Enable receiver overflow interrupts. */
00332 #define NIC_IMR_PTM     0x02    /* Enable transmitter interrupts. */
00333 #define NIC_IMR_PRM     0x01    /* Enable receiver interrupts. */
00334 
00335 #define NIC_PHY_BMCR    0x00    /* Basic mode control register. */
00336 
00337 #define NIC_PHY_BMSR    0x01    /* Basic mode status register. */
00338 #define NIC_PHY_BMSR_ANCOMPL    0x0020  /* Auto negotiation complete. */
00339 #define NIC_PHY_BMSR_LINKSTAT   0x0004  /* Link status. */
00340 
00341 #define NIC_PHY_ID1     0x02    /* PHY identifier register 1. */
00342 
00343 #define NIC_PHY_ID2     0x03    /* PHY identifier register 2. */
00344 
00345 #define NIC_PHY_ANAR    0x04    /* Auto negotiation advertisement register. */
00346 
00347 #define NIC_PHY_ANLPAR  0x05    /* Auto negotiation link partner availability register. */
00348 
00349 #define NIC_PHY_ANER    0x06    /* Auto negotiation expansion register. */
00350 
00351 #define NIC_PHY_DSCR    0x10    /* Davicom specified configuration register. */
00352 
00353 #define NIC_PHY_DSCSR   0x11    /* Davicom specified configuration and status register. */
00354 
00355 #define NIC_PHY_10BTCSR 0x12    /* 10BASE-T configuration and status register. */
00356 
00360 struct _NICINFO {
00361 #ifdef NUT_PERFMON
00362     uint32_t ni_rx_packets;       
00363     uint32_t ni_tx_packets;       
00364     uint32_t ni_overruns;         
00365     uint32_t ni_rx_frame_errors;  
00366     uint32_t ni_rx_crc_errors;    
00367     uint32_t ni_rx_missed_errors; 
00368 #endif
00369     HANDLE volatile ni_rx_rdy;  
00370     HANDLE volatile ni_tx_rdy;  
00371     HANDLE ni_mutex;            
00372     volatile int ni_tx_queued;  
00373     volatile int ni_tx_quelen;  
00374     volatile int ni_insane;     
00375     int ni_iomode;              
00376 };
00377 
00381 typedef struct _NICINFO NICINFO;
00382 
00389 
00390 
00391 static INLINE void nic_outb(uint8_t reg, uint8_t val)
00392 {
00393     outb(NIC_BASE_ADDR, reg);
00394     outb(NIC_DATA_ADDR, val);
00395 }
00396 
00397 static INLINE uint8_t nic_inb(uint16_t reg)
00398 {
00399     outb(NIC_BASE_ADDR, reg);
00400     return inb(NIC_DATA_ADDR);
00401 }
00402 
00410 static uint16_t phy_inw(uint8_t reg)
00411 {
00412     /* Select PHY register */
00413     nic_outb(NIC_EPAR, 0x40 | reg);
00414 
00415     /* PHY read command. */
00416     nic_outb(NIC_EPCR, 0x0C);
00417     NutDelay(1);
00418     nic_outb(NIC_EPCR, 0x00);
00419 
00420     /* Get data from PHY data register. */
00421     return ((uint16_t) nic_inb(NIC_EPDRH) << 8) | (uint16_t) nic_inb(NIC_EPDRL);
00422 }
00423 
00432 static void phy_outw(uint8_t reg, uint16_t val)
00433 {
00434     /* Select PHY register */
00435     nic_outb(NIC_EPAR, 0x40 | reg);
00436 
00437     /* Store value in PHY data register. */
00438     nic_outb(NIC_EPDRL, (uint8_t) val);
00439     nic_outb(NIC_EPDRH, (uint8_t) (val >> 8));
00440 
00441     /* PHY write command. */
00442     nic_outb(NIC_EPCR, 0x0A);
00443     NutDelay(1);
00444     nic_outb(NIC_EPCR, 0x00);
00445 }
00446 
00447 static int NicPhyInit(void)
00448 {
00449     /* Restart auto negotiation. */
00450     phy_outw(NIC_PHY_ANAR, 0x01E1);
00451     phy_outw(NIC_PHY_BMCR, 0x1200);
00452 
00453     nic_outb(NIC_GPCR, 1);
00454     nic_outb(NIC_GPR, 0);
00455 
00456     return 0;
00457 }
00458 
00464 static int NicReset(void)
00465 {
00466     /* Hardware reset. */
00467 #ifdef undef_NIC_RESET_BIT
00468     sbi(NIC_RESET_DDR, NIC_RESET_BIT);
00469     sbi(NIC_RESET_PORT, NIC_RESET_BIT);
00470     NutDelay(WAIT100);
00471     cbi(NIC_RESET_PORT, NIC_RESET_BIT);
00472     NutDelay(WAIT250);
00473     NutDelay(WAIT250);
00474 #else
00475     /* Software reset. */
00476     nic_outb(NIC_NCR, NIC_NCR_RST | NIC_NCR_LBMAC);
00477     NutDelay(1);
00478     /* FIXME: Delay required. */
00479 #endif
00480 
00481     return NicPhyInit();
00482 }
00483 
00484 /*
00485  * NIC interrupt entry.
00486  */
00487 static void NicInterrupt(void *arg)
00488 {
00489     uint8_t isr;
00490     NICINFO *ni = (NICINFO *) ((NUTDEVICE *) arg)->dev_dcb;
00491 
00492     /* Read interrupt status and disable interrupts. */
00493     isr = nic_inb(NIC_ISR);
00494 
00495     /* Receiver interrupt. */
00496     if (isr & NIC_ISR_PRS) {
00497         nic_outb(NIC_ISR, NIC_ISR_PRS);
00498         NutEventPostFromIrq(&ni->ni_rx_rdy);
00499     }
00500 
00501     /* Transmitter interrupt. */
00502     if (isr & NIC_ISR_PTS) {
00503         if (ni->ni_tx_queued) {
00504             if (ni->ni_tx_quelen) {
00505                 /* Initiate transfer of a queued packet. */
00506                 nic_outb(NIC_TXPL, (uint8_t) ni->ni_tx_quelen);
00507                 nic_outb(NIC_TXPL + 1, (uint8_t) (ni->ni_tx_quelen >> 8));
00508                 ni->ni_tx_quelen = 0;
00509                 nic_outb(NIC_TCR, NIC_TCR_TXREQ);
00510             }
00511             ni->ni_tx_queued--;
00512         }
00513         nic_outb(NIC_ISR, NIC_ISR_PTS);
00514         NutEventPostFromIrq(&ni->ni_tx_rdy);
00515     }
00516 
00517     /* Receiver overflow interrupt. */
00518     if (isr & NIC_ISR_ROS) {
00519         nic_outb(NIC_ISR, NIC_ISR_ROS);
00520         ni->ni_insane = 1;
00521         NutEventPostFromIrq(&ni->ni_rx_rdy);
00522     }
00523 
00524     /* Receiver overflow counter interrupt. */
00525     if (isr & NIC_ISR_ROOS) {
00526         nic_outb(NIC_ISR, NIC_ISR_ROOS);
00527         NutEventPostFromIrq(&ni->ni_rx_rdy);
00528     }
00529 }
00530 
00536 static void NicWrite8(uint8_t * buf, uint16_t len)
00537 {
00538     while (len--) {
00539         outb(NIC_DATA_ADDR, *buf);
00540         buf++;
00541     }
00542 }
00543 
00549 static void NicWrite16(uint8_t * buf, uint16_t len)
00550 {
00551     uint16_t *wp = (uint16_t *) buf;
00552 
00553     len = (len + 1) / 2;
00554     while (len--) {
00555         outw(NIC_DATA_ADDR, *wp);
00556         wp++;
00557     }
00558 }
00559 
00565 static void NicRead8(uint8_t * buf, uint16_t len)
00566 {
00567     while (len--) {
00568         *buf++ = inb(NIC_DATA_ADDR);
00569     }
00570 }
00571 
00577 static void NicRead16(uint8_t * buf, uint16_t len)
00578 {
00579     uint16_t *wp = (uint16_t *) buf;
00580 
00581     len = (len + 1) / 2;
00582     while (len--) {
00583         *wp++ = inw(NIC_DATA_ADDR);
00584     }
00585 }
00586 
00595 static int NicGetPacket(NICINFO * ni, NETBUF ** nbp)
00596 {
00597     int rc = -1;
00598     uint16_t fsw;
00599     uint16_t fbc;
00600 
00601     *nbp = NULL;
00602 
00603     /* Disable NIC interrupts. */
00604     NutIrqDisable(&NIC_SIGNAL);
00605 
00606     /* 
00607      * Read the status word w/o auto increment. If zero, no packet is 
00608      * available. Otherwise it should be set to one. Any other value 
00609      * indicates a weird chip crying for reset.
00610      */
00611     nic_inb(NIC_MRCMDX);
00612     /* Add some delay befor reading the status of the received packet. */
00613     _NOP(); _NOP(); _NOP(); _NOP();
00614     fsw = inb(NIC_DATA_ADDR);
00615     if (fsw > 1) {
00616         ni->ni_insane = 1;
00617     } else if (fsw) {
00618         /* Now read status word and byte count with auto increment. */
00619         outb(NIC_BASE_ADDR, NIC_MRCMD);
00620         if (ni->ni_iomode == NIC_ISR_M16) {
00621             fsw = inw(NIC_DATA_ADDR);
00622             _NOP(); _NOP(); _NOP(); _NOP();
00623             fbc = inw(NIC_DATA_ADDR);
00624         } else {
00625             fsw = inb(NIC_DATA_ADDR) + ((uint16_t) inb(NIC_DATA_ADDR) << 8);
00626             _NOP(); _NOP(); _NOP(); _NOP();
00627             fbc = inb(NIC_DATA_ADDR) + ((uint16_t) inb(NIC_DATA_ADDR) << 8);
00628         }
00629 
00630         /*
00631          * Receiving long packets is unexpected, because we disabled 
00632          * this during initialization. Let's declare the chip insane.
00633          * Short packets will be handled by the caller.
00634          */
00635         if (fbc > 1536) {
00636             ni->ni_insane = 1;
00637         } else {
00638             /*
00639              * The high byte of the status word contains a copy of the 
00640              * receiver status register.
00641              */
00642             fsw >>= 8;
00643             fsw &= NIC_RSR_ERRORS;
00644 #ifdef NUT_PERMON
00645             /* Update statistics. */
00646             if (fsw) {
00647                 if (RxStatus & NIC_RSR_CE) {
00648                     ni->ni_crc_errors++;
00649                 } else if (RxStatus & NIC_RSR_FOE) {
00650                     ni->ni_overruns++;
00651                 } else {
00652                     ni->ni_rx_missed_errors++;
00653                 }
00654             } else {
00655                 ni->ni_rx_packets++;
00656             }
00657 #endif
00658             /* 
00659              * If we got an error packet or failed to allocated the
00660              * buffer, then silently discard the packet.
00661              */
00662             if (fsw || (*nbp = NutNetBufAlloc(0, NBAF_DATALINK, fbc - 4)) == NULL) {
00663                 if (ni->ni_iomode == NIC_ISR_M16) {
00664                     fbc = (fbc + 1) / 2;
00665                     while (fbc--) {
00666                         fsw = inw(NIC_DATA_ADDR);
00667                     }
00668                 } else {
00669                     while (fbc--) {
00670                         fsw = inb(NIC_DATA_ADDR);
00671                     }
00672                 }
00673             } else {
00674                 if (ni->ni_iomode == NIC_ISR_M16) {
00675                     /* Read packet data from 16 bit bus. */
00676                     NicRead16((*nbp)->nb_dl.vp, (*nbp)->nb_dl.sz);
00677                     /* Read packet CRC. */
00678                     fsw = inw(NIC_DATA_ADDR);
00679                     fsw = inw(NIC_DATA_ADDR);
00680                 } else {
00681                     /* Read packet data from 8 bit bus. */
00682                     NicRead8((*nbp)->nb_dl.vp, (*nbp)->nb_dl.sz);
00683                     /* Read packet CRC. */
00684                     fsw = inb(NIC_DATA_ADDR);
00685                     fsw = inb(NIC_DATA_ADDR);
00686                     fsw = inb(NIC_DATA_ADDR);
00687                     fsw = inb(NIC_DATA_ADDR);
00688                 }
00689                 /* Return success. */
00690                 rc = 0;
00691             }
00692         }
00693     }
00694 
00695     /* Enable NIC interrupts if the chip is sane. */
00696     if (ni->ni_insane == 0) {
00697         NutIrqEnable(&NIC_SIGNAL);
00698     }
00699     return rc;
00700 }
00701 
00714 static int NicPutPacket(NICINFO * ni, NETBUF * nb)
00715 {
00716     int rc = -1;
00717     uint16_t sz;
00718 
00719     /*
00720      * Calculate the number of bytes to be send. Do not send packets 
00721      * larger than the Ethernet maximum transfer unit. The MTU
00722      * consist of 1500 data bytes plus the 14 byte Ethernet header
00723      * plus 4 bytes CRC. We check the data bytes only.
00724      */
00725     if ((sz = nb->nb_nw.sz + nb->nb_tp.sz + nb->nb_ap.sz) > ETHERMTU) {
00726         return -1;
00727     }
00728     sz += nb->nb_dl.sz;
00729     if (sz & 1) {
00730         sz++;
00731     }
00732 
00733     /* Disable interrupts. */
00734     NutIrqDisable(&NIC_SIGNAL);
00735 
00736     /* TODO: Check for link. */
00737     if (ni->ni_insane == 0) {
00738         /* Enable data write. */
00739         outb(NIC_BASE_ADDR, NIC_MWCMD);
00740 
00741         /* Transfer the Ethernet frame. */
00742         if (ni->ni_iomode == NIC_ISR_M16) {
00743             NicWrite16(nb->nb_dl.vp, nb->nb_dl.sz);
00744             NicWrite16(nb->nb_nw.vp, nb->nb_nw.sz);
00745             NicWrite16(nb->nb_tp.vp, nb->nb_tp.sz);
00746             NicWrite16(nb->nb_ap.vp, nb->nb_ap.sz);
00747         } else {
00748             NicWrite8(nb->nb_dl.vp, nb->nb_dl.sz);
00749             NicWrite8(nb->nb_nw.vp, nb->nb_nw.sz);
00750             NicWrite8(nb->nb_tp.vp, nb->nb_tp.sz);
00751             NicWrite8(nb->nb_ap.vp, nb->nb_ap.sz);
00752         }
00753 
00754         /* If no packet is queued, start the transmission. */
00755         if (ni->ni_tx_queued == 0) {
00756             nic_outb(NIC_TXPL, (uint8_t) sz);
00757             nic_outb(NIC_TXPL + 1, (uint8_t) (sz >> 8));
00758             nic_outb(NIC_TCR, NIC_TCR_TXREQ);
00759         }
00760         /* ...otherwise mark this packet queued. */
00761         else {
00762             ni->ni_tx_quelen = sz;
00763         }
00764         ni->ni_tx_queued++;
00765         rc = 0;
00766 #ifdef NUT_PERFMON
00767         ni->ni_tx_packets++;
00768 #endif
00769     }
00770 
00771     /* Enable interrupts. */
00772     NutIrqEnable(&NIC_SIGNAL);
00773 
00774     /* If the controller buffer is filled with two packets, then
00775        wait for the first being sent out. */
00776     if (rc == 0 && ni->ni_tx_queued > 1) {
00777         NutEventWait(&ni->ni_tx_rdy, 500);
00778     }
00779     return rc;
00780 }
00781 
00789 static int NicStart(CONST uint8_t * mac)
00790 {
00791     int i;
00792     int link_wait = 20;
00793 
00794     /* Power up the PHY. */
00795     nic_outb(NIC_GPR, 0);
00796     NutDelay(5);
00797 
00798     /* Software reset with MAC loopback. */
00799     nic_outb(NIC_NCR, NIC_NCR_RST | NIC_NCR_LBMAC);
00800     NutDelay(5);
00801     nic_outb(NIC_NCR, NIC_NCR_RST | NIC_NCR_LBMAC);
00802     NutDelay(5);
00803 
00804     /* 
00805      * PHY power down followed by PHY power up. This should activate 
00806      * the auto sense link.
00807      */
00808     nic_outb(NIC_GPR, 1);
00809     nic_outb(NIC_GPR, 0);
00810 
00811     /* Set MAC address. */
00812     for (i = 0; i < 6; i++) {
00813         nic_outb(NIC_PAR + i, mac[i]);
00814     }
00815 
00816     /* Enable broadcast receive. */
00817     for (i = 0; i < 7; i++) {
00818         nic_outb(NIC_MAR + i, 0);
00819     }
00820     nic_outb(NIC_MAR + 7, 0x80);
00821 
00822     /* Clear interrupts. */
00823     nic_outb(NIC_ISR, NIC_ISR_ROOS | NIC_ISR_ROS | NIC_ISR_PTS | NIC_ISR_PRS);
00824 
00825     /* Enable late collision retries on the DM9000A. */
00826     if (nic_inb(NIC_CHIPR) == 0x19) {
00827         nic_outb(0x2D, 0x40);
00828     }
00829 
00830     /* Enable receiver. */
00831     nic_outb(NIC_RCR, NIC_RCR_DIS_LONG | NIC_RCR_DIS_CRC | NIC_RCR_RXEN | NIC_RCR_ALL);
00832 
00833     /* Wait for link. */
00834     for (link_wait = 20;; link_wait--) {
00835         if (phy_inw(NIC_PHY_BMSR) & NIC_PHY_BMSR_ANCOMPL) {
00836             break;
00837         }
00838         if (link_wait == 0) {
00839             return -1;
00840         }
00841         NutSleep(200);
00842     }
00843 
00844     /* Enable interrupts. */
00845     nic_outb(NIC_IMR, NIC_IMR_PAR | NIC_IMR_PTM | NIC_IMR_PRM);
00846 
00847     return 0;
00848 }
00849 
00854 THREAD(NicRxLanc, arg)
00855 {
00856     NUTDEVICE *dev;
00857     IFNET *ifn;
00858     NICINFO *ni;
00859     NETBUF *nb;
00860 
00861     dev = arg;
00862     ifn = (IFNET *) dev->dev_icb;
00863     ni = (NICINFO *) dev->dev_dcb;
00864 
00865     /*
00866      * This is a temporary hack. Due to a change in initialization,
00867      * we may not have got a MAC address yet. Wait until one has been
00868      * set.
00869      */
00870     for (;;) {
00871         int i;
00872 
00873         for (i = 0; i < sizeof(ifn->if_mac); i++) {
00874             if (ifn->if_mac[i] && ifn->if_mac[i] != 0xFF) {
00875                 break;
00876             }
00877         }
00878         if (i < sizeof(ifn->if_mac)) {
00879             break;
00880         }
00881         NutSleep(63);
00882     }
00883 
00884     /*
00885      * Do not continue unless we managed to start the NIC. We are
00886      * trapped here if the Ethernet link cannot be established.
00887      * This happens, for example, if no Ethernet cable is plugged
00888      * in.
00889      */
00890     while (NicStart(ifn->if_mac)) {
00891         NutSleep(1000);
00892     }
00893 
00894     /* Initialize the access mutex. */
00895     NutEventPost(&ni->ni_mutex);
00896 
00897     /* Run at high priority. */
00898     NutThreadSetPriority(9);
00899 
00900     /* Enable interrupts. */
00901 #ifdef NIC_SIGNAL_XSR
00902     outr(NIC_SIGNAL_XSR, _BV(NIC_SIGNAL_BIT));
00903 #if defined(ELEKTOR_IR1)
00904     /* Ugly code alarm: Should be configurable. */
00905     outr(PMC_PCER, _BV(IRQ0_ID));
00906 #endif
00907 #endif
00908     outr(NIC_SIGNAL_PDR, _BV(NIC_SIGNAL_BIT));
00909     NutIrqEnable(&NIC_SIGNAL);
00910 #if defined(ELEKTOR_IR1)
00911     /* Ugly code alarm: Should be configurable. */
00912     NutIrqSetMode(&NIC_SIGNAL, NUT_IRQMODE_HIGHLEVEL);
00913 #endif
00914 
00915     for (;;) {
00916         /*
00917          * Wait for the arrival of new packets or poll the receiver 
00918          * every two seconds.
00919          */
00920         NutEventWait(&ni->ni_rx_rdy, 2000);
00921 
00922         /*
00923          * Fetch all packets from the NIC's internal buffer and pass 
00924          * them to the registered handler.
00925          */
00926         while (NicGetPacket(ni, &nb) == 0) {
00927 
00928             /* Discard short packets. */
00929             if (nb->nb_dl.sz < 60) {
00930                 NutNetBufFree(nb);
00931             } else {
00932                 (*ifn->if_recv) (dev, nb);
00933             }
00934         }
00935 
00936         /* We got a weird chip, try to restart it. */
00937         while (ni->ni_insane) {
00938             if (NicStart(ifn->if_mac) == 0) {
00939                 ni->ni_insane = 0;
00940                 ni->ni_tx_queued = 0;
00941                 ni->ni_tx_quelen = 0;
00942                 NutIrqEnable(&NIC_SIGNAL);
00943             } else {
00944                 NutSleep(1000);
00945             }
00946         }
00947     }
00948 }
00949 
00960 int DmOutput(NUTDEVICE * dev, NETBUF * nb)
00961 {
00962     static uint32_t mx_wait = 5000;
00963     int rc = -1;
00964     NICINFO *ni = (NICINFO *) dev->dev_dcb;
00965 
00966     /*
00967      * After initialization we are waiting for a long time to give
00968      * the PHY a chance to establish an Ethernet link.
00969      */
00970     while (rc) {
00971         if (ni->ni_insane) {
00972             break;
00973         }
00974         if (NutEventWait(&ni->ni_mutex, mx_wait)) {
00975             break;
00976         }
00977 
00978         /* Check for packet queue space. */
00979         if (ni->ni_tx_queued > 1) {
00980             if (NutEventWait(&ni->ni_tx_rdy, 500)) {
00981                 /* No queue space. Release the lock and give up. */
00982                 NutEventPost(&ni->ni_mutex);
00983                 break;
00984             }
00985         } else if (NicPutPacket(ni, nb) == 0) {
00986             /* Ethernet works. Set a long waiting time in case we
00987                temporarly lose the link next time. */
00988             rc = 0;
00989             mx_wait = 5000;
00990         }
00991         NutEventPost(&ni->ni_mutex);
00992     }
00993     /*
00994      * Probably no Ethernet link. Significantly reduce the waiting
00995      * time, so following transmission will soon return an error.
00996      */
00997     if (rc) {
00998         mx_wait = 500;
00999     }
01000     return rc;
01001 }
01002 
01020 int DmInit(NUTDEVICE * dev)
01021 {
01022     uint32_t id;
01023     NICINFO *ni = (NICINFO *) dev->dev_dcb;
01024 
01025 #if defined(ELEKTOR_IR1)
01026     outr(PIOA_BSR, _BV(PA20_NCS2_B));
01027     outr(PIOA_PDR, _BV(PA20_NCS2_B));
01028     outr(PIOC_BSR, _BV(PC16_NWAIT_B) | _BV(PC21_NWR0_B) | _BV(PC22_NRD_B));
01029     outr(PIOC_PDR, _BV(PC16_NWAIT_B) | _BV(PC21_NWR0_B) | _BV(PC22_NRD_B));
01030 
01031     outr(SMC_CSR(2)
01032         , (1 << SMC_NWS_LSB)
01033         | SMC_WSEN
01034         | (2 << SMC_TDF_LSB)
01035         | SMC_BAT
01036         | SMC_DBW_16
01037         | (1 << SMC_RWSETUP_LSB)
01038         | (1 << SMC_RWHOLD_LSB)
01039         );
01040 #endif
01041 
01042     /* Probe chip by verifying the identifier registers. */
01043     id = (uint32_t) nic_inb(NIC_VID);
01044     id |= (uint32_t) nic_inb(NIC_VID + 1) << 8;
01045     id |= (uint32_t) nic_inb(NIC_PID) << 16;
01046     id |= (uint32_t) nic_inb(NIC_PID + 1) << 24;
01047     if (id != 0x90000A46) {
01048         return -1;
01049     }
01050 
01051     /* Reset chip. */
01052     if (NicReset()) {
01053         return -1;
01054     }
01055 
01056     /* Clear NICINFO structure. */
01057     memset(ni, 0, sizeof(NICINFO));
01058 
01059     /* Determine bus mode. We do not support 32 bit access. */
01060     ni->ni_iomode = nic_inb(NIC_ISR) & NIC_ISR_IOM;
01061     if (ni->ni_iomode == NIC_ISR_M32) {
01062         return -1;
01063     }
01064 
01065     /* Register interrupt handler. */
01066     if (NutRegisterIrqHandler(&NIC_SIGNAL, NicInterrupt, dev)) {
01067         return -1;
01068     }
01069 
01070     /* Start the receiver thread. */
01071     if (NutThreadCreate("rxi1", NicRxLanc, dev, 
01072         (NUT_THREAD_NICRXSTACK * NUT_THREAD_STACK_MULT) + NUT_THREAD_STACK_ADD) == NULL) {
01073         return -1;
01074     }
01075     return 0;
01076 }
01077 
01078 static NICINFO dcb_eth0;
01079 
01085 static IFNET ifn_eth0 = {
01086     IFT_ETHER,                  
01087     0,                          
01088     {0, 0, 0, 0, 0, 0},         
01089     0,                          
01090     0,                          
01091     0,                          
01092     ETHERMTU,                   
01093     0,                          
01094     0,                          
01095     0,                          
01096     NutEtherInput,              
01097     DmOutput,                   
01098     NutEtherOutput              
01099 };
01100 
01110 NUTDEVICE devDM9000E = {
01111     0,                          
01112     {'e', 't', 'h', '0', 0, 0, 0, 0, 0},        
01113     IFTYP_NET,                  
01114     0,                          
01115     0,                          
01116     &ifn_eth0,                  
01117     &dcb_eth0,                  
01118     DmInit,                     
01119     0,                          
01120     0,                          
01121     0,                          
01122 #ifdef __HARVARD_ARCH__
01123     0,                          
01124 #endif
01125     0,                          
01126     0,                          
01127     0                           
01128 };
01129 
01130 #endif /* NIC_BASE_ADDR */
01131 

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