Two Wire Interface
[AT91 Support]

Two wire interface registers. More...

Collaboration diagram for Two Wire Interface:

TWI Control Register



#define TWI_CR_OFF   0x00000000
 Control register offset.
#define TWI_CR   (TWI_BASE + TWI_CR_OFF)
 Control register address.
#define TWI_START   0x00000001
 Send start condition.
#define TWI_STOP   0x00000002
 Send stop condition.
#define TWI_MSEN   0x00000004
 Enable master mode.
#define TWI_MSDIS   0x00000008
 Disable master mode.
#define TWI_SVEN   0x00000010
 Enable slave mode.
#define TWI_SVDIS   0x00000020
 Disable slave mode.
#define TWI_SWRST   0x00000080
 Software reset.

TWI Master Mode Register



#define TWI_MMR_OFF   0x00000004
 Master mode register offset.
#define TWI_MMR   (TWI_BASE + TWI_MMR_OFF)
 Master mode register address.
#define TWI_IADRSZ   0x00000300
 Internal device address size mask.
#define TWI_IADRSZ_NONE   0x00000000
 No internal device address.
#define TWI_IADRSZ_1BYTE   0x00000100
 One byte internal device address.
#define TWI_IADRSZ_2BYTE   0x00000200
 Two byte internal device address.
#define TWI_IADRSZ_3BYTE   0x00000300
 Three byte internal device address.
#define TWI_MREAD   0x00001000
 Master read direction.
#define TWI_DADR   0x007F0000
 Device address mask.
#define TWI_DADR_LSB   16
 Device address LSB.

TWI Slave Mode Register



#define TWI_SMR_OFF   0x00000008
 Slave mode register offset.
#define TWI_SMR   (TWI_BASE + TWI_SMR_OFF)
 Slave mode register address.
#define TWI_SADR   0x007F0000
 Slave address mask.
#define TWI_SADR_LSB   16
 Slave address LSB.

TWI Internal Address Register



#define TWI_IADRR_OFF   0x0000000C
 Internal address register offset.
#define TWI_IADRR   (TWI_BASE + TWI_IADRR_OFF)
 Internal address register address.
#define TWI_IADR   0x00FFFFFF
 Internal address mask.
#define TWI_IADR_LSB   0
 Internal address LSB.

TWI Clock Waveform Generator Register



#define TWI_CWGR_OFF   0x00000010
 Clock waveform generator register offset.
#define TWI_CWGR   (TWI_BASE + TWI_CWGR_OFF)
 Clock waveform generator register address.
#define TWI_CLDIV   0x000000FF
 Clock low divider mask.
#define TWI_CLDIV_LSB   0
 Clock low divider LSB.
#define TWI_CHDIV   0x0000FF00
 Clock high divider mask.
#define TWI_CHDIV_LSB   8
 Clock high divider LSB.
#define TWI_CKDIV   0x00070000
 Clock divider mask.
#define TWI_CKDIV_LSB   16
 Clock divider LSB.

TWI Status and Interrupt Registers



#define TWI_SR_OFF   0x00000020
 Status register offset.
#define TWI_SR   (TWI_BASE + TWI_SR_OFF)
 Status register address.
#define TWI_IER_OFF   0x00000024
 Interrupt enable register offset.
#define TWI_IER   (TWI_BASE + TWI_IER_OFF)
 Interrupt enable register address.
#define TWI_IDR_OFF   0x00000028
 Interrupt disable register offset.
#define TWI_IDR   (TWI_BASE + TWI_IDR_OFF)
 Interrupt disable register address.
#define TWI_IMR_OFF   0x0000002C
 Interrupt mask register offset.
#define TWI_IMR   (TWI_BASE + TWI_IMR_OFF)
 Interrupt mask register address.
#define TWI_TXCOMP   0x00000001
 Transmission completed.
#define TWI_RXRDY   0x00000002
 Receive holding register ready.
#define TWI_TXRDY   0x00000004
 Transmit holding register ready.
#define TWI_SVREAD   0x00000008
 Slave read.
#define TWI_SVACC   0x00000010
 Slave access.
#define TWI_GACC   0x00000020
 General call access.
#define TWI_OVRE   0x00000040
 Overrun error.
#define TWI_NACK   0x00000100
 Not acknowledged.
#define TWI_ARBLST   0x00000200
 Arbitration lost.
#define TWI_SCLWS   0x00000400
 Clock wait state.
#define TWI_EOSACC   0x00000800
 End of slave access.

TWI Receive Holding Register



#define TWI_RHR_OFF   0x00000030
 Receive holding register offset.
#define TWI_RHR   (TWI_BASE + TWI_RHR_OFF)
 Receive holding register address.

TWI Transmit Holding Register



#define TWI_THR_OFF   0x00000034
 Transmit holding register offset.
#define TWI_THR   (TWI_BASE + TWI_THR_OFF)
 Transmit holding register address.

Detailed Description

Two wire interface registers.


Define Documentation

#define TWI_CR_OFF   0x00000000

Control register offset.

Definition at line 60 of file at91_twi.h.

#define TWI_CR   (TWI_BASE + TWI_CR_OFF)

Control register address.

Definition at line 61 of file at91_twi.h.

Referenced by TwInit(), TwMasterRegRead(), and TwMasterTransact().

#define TWI_START   0x00000001

Send start condition.

Definition at line 62 of file at91_twi.h.

Referenced by TwMasterRegRead(), and TwMasterTransact().

#define TWI_STOP   0x00000002

Send stop condition.

Definition at line 63 of file at91_twi.h.

Referenced by TwMasterRegRead(), and TwMasterTransact().

#define TWI_MSEN   0x00000004

Enable master mode.

Definition at line 64 of file at91_twi.h.

Referenced by TwInit().

#define TWI_MSDIS   0x00000008

Disable master mode.

Definition at line 65 of file at91_twi.h.

#define TWI_SVEN   0x00000010

Enable slave mode.

Definition at line 66 of file at91_twi.h.

#define TWI_SVDIS   0x00000020

Disable slave mode.

Definition at line 67 of file at91_twi.h.

Referenced by TwInit().

#define TWI_SWRST   0x00000080

Software reset.

Definition at line 68 of file at91_twi.h.

Referenced by TwInit().

#define TWI_MMR_OFF   0x00000004

Master mode register offset.

Definition at line 73 of file at91_twi.h.

#define TWI_MMR   (TWI_BASE + TWI_MMR_OFF)

Master mode register address.

Definition at line 74 of file at91_twi.h.

Referenced by TwMasterRegRead(), TwMasterRegWrite(), and TwMasterTransact().

#define TWI_IADRSZ   0x00000300

Internal device address size mask.

Definition at line 75 of file at91_twi.h.

#define TWI_IADRSZ_NONE   0x00000000

No internal device address.

Definition at line 76 of file at91_twi.h.

#define TWI_IADRSZ_1BYTE   0x00000100

One byte internal device address.

Definition at line 77 of file at91_twi.h.

#define TWI_IADRSZ_2BYTE   0x00000200

Two byte internal device address.

Definition at line 78 of file at91_twi.h.

#define TWI_IADRSZ_3BYTE   0x00000300

Three byte internal device address.

Definition at line 79 of file at91_twi.h.

#define TWI_MREAD   0x00001000

Master read direction.

Definition at line 80 of file at91_twi.h.

Referenced by TwMasterRegRead(), and TwMasterTransact().

#define TWI_DADR   0x007F0000

Device address mask.

Definition at line 81 of file at91_twi.h.

#define TWI_DADR_LSB   16

Device address LSB.

Definition at line 82 of file at91_twi.h.

Referenced by TwMasterRegRead(), TwMasterRegWrite(), and TwMasterTransact().

#define TWI_SMR_OFF   0x00000008

Slave mode register offset.

Definition at line 87 of file at91_twi.h.

#define TWI_SMR   (TWI_BASE + TWI_SMR_OFF)

Slave mode register address.

Definition at line 88 of file at91_twi.h.

#define TWI_SADR   0x007F0000

Slave address mask.

Definition at line 89 of file at91_twi.h.

#define TWI_SADR_LSB   16

Slave address LSB.

Definition at line 90 of file at91_twi.h.

#define TWI_IADRR_OFF   0x0000000C

Internal address register offset.

Definition at line 95 of file at91_twi.h.

#define TWI_IADRR   (TWI_BASE + TWI_IADRR_OFF)

Internal address register address.

Definition at line 96 of file at91_twi.h.

Referenced by TwMasterRegRead(), and TwMasterRegWrite().

#define TWI_IADR   0x00FFFFFF

Internal address mask.

Definition at line 97 of file at91_twi.h.

#define TWI_IADR_LSB   0

Internal address LSB.

Definition at line 98 of file at91_twi.h.

#define TWI_CWGR_OFF   0x00000010

Clock waveform generator register offset.

Definition at line 103 of file at91_twi.h.

#define TWI_CWGR   (TWI_BASE + TWI_CWGR_OFF)

Clock waveform generator register address.

Definition at line 104 of file at91_twi.h.

Referenced by TwIOCtl().

#define TWI_CLDIV   0x000000FF

Clock low divider mask.

Definition at line 105 of file at91_twi.h.

#define TWI_CLDIV_LSB   0

Clock low divider LSB.

Definition at line 106 of file at91_twi.h.

#define TWI_CHDIV   0x0000FF00

Clock high divider mask.

Definition at line 107 of file at91_twi.h.

#define TWI_CHDIV_LSB   8

Clock high divider LSB.

Definition at line 108 of file at91_twi.h.

#define TWI_CKDIV   0x00070000

Clock divider mask.

Definition at line 109 of file at91_twi.h.

#define TWI_CKDIV_LSB   16

Clock divider LSB.

Definition at line 110 of file at91_twi.h.

#define TWI_SR_OFF   0x00000020

Status register offset.

Definition at line 115 of file at91_twi.h.

#define TWI_SR   (TWI_BASE + TWI_SR_OFF)

Status register address.

Definition at line 116 of file at91_twi.h.

#define TWI_IER_OFF   0x00000024

Interrupt enable register offset.

Definition at line 118 of file at91_twi.h.

#define TWI_IER   (TWI_BASE + TWI_IER_OFF)

Interrupt enable register address.

Definition at line 119 of file at91_twi.h.

Referenced by TwMasterRegRead(), TwMasterRegWrite(), and TwMasterTransact().

#define TWI_IDR_OFF   0x00000028

Interrupt disable register offset.

Definition at line 121 of file at91_twi.h.

#define TWI_IDR   (TWI_BASE + TWI_IDR_OFF)

Interrupt disable register address.

Definition at line 122 of file at91_twi.h.

Referenced by TwInit(), TwMasterRegRead(), TwMasterRegWrite(), and TwMasterTransact().

#define TWI_IMR_OFF   0x0000002C

Interrupt mask register offset.

Definition at line 124 of file at91_twi.h.

#define TWI_IMR   (TWI_BASE + TWI_IMR_OFF)

Interrupt mask register address.

Definition at line 125 of file at91_twi.h.

#define TWI_TXCOMP   0x00000001

Transmission completed.

Definition at line 127 of file at91_twi.h.

#define TWI_RXRDY   0x00000002

Receive holding register ready.

Definition at line 128 of file at91_twi.h.

Referenced by TwMasterRegRead(), and TwMasterTransact().

#define TWI_TXRDY   0x00000004

Transmit holding register ready.

Definition at line 129 of file at91_twi.h.

Referenced by TwMasterRegWrite(), and TwMasterTransact().

#define TWI_SVREAD   0x00000008

Slave read.

Definition at line 130 of file at91_twi.h.

#define TWI_SVACC   0x00000010

Slave access.

Definition at line 131 of file at91_twi.h.

#define TWI_GACC   0x00000020

General call access.

Definition at line 132 of file at91_twi.h.

#define TWI_OVRE   0x00000040

Overrun error.

Definition at line 133 of file at91_twi.h.

#define TWI_NACK   0x00000100

Not acknowledged.

Definition at line 134 of file at91_twi.h.

#define TWI_ARBLST   0x00000200

Arbitration lost.

Definition at line 135 of file at91_twi.h.

#define TWI_SCLWS   0x00000400

Clock wait state.

Definition at line 136 of file at91_twi.h.

#define TWI_EOSACC   0x00000800

End of slave access.

Definition at line 137 of file at91_twi.h.

#define TWI_RHR_OFF   0x00000030

Receive holding register offset.

Definition at line 142 of file at91_twi.h.

#define TWI_RHR   (TWI_BASE + TWI_RHR_OFF)

Receive holding register address.

Definition at line 143 of file at91_twi.h.

#define TWI_THR_OFF   0x00000034

Transmit holding register offset.

Definition at line 148 of file at91_twi.h.

#define TWI_THR   (TWI_BASE + TWI_THR_OFF)

Transmit holding register address.

Definition at line 149 of file at91_twi.h.

Referenced by TwMasterRegWrite(), and TwMasterTransact().


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