Go to the source code of this file.
Defines | |
#define | EMAC_RX_BUFFERS 32 |
#define | EMAC_RX_BUFSIZ 128 |
#define | EMAC_TX_BUFFERS 2 |
#define | EMAC_TX_BUFSIZ 1536 |
#define | EMAC_LINK_LOOPS 1000000 |
#define | NIC_PHY_BMCR 0x00 |
Basic mode control register. | |
#define | NIC_PHY_BMCR_COLTEST 0x0080 |
Collision test. | |
#define | NIC_PHY_BMCR_FDUPLEX 0x0100 |
Full duplex mode. | |
#define | NIC_PHY_BMCR_ANEGSTART 0x0200 |
Restart auto negotiation. | |
#define | NIC_PHY_BMCR_ISOLATE 0x0400 |
Isolate from MII. | |
#define | NIC_PHY_BMCR_PWRDN 0x0800 |
Power-down. | |
#define | NIC_PHY_BMCR_ANEGENA 0x1000 |
Enable auto negotiation. | |
#define | NIC_PHY_BMCR_100MBPS 0x2000 |
Select 100 Mbps. | |
#define | NIC_PHY_BMCR_LOOPBACK 0x4000 |
Enable loopback mode. | |
#define | NIC_PHY_BMCR_RESET 0x8000 |
Software reset. | |
#define | NIC_PHY_BMSR 0x01 |
Basic mode status register. | |
#define | NIC_PHY_BMSR_ANCOMPL 0x0020 |
Auto negotiation complete. | |
#define | NIC_PHY_BMSR_LINKSTAT 0x0004 |
Link status. | |
#define | NIC_PHY_ID1 0x02 |
PHY identifier register 1. | |
#define | NIC_PHY_ID2 0x03 |
PHY identifier register 2. | |
#define | NIC_PHY_ANAR 0x04 |
Auto negotiation advertisement register. | |
#define | NIC_PHY_ANLPAR 0x05 |
Auto negotiation link partner availability register. | |
#define | NIC_PHY_ANEG_NP 0x8000 |
Next page available. | |
#define | NIC_PHY_ANEG_ACK 0x4000 |
Ability data reception acknowledged. | |
#define | NIC_PHY_ANEG_RF 0x2000 |
Remote fault. | |
#define | NIC_PHY_ANEG_FCS 0x0400 |
Flow control supported. | |
#define | NIC_PHY_ANEG_T4 0x0200 |
100BASE-T4 supported. | |
#define | NIC_PHY_ANEG_TX_FDX 0x0100 |
100BASE-T full duplex supported. | |
#define | NIC_PHY_ANEG_TX_HDX 0x0080 |
100BASE-T half duplex supported. | |
#define | NIC_PHY_ANEG_10_FDX 0x0040 |
10BASE-T full duplex supported. | |
#define | NIC_PHY_ANEG_10_HDX 0x0020 |
10BASE-T half duplex supported. | |
#define | NIC_PHY_ANEG_BINSEL 0x001F |
Binary encoded protocol selector. | |
#define | NIC_PHY_ANER 0x06 |
Auto negotiation expansion register. | |
#define | NIC_PHY_ADDR 0 |
PHY address. | |
#define | PHY_ADDR_STRAP_PINS |
#define | PHY_STRAP_PINS (PHY_ADDR_STRAP_PINS | _BV(PHY_COL_RMII_BIT)) |
#define | RXBUF_OWNERSHIP 0x00000001 |
#define | RXBUF_WRAP 0x00000002 |
#define | RXBUF_ADDRMASK 0xFFFFFFFC |
#define | RXS_BROADCAST_ADDR 0x80000000 |
Broadcast address detected. | |
#define | RXS_MULTICAST_HASH 0x40000000 |
Multicast hash match. | |
#define | RXS_UNICAST_HASH 0x20000000 |
Unicast hash match. | |
#define | RXS_EXTERNAL_ADDR 0x10000000 |
External address match. | |
#define | RXS_SA1_ADDR 0x04000000 |
Specific address register 1 match. | |
#define | RXS_SA2_ADDR 0x02000000 |
Specific address register 2 match. | |
#define | RXS_SA3_ADDR 0x01000000 |
Specific address register 3 match. | |
#define | RXS_SA4_ADDR 0x00800000 |
Specific address register 4 match. | |
#define | RXS_TYPE_ID 0x00400000 |
Type ID match. | |
#define | RXS_VLAN_TAG 0x00200000 |
VLAN tag detected. | |
#define | RXS_PRIORITY_TAG 0x00100000 |
Priority tag detected. | |
#define | RXS_VLAN_PRIORITY 0x000E0000 |
VLAN priority. | |
#define | RXS_CFI_IND 0x00010000 |
Concatenation format indicator. | |
#define | RXS_EOF 0x00008000 |
End of frame. | |
#define | RXS_SOF 0x00004000 |
Start of frame. | |
#define | RXS_RBF_OFFSET 0x00003000 |
Receive buffer offset mask. | |
#define | RXS_LENGTH_FRAME 0x000007FF |
Length of frame including FCS. | |
#define | TXS_USED 0x80000000 |
Used buffer. | |
#define | TXS_WRAP 0x40000000 |
Last descriptor. | |
#define | TXS_ERROR 0x20000000 |
Retry limit exceeded. | |
#define | TXS_UNDERRUN 0x10000000 |
Transmit underrun. | |
#define | TXS_NO_BUFFER 0x08000000 |
Buffer exhausted. | |
#define | TXS_NO_CRC 0x00010000 |
CRC not appended. | |
#define | TXS_LAST_BUFF 0x00008000 |
Last buffer of frame. | |
#define | MII_DM9161_ID_H 0x0181 |
#define | MII_DM9161_ID_L 0xb8a0 |
#define | MII_AM79C875_ID_H 0x0022 |
#define | MII_AM79C875_ID_L 0x5540 |
#define | MII_MICREL_ID_H 0x0022 |
#define | MII_MICREL_ID_L 0x1610 |
#define | MII_LAN8700_ID_H 0x0007 |
#define | MII_LAN8700_ID_L 0xc0c0 |
Functions | |
void | EmacRxThread (void *arg) |
NIC receiver thread. | |
int | EmacOutput (NUTDEVICE *dev, NETBUF *nb) |
Send Ethernet packet. | |
int | EmacInit (NUTDEVICE *dev) |
Initialize Ethernet hardware. | |
Variables | |
NUTDEVICE | devAt91Emac |
Device information structure. |
#define EMAC_RX_BUFFERS 32 |
Definition at line 131 of file at91_emac.c.
#define EMAC_RX_BUFSIZ 128 |
Definition at line 133 of file at91_emac.c.
#define EMAC_TX_BUFFERS 2 |
Definition at line 135 of file at91_emac.c.
#define EMAC_TX_BUFSIZ 1536 |
Definition at line 137 of file at91_emac.c.
#define EMAC_LINK_LOOPS 1000000 |
Definition at line 141 of file at91_emac.c.
Referenced by EmacInit(), and EmacRxThread().
#define NIC_PHY_ADDR 0 |
PHY address.
Any other than 0 seems to create problems with Atmel's evaluation kits.
Definition at line 221 of file at91_emac.c.
#define PHY_ADDR_STRAP_PINS |
#define PHY_STRAP_PINS (PHY_ADDR_STRAP_PINS | _BV(PHY_COL_RMII_BIT)) |
Definition at line 361 of file at91_emac.c.
#define RXBUF_OWNERSHIP 0x00000001 |
Definition at line 409 of file at91_emac.c.
#define RXBUF_WRAP 0x00000002 |
Definition at line 410 of file at91_emac.c.
#define RXBUF_ADDRMASK 0xFFFFFFFC |
Definition at line 411 of file at91_emac.c.
#define RXS_BROADCAST_ADDR 0x80000000 |
Broadcast address detected.
Definition at line 413 of file at91_emac.c.
#define RXS_MULTICAST_HASH 0x40000000 |
Multicast hash match.
Definition at line 414 of file at91_emac.c.
#define RXS_UNICAST_HASH 0x20000000 |
Unicast hash match.
Definition at line 415 of file at91_emac.c.
#define RXS_EXTERNAL_ADDR 0x10000000 |
External address match.
Definition at line 416 of file at91_emac.c.
#define RXS_SA1_ADDR 0x04000000 |
Specific address register 1 match.
Definition at line 417 of file at91_emac.c.
#define RXS_SA2_ADDR 0x02000000 |
Specific address register 2 match.
Definition at line 418 of file at91_emac.c.
#define RXS_SA3_ADDR 0x01000000 |
Specific address register 3 match.
Definition at line 419 of file at91_emac.c.
#define RXS_SA4_ADDR 0x00800000 |
Specific address register 4 match.
Definition at line 420 of file at91_emac.c.
#define RXS_TYPE_ID 0x00400000 |
Type ID match.
Definition at line 421 of file at91_emac.c.
#define RXS_VLAN_TAG 0x00200000 |
VLAN tag detected.
Definition at line 422 of file at91_emac.c.
#define RXS_PRIORITY_TAG 0x00100000 |
Priority tag detected.
Definition at line 423 of file at91_emac.c.
#define RXS_VLAN_PRIORITY 0x000E0000 |
VLAN priority.
Definition at line 424 of file at91_emac.c.
#define RXS_CFI_IND 0x00010000 |
Concatenation format indicator.
Definition at line 425 of file at91_emac.c.
#define RXS_EOF 0x00008000 |
End of frame.
Definition at line 426 of file at91_emac.c.
#define RXS_SOF 0x00004000 |
Start of frame.
Definition at line 427 of file at91_emac.c.
#define RXS_RBF_OFFSET 0x00003000 |
Receive buffer offset mask.
Definition at line 428 of file at91_emac.c.
#define RXS_LENGTH_FRAME 0x000007FF |
Length of frame including FCS.
Definition at line 429 of file at91_emac.c.
#define TXS_USED 0x80000000 |
#define TXS_WRAP 0x40000000 |
Last descriptor.
Definition at line 432 of file at91_emac.c.
#define TXS_ERROR 0x20000000 |
Retry limit exceeded.
Definition at line 433 of file at91_emac.c.
#define TXS_UNDERRUN 0x10000000 |
Transmit underrun.
Definition at line 434 of file at91_emac.c.
#define TXS_NO_BUFFER 0x08000000 |
Buffer exhausted.
Definition at line 435 of file at91_emac.c.
#define TXS_NO_CRC 0x00010000 |
CRC not appended.
Definition at line 436 of file at91_emac.c.
#define TXS_LAST_BUFF 0x00008000 |
Last buffer of frame.
Definition at line 437 of file at91_emac.c.
#define MII_DM9161_ID_H 0x0181 |
#define MII_DM9161_ID_L 0xb8a0 |
#define MII_AM79C875_ID_H 0x0022 |
#define MII_AM79C875_ID_L 0x5540 |
#define MII_MICREL_ID_H 0x0022 |
#define MII_MICREL_ID_L 0x1610 |
#define MII_LAN8700_ID_H 0x0007 |
#define MII_LAN8700_ID_L 0xc0c0 |