vs10xx.c

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00001 /*
00002  * Copyright (C) 2001-2007 by egnite Software GmbH. All rights reserved.
00003  *
00004  * Redistribution and use in source and binary forms, with or without
00005  * modification, are permitted provided that the following conditions
00006  * are met:
00007  *
00008  * 1. Redistributions of source code must retain the above copyright
00009  *    notice, this list of conditions and the following disclaimer.
00010  * 2. Redistributions in binary form must reproduce the above copyright
00011  *    notice, this list of conditions and the following disclaimer in the
00012  *    documentation and/or other materials provided with the distribution.
00013  * 3. Neither the name of the copyright holders nor the names of
00014  *    contributors may be used to endorse or promote products derived
00015  *    from this software without specific prior written permission.
00016  *
00017  * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
00018  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00019  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00020  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
00021  * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
00022  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
00023  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
00024  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
00025  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00026  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
00027  * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
00028  * SUCH DAMAGE.
00029  *
00030  * For additional information see http://www.ethernut.de/
00031  * -
00032  *
00033  * This software has been inspired by all the valuable work done by
00034  * Jesper Hansen and Pavel Chromy. Many thanks for all their help.
00035  */
00036 
00037 /*
00038  * $Log$
00039  * Revision 1.6  2009/01/17 11:26:46  haraldkipp
00040  * Getting rid of two remaining BSD types in favor of stdint.
00041  * Replaced 'u_int' by 'unsinged int' and 'uptr_t' by 'uintptr_t'.
00042  *
00043  * Revision 1.5  2008/10/23 08:54:07  haraldkipp
00044  * Include the correct header file.
00045  *
00046  * Revision 1.4  2008/09/18 09:51:58  haraldkipp
00047  * Use the correct PORT macros.
00048  *
00049  * Revision 1.3  2008/09/02 14:30:28  haraldkipp
00050  * Make it compile for targets without specific configuration.
00051  *
00052  * Revision 1.2  2008/08/11 06:59:42  haraldkipp
00053  * BSD types replaced by stdint types (feature request #1282721).
00054  *
00055  * Revision 1.1  2007/04/12 08:59:55  haraldkipp
00056  * VS10XX decoder support added.
00057  *
00058  */
00059 
00060 #include <sys/atom.h>
00061 #include <sys/event.h>
00062 #include <sys/timer.h>
00063 #include <sys/heap.h>
00064 
00065 #include <cfg/arch/gpio.h>
00066 #include <cfg/audio.h>
00067 #include <dev/irqreg.h>
00068 #include <dev/vs10xx.h>
00069 
00070 #include <sys/bankmem.h>
00071 
00072 #include <stddef.h>
00073 
00078 
00079 #if !defined(AUDIO_VS1001K) && !defined(AUDIO_VS1011E) && !defined(AUDIO_VS1002D) && !defined(AUDIO_VS1003B) && !defined(AUDIO_VS1033C)
00080 #define AUDIO_VS1001K
00081 #endif
00082 
00083 #ifndef VS10XX_FREQ
00084 
00085 #define VS10XX_FREQ             12288000UL
00086 #endif
00087 
00088 #ifndef VS10XX_HWRST_DURATION
00089 
00090 #define VS10XX_HWRST_DURATION   1
00091 #endif
00092 
00093 #ifndef VS10XX_HWRST_RECOVER
00094 
00095 #define VS10XX_HWRST_RECOVER    4
00096 #endif
00097 
00098 #ifndef VS10XX_SWRST_RECOVER
00099 
00100 #define VS10XX_SWRST_RECOVER    2
00101 #endif
00102 
00103 #ifndef VS10XX_SCI_MODE
00104 #define VS10XX_SCI_MODE         0
00105 #endif
00106 
00107 #ifndef VS10XX_SCI_RATE
00108 #define VS10XX_SCI_RATE         (VS10XX_FREQ / 4)
00109 #endif
00110 
00111 #ifndef VS10XX_SDI_MODE
00112 #define VS10XX_SDI_MODE         0
00113 #endif
00114 
00115 #ifndef VS10XX_SDI_RATE
00116 #define VS10XX_SDI_RATE         (VS10XX_FREQ / 4)
00117 #endif
00118 
00119 #if defined(VS10XX_SCI_SPI0_DEVICE) /* Command SPI device. */
00120 
00121 #include <dev/sppif0.h>
00122 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00123 #define SciReset(act)       Sppi0ChipReset(VS10XX_SCI_SPI0_DEVICE, act)
00124 #else
00125 #define SciReset(act)       Sppi0ChipReset(VS10XX_SCI_SPI0_DEVICE, !act)
00126 #endif
00127 #define SciSetMode()        Sppi0SetMode(VS10XX_SCI_SPI0_DEVICE, VS10XX_SCI_MODE)
00128 #define SciSetSpeed()       Sppi0SetSpeed(VS10XX_SCI_SPI0_DEVICE, VS10XX_SCI_RATE)
00129 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00130 #define SciSelect()         Sppi0SelectDevice(VS10XX_SCI_SPI0_DEVICE)
00131 #define SciDeselect()       Sppi0DeselectDevice(VS10XX_SCI_SPI0_DEVICE)
00132 #else
00133 #define SciSelect()         Sppi0NegSelectDevice(VS10XX_SCI_SPI0_DEVICE)
00134 #define SciDeselect()       Sppi0NegDeselectDevice(VS10XX_SCI_SPI0_DEVICE)
00135 #endif
00136 #define SciByte(b)          Sppi0Byte(b)
00137 
00138 #elif defined(VS10XX_SCI_SBBI0_DEVICE) /* Command SPI device. */
00139 
00140 #include <dev/sbbif0.h>
00141 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00142 #define SciReset(act)       Sbbi0ChipReset(VS10XX_SCI_SBBI0_DEVICE, act)
00143 #else
00144 #define SciReset(act)       Sbbi0ChipReset(VS10XX_SCI_SBBI0_DEVICE, !act)
00145 #endif
00146 #define SciSetMode()        Sbbi0SetMode(VS10XX_SCI_SBBI0_DEVICE, VS10XX_SCI_MODE)
00147 #define SciSetSpeed()       Sbbi0SetSpeed(VS10XX_SCI_SBBI0_DEVICE, VS10XX_SCI_RATE)
00148 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00149 #define SciSelect()         Sbbi0SelectDevice(VS10XX_SCI_SBBI0_DEVICE)
00150 #define SciDeselect()       Sbbi0DeselectDevice(VS10XX_SCI_SBBI0_DEVICE)
00151 #else
00152 #define SciSelect()         Sbbi0NegSelectDevice(VS10XX_SCI_SBBI0_DEVICE)
00153 #define SciDeselect()       Sbbi0NegDeselectDevice(VS10XX_SCI_SBBI0_DEVICE)
00154 #endif
00155 #define SciByte(b)          Sbbi0Byte(b)
00156 
00157 #elif defined(VS10XX_SCI_SBBI1_DEVICE) /* Command SPI device. */
00158 
00159 #include <dev/sbbif1.h>
00160 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00161 #define SciReset(act)       Sbbi1ChipReset(VS10XX_SCI_SBBI1_DEVICE, act)
00162 #else
00163 #define SciReset(act)       Sbbi1ChipReset(VS10XX_SCI_SBBI1_DEVICE, !act)
00164 #endif
00165 #define SciSetMode()        Sbbi1SetMode(VS10XX_SCI_SBBI1_DEVICE, VS10XX_SCI_MODE)
00166 #define SciSetSpeed()       Sbbi1SetSpeed(VS10XX_SCI_SBBI1_DEVICE, VS10XX_SCI_RATE)
00167 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00168 #define SciSelect()         Sbbi1SelectDevice(VS10XX_SCI_SBBI1_DEVICE)
00169 #define SciDeselect()       Sbbi1DeselectDevice(VS10XX_SCI_SBBI1_DEVICE)
00170 #else
00171 #define SciSelect()         Sbbi1NegSelectDevice(VS10XX_SCI_SBBI1_DEVICE)
00172 #define SciDeselect()       Sbbi1NegDeselectDevice(VS10XX_SCI_SBBI1_DEVICE)
00173 #endif
00174 #define SciByte(b)          Sbbi1Byte(b)
00175 
00176 #elif defined(VS10XX_SCI_SBBI2_DEVICE) /* Command SPI device. */
00177 
00178 #include <dev/sbbif2.h>
00179 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00180 #define SciReset(act)       Sbbi2ChipReset(VS10XX_SCI_SBBI2_DEVICE, act)
00181 #else
00182 #define SciReset(act)       Sbbi2ChipReset(VS10XX_SCI_SBBI2_DEVICE, !act)
00183 #endif
00184 #define SciSetMode()        Sbbi2SetMode(VS10XX_SCI_SBBI2_DEVICE, VS10XX_SCI_MODE)
00185 #define SciSetSpeed()       Sbbi2SetSpeed(VS10XX_SCI_SBBI2_DEVICE, VS10XX_SCI_RATE)
00186 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00187 #define SciSelect()         Sbbi2SelectDevice(VS10XX_SCI_SBBI2_DEVICE)
00188 #define SciDeselect()       Sbbi2DeselectDevice(VS10XX_SCI_SBBI2_DEVICE)
00189 #else
00190 #define SciSelect()         Sbbi2NegSelectDevice(VS10XX_SCI_SBBI2_DEVICE)
00191 #define SciDeselect()       Sbbi2NegDeselectDevice(VS10XX_SCI_SBBI2_DEVICE)
00192 #endif
00193 #define SciByte(b)          Sbbi2Byte(b)
00194 
00195 #elif defined(VS10XX_SCI_SBBI3_DEVICE) /* Command SPI device. */
00196 
00197 #include <dev/sbbif3.h>
00198 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00199 #define SciReset(act)       Sbbi3ChipReset(VS10XX_SCI_SBBI3_DEVICE, act)
00200 #else
00201 #define SciReset(act)       Sbbi3ChipReset(VS10XX_SCI_SBBI3_DEVICE, !act)
00202 #endif
00203 #define SciSetMode()        Sbbi3SetMode(VS10XX_SCI_SBBI3_DEVICE, VS10XX_SCI_MODE)
00204 #define SciSetSpeed()       Sbbi3SetSpeed(VS10XX_SCI_SBBI3_DEVICE, VS10XX_SCI_RATE)
00205 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00206 #define SciSelect()         Sbbi3SelectDevice(VS10XX_SCI_SBBI3_DEVICE)
00207 #define SciDeselect()       Sbbi3DeselectDevice(VS10XX_SCI_SBBI3_DEVICE)
00208 #else
00209 #define SciSelect()         Sbbi3NegSelectDevice(VS10XX_SCI_SBBI3_DEVICE)
00210 #define SciDeselect()       Sbbi3NegDeselectDevice(VS10XX_SCI_SBBI3_DEVICE)
00211 #endif
00212 #define SciByte(b)          Sbbi3Byte(b)
00213 
00214 #else /* Command SPI device. */
00215 
00216 #define SciReset(act)
00217 #define SciSetMode()        (-1)
00218 #define SciSetSpeed()
00219 #define SciSelect()
00220 #define SciDeselect()
00221 #define SciByte(b)          0
00222 
00223 #endif /* Command SPI device. */
00224 
00225 
00226 #if defined(VS10XX_SDI_SPI0_DEVICE) /* Data SPI device. */
00227 
00228 #include <dev/sppif0.h>
00229 #define SdiSetMode()        Sppi0SetMode(VS10XX_SDI_SPI0_DEVICE, VS10XX_SDI_MODE)
00230 #define SdiSetSpeed()       Sppi0SetSpeed(VS10XX_SDI_SPI0_DEVICE, VS10XX_SDI_RATE)
00231 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00232 #define SdiSelect()         Sppi0SelectDevice(VS10XX_SDI_SPI0_DEVICE)
00233 #define SdiDeselect()       Sppi0DeselectDevice(VS10XX_SDI_SPI0_DEVICE)
00234 #else
00235 #define SdiSelect()         Sppi0NegSelectDevice(VS10XX_SDI_SPI0_DEVICE)
00236 #define SdiDeselect()       Sppi0NegDeselectDevice(VS10XX_SDI_SPI0_DEVICE)
00237 #endif
00238 #define SdiByte(b)          Sppi0Byte(b)
00239 
00240 #elif defined(VS10XX_SDI_SBBI0_DEVICE) /* Data SPI device. */
00241 
00242 #include <dev/sbbif0.h>
00243 #define SdiSetMode()        Sbbi0SetMode(VS10XX_SDI_SBBI0_DEVICE, VS10XX_SDI_MODE)
00244 #define SdiSetSpeed()       Sbbi0SetSpeed(VS10XX_SDI_SBBI0_DEVICE, VS10XX_SDI_RATE)
00245 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00246 #define SdiSelect()         Sbbi0SelectDevice(VS10XX_SDI_SBBI0_DEVICE)
00247 #define SdiDeselect()       Sbbi0DeselectDevice(VS10XX_SDI_SBBI0_DEVICE)
00248 #else
00249 #define SdiSelect()         Sbbi0NegSelectDevice(VS10XX_SDI_SBBI0_DEVICE)
00250 #define SdiDeselect()       Sbbi0NegDeselectDevice(VS10XX_SDI_SBBI0_DEVICE)
00251 #endif
00252 #define SdiByte(b)          Sbbi0Byte(b)
00253 
00254 #elif defined(VS10XX_SDI_SBBI1_DEVICE) /* Data SPI device. */
00255 
00256 #include <dev/sbbif1.h>
00257 #define SdiSetMode()        Sbbi1SetMode(VS10XX_SDI_SBBI1_DEVICE, VS10XX_SDI_MODE)
00258 #define SdiSetSpeed()       Sbbi1SetSpeed(VS10XX_SDI_SBBI1_DEVICE, VS10XX_SDI_RATE)
00259 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00260 #define SdiSelect()         Sbbi1SelectDevice(VS10XX_SDI_SBBI1_DEVICE)
00261 #define SdiDeselect()       Sbbi1DeselectDevice(VS10XX_SDI_SBBI1_DEVICE)
00262 #else
00263 #define SdiSelect()         Sbbi1NegSelectDevice(VS10XX_SDI_SBBI1_DEVICE)
00264 #define SdiDeselect()       Sbbi1NegDeselectDevice(VS10XX_SDI_SBBI1_DEVICE)
00265 #endif
00266 #define SdiByte(b)          Sbbi1Byte(b)
00267 
00268 #elif defined(VS10XX_SDI_SBBI2_DEVICE) /* Data SPI device. */
00269 
00270 #include <dev/sbbif2.h>
00271 #define SdiSetMode()        Sbbi2SetMode(VS10XX_SDI_SBBI2_DEVICE, VS10XX_SDI_MODE)
00272 #define SdiSetSpeed()       Sbbi2SetSpeed(VS10XX_SDI_SBBI2_DEVICE, VS10XX_SDI_RATE)
00273 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00274 #define SdiSelect()         Sbbi2SelectDevice(VS10XX_SDI_SBBI2_DEVICE)
00275 #define SdiDeselect()       Sbbi2DeselectDevice(VS10XX_SDI_SBBI2_DEVICE)
00276 #else
00277 #define SdiSelect()         Sbbi2NegSelectDevice(VS10XX_SDI_SBBI2_DEVICE)
00278 #define SdiDeselect()       Sbbi2NegDeselectDevice(VS10XX_SDI_SBBI2_DEVICE)
00279 #endif
00280 #define SdiByte(b)          Sbbi2Byte(b)
00281 
00282 #elif defined(VS10XX_SDI_SBBI3_DEVICE) /* Data SPI device. */
00283 
00284 #include <dev/sbbif3.h>
00285 #define SdiSetMode()        Sbbi3SetMode(VS10XX_SDI_SBBI3_DEVICE, VS10XX_SDI_MODE)
00286 #define SdiSetSpeed()       Sbbi3SetSpeed(VS10XX_SDI_SBBI3_DEVICE, VS10XX_SDI_RATE)
00287 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00288 #define SdiSelect()         Sbbi3SelectDevice(VS10XX_SDI_SBBI3_DEVICE)
00289 #define SdiDeselect()       Sbbi3DeselectDevice(VS10XX_SDI_SBBI3_DEVICE)
00290 #else
00291 #define SdiSelect()         Sbbi3NegSelectDevice(VS10XX_SDI_SBBI3_DEVICE)
00292 #define SdiDeselect()       Sbbi3NegDeselectDevice(VS10XX_SDI_SBBI3_DEVICE)
00293 #endif
00294 #define SdiByte(b)          Sbbi3Byte(b)
00295 
00296 #else /* Data SPI device. */
00297 
00298 #define SdiSetMode()        (-1)
00299 #define SdiSetSpeed()
00300 #define SdiSelect()
00301 #define SdiDeselect()
00302 #define SdiByte(b)          0
00303 
00304 #endif /* Data SPI device. */
00305 
00306 /* -------------------------------------------------
00307  * AT91 port specifications.
00308  */
00309 #if MCU_AT91
00310 
00311 #if (VS10XX_SIGNAL_IRQ == INT0)
00312 #define VS10XX_SIGNAL       sig_INTERRUPT0
00313 #elif (VS10XX_SIGNAL_IRQ == INT1)
00314 #define VS10XX_SIGNAL       sig_INTERRUPT1
00315 #elif (VS10XX_SIGNAL_IRQ == INT2)
00316 #define VS10XX_SIGNAL       sig_INTERRUPT2
00317 #endif
00318 
00319 #if defined(VS10XX_XCS_BIT)
00320 
00321 #if !defined(VS10XX_XCS_PORT)
00322 #define VS10XX_XCS_PE_REG        PIO_PER
00323 #define VS10XX_XCS_OE_REG        PIO_OER
00324 #define VS10XX_XCS_COD_REG       PIO_CODR
00325 #define VS10XX_XCS_SOD_REG       PIO_SODR
00326 #elif VS10XX_XCS_PORT == PIOA_ID
00327 #define VS10XX_XCS_PE_REG        PIOA_PER
00328 #define VS10XX_XCS_OE_REG        PIOA_OER
00329 #define VS10XX_XCS_COD_REG       PIOA_CODR
00330 #define VS10XX_XCS_SOD_REG       PIOA_SODR
00331 #elif VS10XX_XCS_PORT == PIOB_ID
00332 #define VS10XX_XCS_PE_REG        PIOB_PER
00333 #define VS10XX_XCS_OE_REG        PIOB_OER
00334 #define VS10XX_XCS_COD_REG       PIOB_CODR
00335 #define VS10XX_XCS_SOD_REG       PIOB_SODR
00336 #elif VS10XX_XCS_PORT == PIOC_ID
00337 #define VS10XX_XCS_PE_REG        PIOC_PER
00338 #define VS10XX_XCS_OE_REG        PIOC_OER
00339 #define VS10XX_XCS_COD_REG       PIOC_CODR
00340 #define VS10XX_XCS_SOD_REG       PIOC_SODR
00341 #endif
00342 #define VS10XX_XCS_ENA() \
00343     outr(VS10XX_XCS_PE_REG, _BV(VS10XX_XCS_BIT)); \
00344     outr(VS10XX_XCS_OE_REG, _BV(VS10XX_XCS_BIT))
00345 #define VS10XX_XCS_CLR()   outr(VS10XX_XCS_COD_REG, _BV(VS10XX_XCS_BIT))
00346 #define VS10XX_XCS_SET()   outr(VS10XX_XCS_SOD_REG, _BV(VS10XX_XCS_BIT))
00347 
00348 #else /* VS10XX_XCS_BIT */
00349 
00350 #define VS10XX_XCS_ENA()
00351 #define VS10XX_XCS_CLR()
00352 #define VS10XX_XCS_SET()
00353 
00354 #endif /* VS10XX_XCS_BIT */
00355 
00356 #if defined(VS10XX_XDCS_BIT)
00357 
00358 #if !defined(VS10XX_XDCS_PORT)
00359 #define VS10XX_XDCS_PE_REG        PIO_PER
00360 #define VS10XX_XDCS_OE_REG        PIO_OER
00361 #define VS10XX_XDCS_COD_REG       PIO_CODR
00362 #define VS10XX_XDCS_SOD_REG       PIO_SODR
00363 #elif VS10XX_XDCS_PORT == PIOA_ID
00364 #define VS10XX_XDCS_PE_REG        PIOA_PER
00365 #define VS10XX_XDCS_OE_REG        PIOA_OER
00366 #define VS10XX_XDCS_COD_REG       PIOA_CODR
00367 #define VS10XX_XDCS_SOD_REG       PIOA_SODR
00368 #elif VS10XX_XDCS_PORT == PIOB_ID
00369 #define VS10XX_XDCS_PE_REG        PIOB_PER
00370 #define VS10XX_XDCS_OE_REG        PIOB_OER
00371 #define VS10XX_XDCS_COD_REG       PIOB_CODR
00372 #define VS10XX_XDCS_SOD_REG       PIOB_SODR
00373 #elif VS10XX_XDCS_PORT == PIOC_ID
00374 #define VS10XX_XDCS_PE_REG        PIOC_PER
00375 #define VS10XX_XDCS_OE_REG        PIOC_OER
00376 #define VS10XX_XDCS_COD_REG       PIOC_CODR
00377 #define VS10XX_XDCS_SOD_REG       PIOC_SODR
00378 #endif
00379 #define VS10XX_XDCS_ENA() \
00380     outr(VS10XX_XDCS_PE_REG, _BV(VS10XX_XDCS_BIT)); \
00381     outr(VS10XX_XDCS_OE_REG, _BV(VS10XX_XDCS_BIT))
00382 #define VS10XX_XDCS_CLR()   outr(VS10XX_XDCS_COD_REG, _BV(VS10XX_XDCS_BIT))
00383 #define VS10XX_XDCS_SET()   outr(VS10XX_XDCS_SOD_REG, _BV(VS10XX_XDCS_BIT))
00384 
00385 #else /* VS10XX_XDCS_BIT */
00386 
00387 #define VS10XX_XDCS_ENA()
00388 #define VS10XX_XDCS_CLR()
00389 #define VS10XX_XDCS_SET()
00390 
00391 #endif /* VS10XX_XDCS_BIT */
00392 
00393 #if defined(VS10XX_DREQ_BIT)
00394 
00395 #if !defined(VS10XX_DREQ_PIO_ID)
00396 #define VS10XX_DREQ_PE_REG       PIO_PER
00397 #define VS10XX_DREQ_OD_REG       PIO_ODR
00398 #define VS10XX_DREQ_PDS_REG      PIO_PDSR
00399 #elif VS10XX_DREQ_PIO_ID == PIOA_ID
00400 #define VS10XX_DREQ_PE_REG       PIOA_PER
00401 #define VS10XX_DREQ_OD_REG       PIOA_ODR
00402 #define VS10XX_DREQ_PDS_REG      PIOA_PDSR
00403 #elif VS10XX_DREQ_PIO_ID == PIOB_ID
00404 #define VS10XX_DREQ_PE_REG       PIOB_PER
00405 #define VS10XX_DREQ_OD_REG       PIOB_ODR
00406 #define VS10XX_DREQ_PDS_REG      PIOB_PDSR
00407 #elif VS10XX_DREQ_PIO_ID == PIOC_ID
00408 #define VS10XX_DREQ_PE_REG       PIOC_PER
00409 #define VS10XX_DREQ_OD_REG       PIOC_ODR
00410 #define VS10XX_DREQ_PDS_REG      PIOC_PDSR
00411 #endif
00412 
00413 #define VS10XX_DREQ_PD_REG      PIO_PDR
00414 #define VS10XX_DREQ_OD_REG      PIO_ODR
00415 #define VS10XX_DREQ_PDS_REG     PIO_PDSR
00416 #define VS10XX_DREQ_ENA() \
00417     outr(VS10XX_DREQ_PD_REG, _BV(VS10XX_DREQ_BIT)); \
00418     outr(VS10XX_DREQ_OD_REG, _BV(VS10XX_DREQ_BIT))
00419 #define VS10XX_DREQ_TST()    ((inr(VS10XX_DREQ_PDS_REG) & _BV(VS10XX_DREQ_BIT)) == _BV(VS10XX_DREQ_BIT))
00420 
00421 #else /* VS10XX_DREQ_BIT */
00422 
00423 #define VS10XX_DREQ_ENA()
00424 #define VS10XX_DREQ_TST()   0
00425 
00426 #endif /* VS10XX_DREQ_BIT */
00427 
00428 #ifdef VS10XX_BSYNC_BIT
00429 
00430 #if !defined(VS10XX_BSYNC_PIO_ID)
00431 #define VS10XX_BSYNC_PE_REG        PIO_PER
00432 #define VS10XX_BSYNC_OE_REG        PIO_OER
00433 #define VS10XX_BSYNC_COD_REG       PIO_CODR
00434 #define VS10XX_BSYNC_SOD_REG       PIO_SODR
00435 #elif VS10XX_BSYNC_PIO_ID == PIOA_ID
00436 #define VS10XX_BSYNC_PE_REG        PIOA_PER
00437 #define VS10XX_BSYNC_OE_REG        PIOA_OER
00438 #define VS10XX_BSYNC_COD_REG       PIOA_CODR
00439 #define VS10XX_BSYNC_SOD_REG       PIOA_SODR
00440 #elif VS10XX_BSYNC_PIO_ID == PIOB_ID
00441 #define VS10XX_BSYNC_PE_REG        PIOB_PER
00442 #define VS10XX_BSYNC_OE_REG        PIOB_OER
00443 #define VS10XX_BSYNC_COD_REG       PIOB_CODR
00444 #define VS10XX_BSYNC_SOD_REG       PIOB_SODR
00445 #elif VS10XX_BSYNC_PIO_ID == PIOC_ID
00446 #define VS10XX_BSYNC_PE_REG        PIOC_PER
00447 #define VS10XX_BSYNC_OE_REG        PIOC_OER
00448 #define VS10XX_BSYNC_COD_REG       PIOC_CODR
00449 #define VS10XX_BSYNC_SOD_REG       PIOC_SODR
00450 #endif
00451 #define VS10XX_BSYNC_ENA() \
00452     outr(VS10XX_BSYNC_PE_REG, _BV(VS10XX_BSYNC_BIT)); \
00453     outr(VS10XX_BSYNC_OE_REG, _BV(VS10XX_BSYNC_BIT))
00454 #define VS10XX_BSYNC_CLR()   outr(VS10XX_BSYNC_COD_REG, _BV(VS10XX_BSYNC_BIT))
00455 #define VS10XX_BSYNC_SET()   outr(VS10XX_BSYNC_SOD_REG, _BV(VS10XX_BSYNC_BIT))
00456 
00457 #else /* VS10XX_BSYNC_BIT */
00458 
00459 #define VS10XX_BSYNC_ENA()
00460 #define VS10XX_BSYNC_CLR()
00461 #define VS10XX_BSYNC_SET()
00462 
00463 #endif /* VS10XX_BSYNC_BIT */
00464 
00465 
00466 /* -------------------------------------------------
00467  * AVR port specifications.
00468  */
00469 #elif defined(__AVR__)
00470 
00471 #if !defined(VS10XX_SIGNAL_IRQ)
00472 #define VS10XX_SIGNAL_IRQ   INT6
00473 #endif
00474 
00475 #if (VS10XX_SIGNAL_IRQ == INT0)
00476 #define VS10XX_SIGNAL       sig_INTERRUPT0
00477 #define VS10XX_DREQ_BIT     0
00478 #define VS10XX_DREQ_PDS_REG PIND
00479 #define VS10XX_DREQ_PUE_REG PORTD
00480 #define VS10XX_DREQ_OE_REG  DDRD
00481 
00482 #elif (VS10XX_SIGNAL_IRQ == INT1)
00483 #define VS10XX_SIGNAL       sig_INTERRUPT1
00484 #define VS10XX_DREQ_BIT     1
00485 #define VS10XX_DREQ_PDS_REG PIND
00486 #define VS10XX_DREQ_PUE_REG PORTD
00487 #define VS10XX_DREQ_OE_REG  DDRD
00488 
00489 #elif (VS10XX_SIGNAL_IRQ == INT2)
00490 #define VS10XX_SIGNAL       sig_INTERRUPT2
00491 #define VS10XX_DREQ_BIT     2
00492 #define VS10XX_DREQ_PDS_REG PIND
00493 #define VS10XX_DREQ_PUE_REG PORTD
00494 #define VS10XX_DREQ_OE_REG  DDRD
00495 
00496 #elif (VS10XX_SIGNAL_IRQ == INT3)
00497 #define VS10XX_SIGNAL       sig_INTERRUPT3
00498 #define VS10XX_DREQ_BIT     3
00499 #define VS10XX_DREQ_PDS_REG PIND
00500 #define VS10XX_DREQ_PUE_REG PORTD
00501 #define VS10XX_DREQ_OE_REG  DDRD
00502 
00503 #elif (VS10XX_SIGNAL_IRQ == INT4)
00504 #define VS10XX_SIGNAL       sig_INTERRUPT4
00505 #define VS10XX_DREQ_BIT     4
00506 #define VS10XX_DREQ_PDS_REG PINE
00507 #define VS10XX_DREQ_PUE_REG PORTE
00508 #define VS10XX_DREQ_OE_REG  DDRE
00509 
00510 #elif (VS10XX_SIGNAL_IRQ == INT5)
00511 #define VS10XX_SIGNAL       sig_INTERRUPT5
00512 #define VS10XX_DREQ_BIT     5
00513 #define VS10XX_DREQ_PDS_REG PINE
00514 #define VS10XX_DREQ_PUE_REG PORTE
00515 #define VS10XX_DREQ_OE_REG  DDRE
00516 
00517 #elif (VS10XX_SIGNAL_IRQ == INT7)
00518 #define VS10XX_SIGNAL       sig_INTERRUPT7
00519 #define VS10XX_DREQ_BIT     7
00520 #define VS10XX_DREQ_PDS_REG PINE
00521 #define VS10XX_DREQ_PUE_REG PORTE
00522 #define VS10XX_DREQ_OE_REG  DDRE
00523 
00524 #else
00525 #define VS10XX_SIGNAL       sig_INTERRUPT6
00526 #define VS10XX_DREQ_BIT     6
00527 #define VS10XX_DREQ_PDS_REG PINE
00528 #define VS10XX_DREQ_PUE_REG PORTE
00529 #define VS10XX_DREQ_OE_REG  DDRE
00530 
00531 #endif
00532 
00533 #define VS10XX_DREQ_ENA() \
00534     cbi(VS10XX_DREQ_OE_REG, VS10XX_DREQ_BIT); \
00535     sbi(VS10XX_DREQ_PUE_REG, VS10XX_DREQ_BIT)
00536 #define VS10XX_DREQ_TST()    ((inb(VS10XX_DREQ_PDS_REG) & _BV(VS10XX_DREQ_BIT)) == _BV(VS10XX_DREQ_BIT))
00537 
00538 
00539 #if defined(VS10XX_XCS_BIT)
00540 
00541 #if (VS10XX_XCS_PORT == AVRPORTA)
00542 #define VS10XX_XCS_SOD_REG  PORTA
00543 #define VS10XX_XCS_OE_REG   DDRA
00544 #elif (VS10XX_XCS_PORT == AVRPORTB)
00545 #define VS10XX_XCS_SOD_REG  PORTB
00546 #define VS10XX_XCS_OE_REG   DDRB
00547 #elif (VS10XX_XCS_PORT == AVRPORTD)
00548 #define VS10XX_XCS_SOD_REG  PORTD
00549 #define VS10XX_XCS_OE_REG   DDRD
00550 #elif (VS10XX_XCS_PORT == AVRPORTE)
00551 #define VS10XX_XCS_SOD_REG  PORTE
00552 #define VS10XX_XCS_OE_REG   DDRE
00553 #elif (VS10XX_XCS_PORT == AVRPORTF)
00554 #define VS10XX_XCS_SOD_REG  PORTF
00555 #define VS10XX_XCS_OE_REG   DDRF
00556 #elif (VS10XX_XCS_PORT == AVRPORTG)
00557 #define VS10XX_XCS_SOD_REG  PORTG
00558 #define VS10XX_XCS_OE_REG   DDRG
00559 #elif (VS10XX_XCS_PORT == AVRPORTH)
00560 #define VS10XX_XCS_SOD_REG  PORTH
00561 #define VS10XX_XCS_OE_REG   DDRH
00562 #endif
00563 #define VS10XX_XCS_ENA()      sbi(VS10XX_XCS_OE_REG, VS10XX_XCS_BIT)
00564 #define VS10XX_XCS_CLR()      cbi(VS10XX_XCS_SOD_REG, VS10XX_XCS_BIT)
00565 #define VS10XX_XCS_SET()      sbi(VS10XX_XCS_SOD_REG, VS10XX_XCS_BIT)
00566 
00567 #else /* VS10XX_XCS_BIT */
00568 
00569 #define VS10XX_XCS_ENA()
00570 #define VS10XX_XCS_CLR()
00571 #define VS10XX_XCS_SET()
00572 
00573 #endif /* VS10XX_XCS_BIT */
00574 
00575 #if defined(VS10XX_XDCS_BIT)
00576 
00577 #if (VS10XX_XDCS_PORT == AVRPORTA)
00578 #define VS10XX_XDCS_SOD_REG  PORTA
00579 #define VS10XX_XDCS_OE_REG   DDRA
00580 #elif (VS10XX_XDCS_PORT == AVRPORTB)
00581 #define VS10XX_XDCS_SOD_REG  PORTB
00582 #define VS10XX_XDCS_OE_REG   DDRB
00583 #elif (VS10XX_XDCS_PORT == AVRPORTD)
00584 #define VS10XX_XDCS_SOD_REG  PORTD
00585 #define VS10XX_XDCS_OE_REG   DDRD
00586 #elif (VS10XX_XDCS_PORT == AVRPORTE)
00587 #define VS10XX_XDCS_SOD_REG  PORTE
00588 #define VS10XX_XDCS_OE_REG   DDRE
00589 #elif (VS10XX_XDCS_PORT == AVRPORTF)
00590 #define VS10XX_XDCS_SOD_REG  PORTF
00591 #define VS10XX_XDCS_OE_REG   DDRF
00592 #elif (VS10XX_XDCS_PORT == AVRPORTG)
00593 #define VS10XX_XDCS_SOD_REG  PORTG
00594 #define VS10XX_XDCS_OE_REG   DDRG
00595 #elif (VS10XX_XDCS_PORT == AVRPORTH)
00596 #define VS10XX_XDCS_SOD_REG  PORTH
00597 #define VS10XX_XDCS_OE_REG   DDRH
00598 #endif
00599 #define VS10XX_XDCS_ENA()      sbi(VS10XX_XDCS_OE_REG, VS10XX_XDCS_BIT)
00600 #define VS10XX_XDCS_CLR()      cbi(VS10XX_XDCS_SOD_REG, VS10XX_XDCS_BIT)
00601 #define VS10XX_XDCS_SET()      sbi(VS10XX_XDCS_SOD_REG, VS10XX_XDCS_BIT)
00602 
00603 #else /* VS10XX_XDCS_BIT */
00604 
00605 #define VS10XX_XDCS_ENA()
00606 #define VS10XX_XDCS_CLR()
00607 #define VS10XX_XDCS_SET()
00608 
00609 #endif /* VS10XX_XDCS_BIT */
00610 
00611 
00612 #if defined(VS10XX_BSYNC_BIT)
00613 
00614 #if (VS10XX_BSYNC_AVRPORT == AVRPORTA)
00615 #define VS10XX_BSYNC_SOD_REG  PORTA
00616 #define VS10XX_BSYNC_OE_REG   DDRA
00617 #elif (VS10XX_BSYNC_AVRPORT == AVRPORTB)
00618 #define VS10XX_BSYNC_SOD_REG  PORTB
00619 #define VS10XX_BSYNC_OE_REG   DDRB
00620 #elif (VS10XX_BSYNC_AVRPORT == AVRPORTD)
00621 #define VS10XX_BSYNC_SOD_REG  PORTD
00622 #define VS10XX_BSYNC_OE_REG   DDRD
00623 #elif (VS10XX_BSYNC_AVRPORT == AVRPORTE)
00624 #define VS10XX_BSYNC_SOD_REG  PORTE
00625 #define VS10XX_BSYNC_OE_REG   DDRE
00626 #elif (VS10XX_BSYNC_AVRPORT == AVRPORTF)
00627 #define VS10XX_BSYNC_SOD_REG  PORTF
00628 #define VS10XX_BSYNC_OE_REG   DDRF
00629 #elif (VS10XX_BSYNC_AVRPORT == AVRPORTG)
00630 #define VS10XX_BSYNC_SOD_REG  PORTG
00631 #define VS10XX_BSYNC_OE_REG   DDRG
00632 #elif (VS10XX_BSYNC_AVRPORT == AVRPORTH)
00633 #define VS10XX_BSYNC_SOD_REG  PORTH
00634 #define VS10XX_BSYNC_OE_REG   DDRH
00635 #endif
00636 #define VS10XX_BSYNC_ENA()      sbi(VS10XX_BSYNC_OE_REG, VS10XX_BSYNC_BIT)
00637 #define VS10XX_BSYNC_CLR()      cbi(VS10XX_BSYNC_SOD_REG, VS10XX_BSYNC_BIT)
00638 #define VS10XX_BSYNC_SET()      sbi(VS10XX_BSYNC_SOD_REG, VS10XX_BSYNC_BIT)
00639 
00640 #else /* VS10XX_BSYNC_BIT */
00641 
00642 #define VS10XX_BSYNC_ENA()
00643 #define VS10XX_BSYNC_CLR()
00644 #define VS10XX_BSYNC_SET()
00645 
00646 #endif /* VS10XX_BSYNC_BIT */
00647 
00648 
00649 /* -------------------------------------------------
00650  * End of port specifications.
00651  */
00652 #endif
00653 
00654 
00655 static volatile ureg_t vs_status = VS_STATUS_STOPPED;
00656 static volatile unsigned int vs_flush;
00657 
00658 /*
00659  * \brief Write a byte to the VS10XX data interface.
00660  *
00661  * The caller is responsible for checking the DREQ line. Also make sure,
00662  * that decoder interrupts are disabled.
00663  *
00664  * \param b Byte to be shifted to the decoder's data interface.
00665  */
00666 static INLINE void VsSdiPutByte(ureg_t b)
00667 {
00668 #if defined(VS10XX_BSYNC_BIT)
00669 
00670 #if defined(VS10XX_SDI_SBBI0_DEVICE) /* VS10XX_SDI_DEVICE */
00671     ureg_t mask;
00672 
00673     VS10XX_BSYNC_SET();
00674 
00675     for (mask = 0x80; mask; mask >>= 1) {
00676         SBBI0_SCK_CLR();
00677         if (b & mask) {
00678             SBBI0_MOSI_SET();
00679         }
00680         else {
00681             SBBI0_MOSI_CLR();
00682         }
00683         SBBI0_SCK_SET();
00684         if (mask & 0x40) {
00685             VS10XX_BSYNC_CLR();
00686         }
00687     }
00688     SBBI0_SCK_CLR();
00689 #elif defined(VS10XX_SDI_SBBI1_DEVICE) /* VS10XX_SDI_DEVICE */
00690     ureg_t mask;
00691 
00692     VS10XX_BSYNC_SET();
00693 
00694     for (mask = 0x80; mask; mask >>= 1) {
00695         SBBI1_SCK_CLR();
00696         if (b & mask) {
00697             SBBI1_MOSI_SET();
00698         }
00699         else {
00700             SBBI1_MOSI_CLR();
00701         }
00702         SBBI1_SCK_SET();
00703         if (mask & 0x40) {
00704             VS10XX_BSYNC_CLR();
00705         }
00706     }
00707     SBBI1_SCK_CLR();
00708 #elif defined(VS10XX_SDI_SBBI2_DEVICE) /* VS10XX_SDI_DEVICE */
00709     ureg_t mask;
00710 
00711     VS10XX_BSYNC_SET();
00712 
00713     for (mask = 0x80; mask; mask >>= 1) {
00714         SBBI2_SCK_CLR();
00715         if (b & mask) {
00716             SBBI2_MOSI_SET();
00717         }
00718         else {
00719             SBBI2_MOSI_CLR();
00720         }
00721         SBBI2_SCK_SET();
00722         if (mask & 0x40) {
00723             VS10XX_BSYNC_CLR();
00724         }
00725     }
00726     SBBI2_SCK_CLR();
00727 #elif defined(VS10XX_SDI_SBBI3_DEVICE) /* VS10XX_SDI_DEVICE */
00728     ureg_t mask;
00729 
00730     VS10XX_BSYNC_SET();
00731 
00732     for (mask = 0x80; mask; mask >>= 1) {
00733         SBBI3_SCK_CLR();
00734         if (b & mask) {
00735             SBBI3_MOSI_SET();
00736         }
00737         else {
00738             SBBI3_MOSI_CLR();
00739         }
00740         SBBI3_SCK_SET();
00741         if (mask & 0x40) {
00742             VS10XX_BSYNC_CLR();
00743         }
00744     }
00745     SBBI3_SCK_CLR();
00746 #elif defined(VS10XX_SDI_SPI0_DEVICE) /* VS10XX_SDI_DEVICE */
00747     VS10XX_BSYNC_SET();
00748 
00749     outb(SPDR, b);
00750 
00751     _NOP();
00752     _NOP();
00753     _NOP();
00754     _NOP();
00755     VS10XX_BSYNC_CLR();
00756 
00757     /* Wait for SPI transfer to finish. */
00758     loop_until_bit_is_set(SPSR, SPIF);
00759 #endif  /* VS10XX_SDI_DEVICE */
00760 
00761 #else  /* !VS10XX_BSYNC_BIT */
00762 
00763     (void)SdiByte(b);
00764 
00765 #endif /* !VS10XX_BSYNC_BIT */
00766 
00767 }
00768 
00780 ureg_t VsPlayerInterrupts(ureg_t enable)
00781 {
00782     static ureg_t is_enabled = 0;
00783     ureg_t rc;
00784 
00785     rc = is_enabled;
00786     if(enable) {
00787         VS10XX_DREQ_ENA();
00788         NutIrqEnable(&VS10XX_SIGNAL);
00789     }
00790     else {
00791         NutIrqDisable(&VS10XX_SIGNAL);
00792     }
00793     is_enabled = enable;
00794 
00795     return rc;
00796 }
00797 
00822 ureg_t VsPlayerThrottle(ureg_t on)
00823 {
00824     static ureg_t is_throttled = 0;
00825     ureg_t rc;
00826 
00827     rc = is_throttled;
00828     if(on) {
00829         VS10XX_XDCS_SET();
00830         SdiDeselect();
00831     }
00832     else {
00833         VS10XX_XDCS_CLR();
00834         SdiSelect();
00835     }
00836     is_throttled = on;
00837 
00838     return rc;
00839 }
00840 
00844 static void VsSciSelect(ureg_t on)
00845 {
00846     if (on) {
00847         /* Disable data interface. */
00848         SdiDeselect();
00849 
00850 #if defined(VS10XX_SDI_SPI0_DEVICE) && !defined(VS10XX_SCI_SPI0_DEVICE)
00851         /* Hint given by Jesper Hansen: If data channel uses HW SPI and 
00852            command channel uses SW SPI, then disable HW SPI while sending 
00853            using the command channel. */
00854         cbi(SPCR, SPE);
00855 #endif
00856 
00857         /* Deselect data channel. */
00858         VS10XX_XDCS_SET();
00859         /* Select cmd channel. */
00860         VS10XX_XCS_CLR();
00861         /* Enable cmd interface. */
00862         SciSelect();
00863     }
00864     else {
00865         /* Disable cmd interface. */
00866         SciDeselect();
00867         /* Deselect cmd channel. */
00868         VS10XX_XCS_SET();
00869         /* Re-select data channel. */
00870         VS10XX_XDCS_CLR();
00871         /* Enable data interface. */
00872         SdiSelect();
00873     }
00874 }
00875 
00882 static int VsWaitReady(void)
00883 {
00884     int tmo;
00885 
00886     for (tmo = 0; tmo < 5000; tmo++) {
00887         if (VS10XX_DREQ_TST()) {
00888             return 0;
00889         }
00890     }
00891     return -1;
00892 }
00893 
00894 /*
00895  * \brief Write a specified number of bytes to the VS10XX data interface.
00896  *
00897  * This function will check the DREQ line. Decoder interrupts must have 
00898  * been disabled before calling this function.
00899  */
00900 static int VsSdiWrite(CONST uint8_t * data, size_t len)
00901 {
00902     while (len--) {
00903         if (!VS10XX_DREQ_TST() && VsWaitReady()) {
00904             return -1;
00905         }
00906         VsSdiPutByte(*data);
00907         data++;
00908     }
00909     return 0;
00910 }
00911 
00912 /*
00913  * \brief Write a specified number of bytes from program space to the 
00914  *        VS10XX data interface.
00915  *
00916  * This function is similar to VsSdiWrite() except that the data is 
00917  * located in program space.
00918  */
00919 static int VsSdiWrite_P(PGM_P data, size_t len)
00920 {
00921     while (len--) {
00922         if (!VS10XX_DREQ_TST() && VsWaitReady()) {
00923             return -1;
00924         }
00925         VsSdiPutByte(PRG_RDB(data));
00926         data++;
00927     }
00928     return 0;
00929 }
00930 
00931 /*
00932  * \brief Write to a decoder register.
00933  *
00934  * Decoder interrupts must have been disabled before calling this function.
00935  */
00936 static void VsRegWrite(ureg_t reg, uint16_t data)
00937 {
00938     /* Select command channel. */
00939     VsWaitReady();
00940     VsSciSelect(1);
00941     /*
00942      * The VS1011E datasheet demands a minimum of 5 ns between
00943      * the falling CS and the first rising SCK. This is a very
00944      * short time and doesn't require any additional delay
00945      * even on very fast CPUs.
00946      */
00947     (void)SciByte(VS_OPCODE_WRITE);
00948     (void)SciByte((uint8_t) reg);
00949     (void)SciByte((uint8_t) (data >> 8));
00950     (void)SciByte((uint8_t) data);
00951 
00952     /* Re-select data channel. */
00953     VsSciSelect(0);
00954 }
00955 
00956 /*
00957  * \brief Read from a register.
00958  *
00959  * Decoder interrupts must have been disabled before calling this function.
00960  * 
00961  * \return Register contents.
00962  */
00963 static uint16_t VsRegRead(ureg_t reg)
00964 {
00965     uint16_t data;
00966 
00967     /* Select command channel. */
00968     VsWaitReady();
00969     VsSciSelect(1);
00970 
00971     (void)SciByte(VS_OPCODE_READ);
00972     (void)SciByte((uint8_t) reg);
00973     data = (uint16_t)SciByte(0) << 8;
00974     data |= SciByte(0);
00975 
00976     /* Select data channel. */
00977     VsSciSelect(0);
00978 
00979     return data;
00980 }
00981 
00982 /*
00983  * \brief Feed the decoder with data.
00984  *
00985  * This function serves two purposes: 
00986  * - It is called by VsPlayerKick() to initially fill the decoder buffer.
00987  * - It is used as an interrupt handler for the decoder.
00988  */
00989 static void VsPlayerFeed(void *arg)
00990 {
00991     ureg_t j = 32;
00992     size_t total = 0;
00993 
00994     if (!VS10XX_DREQ_TST()) {
00995         return;
00996     }
00997 
00998     /* 
00999      * Feed the decoder until its buffer is full or we ran out of data.
01000      */
01001     if (vs_status == VS_STATUS_RUNNING) {
01002         char *bp = 0;
01003         size_t consumed = 0;
01004         size_t available = 0;
01005         do {
01006             if(consumed >= available) {
01007                 /* Commit previously consumed bytes. */
01008                 if(consumed) {
01009                     NutSegBufReadCommit(consumed);
01010                     consumed = 0;
01011                 }
01012                 /* All bytes consumed, request new. */
01013                 bp = NutSegBufReadRequest(&available);
01014                 if(available == 0) {
01015                     /* End of stream. */
01016                     vs_status = VS_STATUS_EOF;
01017                     break;
01018                 }
01019             }
01020             /* We have some data in the buffer, feed it. */
01021             VsSdiPutByte(*bp);
01022             bp++;
01023             consumed++;
01024             total++;
01025             if (total > 4096) {
01026                 vs_status = VS_STATUS_EOF;
01027                 break;
01028             }
01029 
01030             /* Allow 32 bytes to be sent as long as DREQ is set, This includes
01031                the one in progress. */
01032             if (VS10XX_DREQ_TST()) {
01033                 j = 32;
01034             }
01035         } while(j--);
01036 
01037         /* Finally re-enable the producer buffer. */
01038         NutSegBufReadLast(consumed);
01039     }
01040 
01041     /* 
01042      * Flush the internal VS buffer. 
01043      */
01044     if(vs_status != VS_STATUS_RUNNING && vs_flush) {
01045         do {
01046             VsSdiPutByte(0);
01047             if (--vs_flush == 0) {
01048                 /* Decoder internal buffer is flushed. */
01049                 vs_status = VS_STATUS_EMPTY;
01050                 break;
01051             }
01052             /* Allow 32 bytes to be sent as long as DREQ is set, This includes
01053                the one in progress. */
01054             if (VS10XX_DREQ_TST()) {
01055                 j = 32;
01056             }
01057         } while(j--);
01058     }
01059 }
01060 
01072 int VsPlayerKick(void)
01073 {
01074     /*
01075      * Start feeding the decoder with data.
01076      */
01077     VsPlayerInterrupts(0);
01078     vs_status = VS_STATUS_RUNNING;
01079     VsPlayerFeed(NULL);
01080     VsPlayerInterrupts(1);
01081 
01082     return 0;
01083 }
01084 
01093 int VsPlayerStop(void)
01094 {
01095     ureg_t ief;
01096 
01097     ief = VsPlayerInterrupts(0);
01098     /* Check whether we need to stop at all to not overwrite other than running status */
01099     if (vs_status == VS_STATUS_RUNNING) {
01100         vs_status = VS_STATUS_STOPPED;
01101     }
01102     VsPlayerInterrupts(ief);
01103 
01104     return 0;
01105 }
01106 
01107 
01120 int VsPlayerFlush(void)
01121 {
01122     VsPlayerInterrupts(0);
01123     /* Set up fluhing unless both buffers are empty. */
01124     if (vs_status != VS_STATUS_EMPTY || NutSegBufUsed()) {
01125         if (vs_flush == 0) {
01126             vs_flush = VS_FLUSH_BYTES;
01127         }
01128         /* start the playback if necessary */
01129         if (vs_status != VS_STATUS_RUNNING) {
01130             VsPlayerKick();
01131         }
01132     }
01133     VsPlayerInterrupts(1);
01134 
01135     return 0;
01136 }
01137 
01143 int VsPlayerInit(void)
01144 {
01145     /* Disable decoder interrupts. */
01146     VsPlayerInterrupts(0);
01147 
01148     /* Keep decoder in reset state. */
01149     SciReset(1);
01150 
01151     /* Initialize command channel. */
01152     if (SciSetMode()) {
01153         return -1;
01154     }
01155     SciSetSpeed();
01156     SciDeselect();
01157 
01158     /* Initialize data channel. */
01159     if (SdiSetMode()) {
01160         return -1;
01161     }
01162     SdiSetSpeed();
01163     SdiDeselect();
01164 
01165     /* Set BSYNC output low. */
01166     VS10XX_BSYNC_CLR();
01167     VS10XX_BSYNC_ENA();
01168 
01169     /* Set low active data channel select output low. */
01170     VS10XX_XDCS_SET();
01171     VS10XX_XDCS_ENA();
01172 
01173     /* Set low active command channel select output high. */
01174     VS10XX_XCS_SET();
01175     VS10XX_XCS_ENA();
01176 
01177     /* Enable DREQ interrupt input. */
01178     VS10XX_DREQ_ENA();
01179 
01180     /* Register the interrupt routine */
01181     if (NutRegisterIrqHandler(&VS10XX_SIGNAL, VsPlayerFeed, NULL)) {
01182         return -1;
01183     }
01184 
01185     /* Rising edge will generate an interrupt. */
01186     NutIrqSetMode(&VS10XX_SIGNAL, NUT_IRQMODE_RISINGEDGE);
01187 
01188     /* Release decoder reset line. */
01189     SciReset(0);
01190     NutDelay(VS10XX_HWRST_RECOVER);
01191 
01192     return VsPlayerReset(0);
01193 }
01194 
01221 int VsPlayerReset(uint16_t mode)
01222 {
01223     /* Disable decoder interrupts and feeding. */
01224     VsPlayerInterrupts(0);
01225     vs_status = VS_STATUS_STOPPED;
01226 
01227     /* Software reset, set modes of decoder. */
01228 #if defined(VS10XX_BSYNC_BIT)
01229     VsRegWrite(VS_MODE_REG, VS_SM_RESET | mode);
01230 #else
01231     VsRegWrite(VS_MODE_REG, VS_SM_RESET | VS_SM_SDINEW | mode);
01232 #endif
01233     /* The decoder needs 9600 XTAL cycles. This is at least twice. */
01234     NutDelay(VS10XX_SWRST_RECOVER);
01235 
01236     /*
01237      * Check for correct reset.
01238      */
01239     if ((mode & VS_SM_RESET) != 0 || !VS10XX_DREQ_TST()) {
01240         /* If not succeeded, give it one more chance and try hw reset. */
01241         SciReset(1);
01242         /* No idea how long we must held reset low. */
01243         NutDelay(VS10XX_HWRST_DURATION);
01244         SciReset(0);
01245         /* No idea how long we need to wait here. */
01246         NutDelay(VS10XX_HWRST_RECOVER);
01247 
01248         /* Set the requested modes. */
01249 #if defined(VS10XX_BSYNC_BIT)
01250         VsRegWrite(VS_MODE_REG, VS_SM_RESET | mode);
01251 #else
01252         VsRegWrite(VS_MODE_REG, VS_SM_RESET | VS_SM_SDINEW | mode);
01253 #endif
01254         NutDelay(VS10XX_SWRST_RECOVER);
01255         if (!VS10XX_DREQ_TST()) {
01256             return -1;
01257         }
01258     }
01259 
01260 #if VS10XX_FREQ < 20000000UL
01261     VsRegWrite(VS_CLOCKF_REG, (uint16_t)(VS_CF_DOUBLER | (VS10XX_FREQ / 2000UL)));
01262 #else
01263     VsRegWrite(VS_CLOCKF_REG, (uint16_t)(VS10XX_FREQ / 2000UL));
01264 #endif
01265 #if defined(AUDIO_VS1001K)
01266     /* Force frequency change (see datasheet). */
01267     VsRegWrite(VS_INT_FCTLH_REG, 0x8008);
01268 #endif
01269     NutDelay(1);
01270 
01271 #if defined(VS10XX_SDI_SPI0_DEVICE) || defined(VS10XX_SCI_SPI0_DEVICE)
01272     /* Clear any spurious interrupts. */
01273     outb(EIFR, BV(VS10XX_DREQ_BIT));
01274 #endif
01275 
01276     return 0;
01277 }
01278 
01302 int VsPlayerSetMode(uint16_t mode)
01303 {
01304     ureg_t ief;
01305 
01306     ief = VsPlayerInterrupts(0);
01307 #if defined(VS10XX_BSYNC_BIT)
01308     VsRegWrite(VS_MODE_REG, mode);
01309 #else
01310     VsRegWrite(VS_MODE_REG, VS_SM_SDINEW | mode);
01311 #endif
01312     VsPlayerInterrupts(ief);
01313 
01314     return 0;
01315 }
01316 
01322 uint16_t VsPlayTime(void)
01323 {
01324     uint16_t rc;
01325     ureg_t ief;
01326 
01327     ief = VsPlayerInterrupts(0);
01328     rc = VsRegRead(VS_DECODE_TIME_REG);
01329     VsPlayerInterrupts(ief);
01330 
01331     return rc;
01332 }
01333 
01343 unsigned int VsGetStatus(void)
01344 {
01345     return vs_status;
01346 }
01347 
01348 #ifdef __GNUC__
01349 
01357 int VsGetHeaderInfo(VS_HEADERINFO * vshi)
01358 {
01359     uint16_t *usp = (uint16_t *) vshi;
01360     ureg_t ief;
01361 
01362     ief = VsPlayerInterrupts(0);
01363     *usp = VsRegRead(VS_HDAT1_REG);
01364     *++usp = VsRegRead(VS_HDAT0_REG);
01365     VsPlayerInterrupts(ief);
01366 
01367     return 0;
01368 }
01369 #endif
01370 
01383 uint16_t VsMemoryTest(void)
01384 {
01385     uint16_t rc;
01386     ureg_t ief;
01387     static prog_char mtcmd[] = { 0x4D, 0xEA, 0x6D, 0x54, 0x00, 0x00, 0x00, 0x00 };
01388 
01389     ief = VsPlayerInterrupts(0);
01390 #if defined(VS10XX_BSYNC_BIT)
01391     VsRegWrite(VS_MODE_REG, VS_SM_TESTS);
01392 #else
01393     VsRegWrite(VS_MODE_REG, VS_SM_TESTS | VS_SM_SDINEW);
01394 #endif
01395     VsSdiWrite_P(mtcmd, sizeof(mtcmd));
01396     while(((rc = VsRegRead(VS_HDAT0_REG)) & 0x8000) == 0) {
01397         NutDelay(1);
01398     }
01399 #if defined(VS10XX_BSYNC_BIT)
01400     VsRegWrite(VS_MODE_REG, 0);
01401 #else
01402     VsRegWrite(VS_MODE_REG, VS_SM_SDINEW);
01403 #endif
01404     VsPlayerInterrupts(ief);
01405 
01406     return rc;
01407 }
01408 
01418 int VsSetVolume(ureg_t left, ureg_t right)
01419 {
01420     ureg_t ief;
01421 
01422     ief = VsPlayerInterrupts(0);
01423     VsRegWrite(VS_VOL_REG, ((uint16_t)left << VS_VOL_LEFT_LSB) | ((uint16_t)right << VS_VOL_RIGHT_LSB));
01424     VsPlayerInterrupts(ief);
01425 
01426     return 0;
01427 }
01428 
01437 int VsBeep(uint8_t fsin, uint8_t ms)
01438 {
01439     ureg_t ief;
01440     static prog_char on[] = { 0x53, 0xEF, 0x6E };
01441     static prog_char off[] = { 0x45, 0x78, 0x69, 0x74 };
01442     static prog_char end[] = { 0x00, 0x00, 0x00, 0x00 };
01443 
01444     /* Disable decoder interrupts. */
01445     ief = VsPlayerInterrupts(0);
01446 
01447 #if defined(VS10XX_BSYNC_BIT)
01448     VsRegWrite(VS_MODE_REG, VS_SM_TESTS);
01449 #else
01450     VsRegWrite(VS_MODE_REG, VS_SM_TESTS | VS_SM_SDINEW);
01451 #endif
01452 
01453     fsin = 56 + (fsin & 7) * 9;
01454     VsSdiWrite_P(on, sizeof(on));
01455     VsSdiWrite(&fsin, 1);
01456     VsSdiWrite_P(end, sizeof(end));
01457     NutDelay(ms);
01458     VsSdiWrite_P(off, sizeof(off));
01459     VsSdiWrite_P(end, sizeof(end));
01460 
01461 #if defined(VS10XX_BSYNC_BIT)
01462     VsRegWrite(VS_MODE_REG, 0);
01463 #else
01464     VsRegWrite(VS_MODE_REG, VS_SM_SDINEW);
01465 #endif
01466 
01467     /* Restore decoder interrupt enable. */
01468     VsPlayerInterrupts(ief);
01469 
01470     return 0;
01471 }
01472 
01473 

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