usart1at91.c

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00001 /*
00002  * Copyright (C) 2005 by egnite Software GmbH
00003  * Copyright 2009 by egnite GmbH
00004  *
00005  * All rights reserved.
00006  *
00007  * Redistribution and use in source and binary forms, with or without
00008  * modification, are permitted provided that the following conditions
00009  * are met:
00010  *
00011  * 1. Redistributions of source code must retain the above copyright
00012  *    notice, this list of conditions and the following disclaimer.
00013  * 2. Redistributions in binary form must reproduce the above copyright
00014  *    notice, this list of conditions and the following disclaimer in the
00015  *    documentation and/or other materials provided with the distribution.
00016  * 3. Neither the name of the copyright holders nor the names of
00017  *    contributors may be used to endorse or promote products derived
00018  *    from this software without specific prior written permission.
00019  *
00020  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
00021  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00022  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00023  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
00024  * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
00025  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
00026  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
00027  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
00028  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00029  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
00030  * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
00031  * SUCH DAMAGE.
00032  *
00033  * For additional information see http://www.ethernut.de/
00034  */
00035 
00036 /*
00037  * $Id: usart1at91.c 2682 2009-09-11 12:27:11Z haraldkipp $
00038  */
00039 
00040 #include <cfg/os.h>
00041 #include <cfg/clock.h>
00042 #include <cfg/arch.h>
00043 #include <cfg/uart.h>
00044 #include <cfg/arch/gpio.h>
00045 
00046 #include <string.h>
00047 
00048 #include <sys/atom.h>
00049 #include <sys/event.h>
00050 #include <sys/timer.h>
00051 
00052 #include <dev/irqreg.h>
00053 #include <dev/usartat91.h>
00054 
00055 #ifndef NUT_CPU_FREQ
00056 #ifdef NUT_PLL_CPUCLK
00057 #include <dev/cy2239x.h>
00058 #else /* !NUT_PLL_CPUCLK */
00059 #define NUT_CPU_FREQ    73728000UL
00060 #endif /* !NUT_PLL_CPUCLK */
00061 #endif /* !NUT_CPU_FREQ */
00062 
00063 /*
00064  * Local function prototypes.
00065  */
00066 static uint32_t At91UsartGetSpeed(void);
00067 static int At91UsartSetSpeed(uint32_t rate);
00068 static uint8_t At91UsartGetDataBits(void);
00069 static int At91UsartSetDataBits(uint8_t bits);
00070 static uint8_t At91UsartGetParity(void);
00071 static int At91UsartSetParity(uint8_t mode);
00072 static uint8_t At91UsartGetStopBits(void);
00073 static int At91UsartSetStopBits(uint8_t bits);
00074 static uint32_t At91UsartGetFlowControl(void);
00075 static int At91UsartSetFlowControl(uint32_t flags);
00076 static uint32_t At91UsartGetStatus(void);
00077 static int At91UsartSetStatus(uint32_t flags);
00078 static uint8_t At91UsartGetClockMode(void);
00079 static int At91UsartSetClockMode(uint8_t mode);
00080 static void At91UsartTxStart(void);
00081 static void At91UsartRxStart(void);
00082 static int At91UsartInit(void);
00083 static int At91UsartDeinit(void);
00084 
00089 
00093 static USARTDCB dcb_usart1 = {
00094     0,                          /* dcb_modeflags */
00095     0,                          /* dcb_statusflags */
00096     0,                          /* dcb_rtimeout */
00097     0,                          /* dcb_wtimeout */
00098     {0, 0, 0, 0, 0, 0, 0, 0},   /* dcb_tx_rbf */
00099     {0, 0, 0, 0, 0, 0, 0, 0},   /* dcb_rx_rbf */
00100     0,                          /* dbc_last_eol */
00101     At91UsartInit,              /* dcb_init */
00102     At91UsartDeinit,            /* dcb_deinit */
00103     At91UsartTxStart,           /* dcb_tx_start */
00104     At91UsartRxStart,           /* dcb_rx_start */
00105     At91UsartSetFlowControl,    /* dcb_set_flow_control */
00106     At91UsartGetFlowControl,    /* dcb_get_flow_control */
00107     At91UsartSetSpeed,          /* dcb_set_speed */
00108     At91UsartGetSpeed,          /* dcb_get_speed */
00109     At91UsartSetDataBits,       /* dcb_set_data_bits */
00110     At91UsartGetDataBits,       /* dcb_get_data_bits */
00111     At91UsartSetParity,         /* dcb_set_parity */
00112     At91UsartGetParity,         /* dcb_get_parity */
00113     At91UsartSetStopBits,       /* dcb_set_stop_bits */
00114     At91UsartGetStopBits,       /* dcb_get_stop_bits */
00115     At91UsartSetStatus,         /* dcb_set_status */
00116     At91UsartGetStatus,         /* dcb_get_status */
00117     At91UsartSetClockMode,      /* dcb_set_clock_mode */
00118     At91UsartGetClockMode,      /* dcb_get_clock_mode */
00119 };
00120 
00136 NUTDEVICE devUsartAt911 = {
00137     0,                          /* Pointer to next device, dev_next. */
00138     {'u', 'a', 'r', 't', '1', 0, 0, 0, 0},    /* Unique device name, dev_name. */
00139     IFTYP_CHAR,                 /* Type of device, dev_type. */
00140     1,                          /* Base address, dev_base (not used). */
00141     0,                          /* First interrupt number, dev_irq (not used). */
00142     0,                          /* Interface control block, dev_icb (not used). */
00143     &dcb_usart1,                /* Driver control block, dev_dcb. */
00144     UsartInit,                  /* Driver initialization routine, dev_init. */
00145     UsartIOCtl,                 /* Driver specific control function, dev_ioctl. */
00146     UsartRead,                  /* Read from device, dev_read. */
00147     UsartWrite,                 /* Write to device, dev_write. */
00148     UsartOpen,                  /* Open a device or file, dev_open. */
00149     UsartClose,                 /* Close a device or file, dev_close. */
00150     UsartSize                   /* Request file size, dev_size. */
00151 };
00152 
00156 
00157 /* Modem control includes hardware handshake. */
00158 #if defined(UART1_MODEM_CONTROL)
00159 #define UART_MODEM_CONTROL
00160 #define UART_HARDWARE_HANDSHAKE
00161 #elif defined(UART1_HARDWARE_HANDSHAKE)
00162 #define UART_HARDWARE_HANDSHAKE
00163 #endif
00164 
00165 /*
00166 ** SAM9260 and SAM9XE pins.
00167 */
00168 #if defined(MCU_AT91SAM9260) || defined(MCU_AT91SAM9XE)
00169 
00170 #define UART_RXTX_PINS  (_BV(PB7_RXD1_A) | _BV(PB6_TXD1_A))
00171 #define UART_HDX_PIN    _BV(PB28_RTS1_A)
00172 #define UART_RTS_PIN    _BV(PB28_RTS1_A)
00173 #define UART_CTS_PIN    _BV(PB29_CTS1_A)
00174 
00175 #define UART_RXTX_PINS_ENABLE()     outr(PIOB_ASR, UART_RXTX_PINS); \
00176                                     outr(PIOB_PDR, UART_RXTX_PINS)
00177 
00178 #if defined(UART_HARDWARE_HANDSHAKE)
00179 #define UART_HDX_PIN_ENABLE()       outr(PIOB_ASR, UART_HDX_PIN); \
00180                                     outr(PIOB_PDR, UART_HDX_PIN)
00181 #define UART_RTS_PIN_ENABLE()       outr(PIOB_ASR, UART_RTS_PIN); \
00182                                     outr(PIOB_PDR, UART_RTS_PIN)
00183 #define UART_CTS_PIN_ENABLE()       outr(PIOB_ASR, UART_CTS_PIN); \
00184                                     outr(PIOB_PDR, UART_CTS_PIN)
00185 #endif
00186 
00187 /*
00188 ** SAM7S and SAM7SE pins.
00189 */
00190 #elif defined(MCU_AT91SAM7S) || defined(MCU_AT91SAM7SE)
00191 
00192 #define UART_RXTX_PINS  (_BV(PA21_RXD1_A) | _BV(PA22_TXD1_A))
00193 #define UART_HDX_PIN    _BV(PA24_RTS1_A)
00194 #define UART_RTS_PIN    _BV(PA24_RTS1_A)
00195 #define UART_CTS_PIN    _BV(PA25_CTS1_A)
00196 #define UART_MODEM_PINS (_BV(PB27_DTR1_A) | _BV(PB28_DSR1_A) | _BV(PB26_DCD1_A) | _BV(PB29_RI1_A))
00197 
00198 #define UART_RXTX_PINS_ENABLE()     outr(PIOA_ASR, UART_RXTX_PINS); \
00199                                     outr(PIOA_PDR, UART_RXTX_PINS)
00200 
00201 #if defined(UART_HARDWARE_HANDSHAKE)
00202 #define UART_HDX_PIN_ENABLE()       outr(PIOA_ASR, UART_HDX_PIN); \
00203                                     outr(PIOA_PDR, UART_HDX_PIN)
00204 #define UART_RTS_PIN_ENABLE()       outr(PIOA_ASR, UART_RTS_PIN); \
00205                                     outr(PIOA_PDR, UART_RTS_PIN)
00206 #define UART_CTS_PIN_ENABLE()       outr(PIOA_ASR, UART_CTS_PIN); \
00207                                     outr(PIOA_PDR, UART_CTS_PIN)
00208 #endif
00209 
00210 #if defined(UART_MODEM_CONTROL)
00211 #define UART_MODEM_PINS_ENABLE()    outr(PIOB_ASR, UART_MODEM_PINS); \
00212                                     outr(PIOB_PDR, UART_MODEM_PINS)
00213 #endif
00214 
00215 /*
00216 ** SAM7X pins.
00217 */
00218 #elif defined(MCU_AT91SAM7X)
00219 #define UART_RXTX_PINS  (_BV(PA5_RXD1_A) | _BV(PA6_TXD1_A))
00220 #define UART_HDX_PIN    _BV(PA8_RTS1_A)
00221 #define UART_RTS_PIN    _BV(PA8_RTS1_A)
00222 #define UART_CTS_PIN    _BV(PA9_CTS1_A)
00223 #define UART_MODEM_PINS (_BV(PB25_DTR1_B) | _BV(PB24_DSR1_B) | _BV(PB23_DCD1_B) | _BV(PB26_RI1_B))
00224 
00225 #define UART_RXTX_PINS_ENABLE()     outr(PIOA_ASR, UART_RXTX_PINS); \
00226                                     outr(PIOA_PDR, UART_RXTX_PINS)
00227 
00228 #if defined(UART_HARDWARE_HANDSHAKE)
00229 #define UART_HDX_PIN_ENABLE()       outr(PIOA_ASR, UART_HDX_PIN); \
00230                                     outr(PIOA_PDR, UART_HDX_PIN)
00231 #define UART_RTS_PIN_ENABLE()       outr(PIOA_ASR, UART_RTS_PIN); \
00232                                     outr(PIOA_PDR, UART_RTS_PIN)
00233 #define UART_CTS_PIN_ENABLE()       outr(PIOA_ASR, UART_CTS_PIN); \
00234                                     outr(PIOA_PDR, UART_CTS_PIN)
00235 #endif
00236 
00237 #if defined(UART_MODEM_CONTROL)
00238 #define UART_MODEM_PINS_ENABLE()    outr(PIOB_BSR, UART_MODEM_PINS); \
00239                                     outr(PIOB_PDR, UART_MODEM_PINS)
00240 #endif
00241 
00242 /*
00243 ** X40 pins.
00244 */
00245 #elif defined(MCU_AT91R40008)
00246 
00247 #define UART_RXTX_PINS  (_BV(P22_RXD1) | _BV(P21_TXD1))
00248 
00249 #define UART_RXTX_PINS_ENABLE() outr(PIO_PDR, UART_RXTX_PINS)
00250 
00251 /*
00252 ** Add more targets here. 
00253 **
00254 ** For unsupported targets you may also do basic initializations in 
00255 ** your application code.
00256 */
00257 
00258 #endif
00259 
00260 /*
00261 ** CPLD logic, currently used on Ethernut 3 only.
00262 */
00263 #if defined(ETHERNUT3)
00264 #define UART_USES_NPL   1
00265 #endif
00266 
00267 /*
00268 ** Translate all macros for UART1 to generalized ones used by the
00269 ** source that will be included at the end of this file.
00270 */
00271 #if defined(UART1_HDX_BIT)
00272 #define UART_HDX_BIT    UART1_HDX_BIT
00273 #endif
00274 #if defined(UART1_HDX_PIO_ID)
00275 #define UART_HDX_PIO_ID UART1_HDX_PIO_ID
00276 #endif
00277 
00278 #if defined(UART1_RTS_BIT)
00279 #define UART_RTS_BIT    UART1_RTS_BIT
00280 #endif
00281 #if defined(UART1_RTS_PIO_ID)
00282 #define UART_RTS_PIO_ID UART1_RTS_PIO_ID
00283 #endif
00284 
00285 #if defined(UART1_CTS_BIT)
00286 #define UART_CTS_BIT    UART1_CTS_BIT
00287 #endif
00288 #if defined(UART1_CTS_PIO_ID)
00289 #define UART_CTS_PIO_ID UART1_CTS_PIO_ID
00290 #endif
00291 #if defined(UART0_CTS_SIGNAL)
00292 #define UART_CTS_SIGNAL UART0_CTS_SIGNAL
00293 #endif
00294 
00295 #if defined(UART1_INIT_BAUDRATE)
00296 #define UART_INIT_BAUDRATE  UART1_INIT_BAUDRATE
00297 #endif
00298 
00299 #define USARTn_BASE     USART1_BASE
00300 #define US_ID           US1_ID
00301 #define SIG_UART        sig_UART1
00302 #define dcb_usart       dcb_usart1
00303 
00304 #include "usartat91.c"

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