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ADC Control Register |
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#define | ADC_CR_OFF 0x00000000 |
| Control register offset.
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#define | ADC_CR (ADC_BASE + ADC_CR_OFF) |
| Control register address.
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#define | ADC_SWRST 0x00000001 |
| Software reset.
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ADC Mode Register |
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#define | ADC_START 0x00000002 |
| Start a conversion.
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#define | ADC_START 0x00000002 |
| Start a conversion.
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#define | ADC_MR_OFF 0x00000004 |
| Mode register offset.
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#define | ADC_MR (ADC_BASE + ADC_MR_OFF) |
| Mode register address.
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#define | ADC_TRGEN 0x00000001 |
| Software reset.
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#define | ADC_TRGSEL 0x0000000E |
| Trigger select mask.
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#define | ADC_TRGSEL_TIOA0 0x00000000 |
| Trigger select timer counter 0 output.
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#define | ADC_TRGSEL_TIOA1 0x00000002 |
| Trigger select timer counter 1 output.
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#define | ADC_TRGSEL_TIOA2 0x00000004 |
| Trigger select timer counter 2 output.
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#define | ADC_TRGSEL_EXT 0x0000000C |
| Single trigger.
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#define | ADC_LOWRES 0x00000010 |
| 10bit / 8bit selection
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#define | ADC_SLEEP 0x00000020 |
| Enter sleep mode.
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#define | ADC_PRESCAL 0x00003F00 |
| Prescaler mask.
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#define | ADC_PRESCAL_LSB 8 |
| Prescaler LSB.
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#define | ADC_STARTUP 0x001F0000 |
| Startup time mask.
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#define | ADC_STARTUP_LSB 16 |
| Startup time LSB.
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#define | ADC_SHTIM 0x0F000000 |
| Sample hold time mask.
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#define | ADC_SHTIM_LSB 24 |
| Sample hold time LSB.
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ADC Channel Enable Register |
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#define | ADC_CHER_OFF 0x00000010 |
| Channel enable register offset.
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#define | ADC_CHER (ADC_BASE + ADC_CHER_OFF) |
| Channel enable register address.
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#define | ADC_CH(x) ((unsigned long)BV(x)) |
| macro to access channel by numer
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#define | ADC_CH0 0x00000001 |
| ADC Channel 0.
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#define | ADC_CH1 0x00000002 |
| ADC Channel 1.
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#define | ADC_CH2 0x00000004 |
| ADC Channel 2.
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#define | ADC_CH3 0x00000008 |
| ADC Channel 3.
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#define | ADC_CH4 0x00000010 |
| ADC Channel 4.
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#define | ADC_CH5 0x00000020 |
| ADC Channel 5.
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#define | ADC_CH6 0x00000040 |
| ADC Channel 6.
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#define | ADC_CH7 0x00000080 |
| ADC Channel 7.
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ADC Channel Disable Register |
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#define | ADC_CHDR_OFF 0x00000014 |
| Channel disable register offset.
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#define | ADC_CHDR (ADC_BASE + ADC_CHDR_OFF) |
| Channel disable register address.
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ADC Channel Status Register |
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#define | ADC_CHSR_OFF 0x00000018 |
| Channel status register offset.
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#define | ADC_CHSR (ADC_BASE + ADC_CHSR_OFF) |
| Channel status register address.
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ADC Status Register |
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#define | ADC_SR_OFF 0x0000001C |
| ADC status register offset.
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#define | ADC_SR (ADC_BASE + ADC_SR_OFF) |
| ADC status register address.
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#define | ADC_EOC(x) ((unsigned long)BV(x)) |
| Macro to access EOC flag by channel number.
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#define | ADC_EOC0 0x00000001 |
| End of conversion channel 0.
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#define | ADC_EOC1 0x00000002 |
| End of conversion channel 1.
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#define | ADC_EOC2 0x00000004 |
| End of conversion channel 2.
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#define | ADC_EOC3 0x00000008 |
| End of conversion channel 3.
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#define | ADC_EOC4 0x00000010 |
| End of conversion channel 4.
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#define | ADC_EOC5 0x00000020 |
| End of conversion channel 5.
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#define | ADC_EOC6 0x00000040 |
| End of conversion channel 6.
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#define | ADC_EOC7 0x00000080 |
| End of conversion channel 7.
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#define | ADC_OVRE(x) ((unsigned long)BV(x+8)) |
| Macto to acces overrun error flag by channel number.
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#define | ADC_OVRE0 0x00000100 |
| Overrun error flag channel 0.
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#define | ADC_OVRE1 0x00000200 |
| Overrun error flag channel 1.
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#define | ADC_OVRE2 0x00000400 |
| Overrun error flag channel 2.
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#define | ADC_OVRE3 0x00000800 |
| Overrun error flag channel 3.
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#define | ADC_OVRE4 0x00001000 |
| Overrun error flag channel 4.
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#define | ADC_OVRE5 0x00002000 |
| Overrun error flag channel 5.
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#define | ADC_OVRE6 0x00004000 |
| Overrun error flag channel 6.
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#define | ADC_OVRE7 0x00008000 |
| Overrun error flag channel 7.
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#define | ADC_DRDY 0x00010000 |
| Data ready flag.
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#define | ADC_GOVRE 0x00020000 |
| General data overrun error flag.
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#define | ADC_ENDRX 0x00040000 |
| End of rx buffer flag.
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#define | ADC_RXBUF 0x00080000 |
| Rx buffer full flag.
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ADC Last Converted Data Register |
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#define | ADC_LCDR_OFF 0x00000020 |
| Last converted data register offset.
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#define | ADC_LCDR (ADC_BASE + ADC_LCDR_OFF) |
| Last converted data register.
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#define | ADC_LCDR_MASK 0x000003FF |
| Last converted data mask (10bit).
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ADC Interrupt Enable Register |
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#define | ADC_IER_OFF 0x00000024 |
| Interrupt enable register offset.
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#define | ADC_IER (ADC_BASE + ADC_IER_OFF) |
| Last converted data register.
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ADC Interrupt Disable Register |
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#define | ADC_IDR_OFF 0x00000028 |
| Interrupt disable register offset.
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#define | ADC_IDR (ADC_BASE + ADC_IDR_OFF) |
| Interrupt disable register.
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ADC Interrupt Mask Register |
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#define | ADC_IMR_OFF 0x0000002C |
| Interrupt mask register offset.
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#define | ADC_IMR (ADC_BASE + ADC_IMR_OFF) |
| Interrupt mask register.
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ADC Channel Data Register |
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#define | ADC_CDR_OFF 0x00000030 |
| Channel data register offset.
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#define | ADC_CDR(x) (ADC_BASE + ADC_CDR_OFF + ((x) << 2)) |
| Channel data register.
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#define | ADC_CDR_MASK 0x000003FF |
| Channel data mask (10bit).
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