|
#define | CR 0x00 |
| Asix Ax88796L register definitions.
|
#define | DATAPORT 0x10 |
| Data Port.
|
#define | IFGS1 0x12 |
| Inter-frame Gap Segment 1.
|
#define | IFGS2 0x13 |
| Inter-frame Gap Segment 2.
|
#define | MII_EEP 0x14 |
| MII/EEPROM Access.
|
#define | TR 0x15 |
| Test Register.
|
#define | IFG 0x16 |
| Inter-frame Gap.
|
#define | GPI 0x17 |
| GPI.
|
#define | GPOC 0x17 |
| GPOC.
|
#define | SPP1 0x18 |
| Standard Printer Port 1.
|
#define | SPP2 0x19 |
| Standard Printer Port 2.
|
#define | SPP3 0x1a |
| Standard Printer Port 3.
|
#define | RESET 0x1f |
| Reset port.
|
#define | PG0_PSTART 0x01 |
| Page start register.
|
#define | PG0_PSTOP 0x02 |
| Page stop register.
|
#define | PG0_BNRY 0x03 |
| Boundary pointer.
|
#define | PG0_TSR 0x04 |
| Transmit status register.
|
#define | PG0_TPSR 0x04 |
| Transmit page start address.
|
#define | PG0_NCR 0x05 |
| Number of collisions register.
|
#define | PG0_TBCR0 0x05 |
| Transmit byte count register 0.
|
#define | PG0_CPR 0x06 |
| Current Page Register.
|
#define | PG0_TBCR1 0x06 |
| Transmit Byte Count Register 1.
|
#define | PG0_ISR 0x07 |
| Interrupt status register.
|
#define | PG0_CRDA0 0x08 |
| Current remote DMA address 0.
|
#define | PG0_RSAR0 0x08 |
| Remote start address register 0 Low byte address to read from the buffer.
|
#define | PG0_CRDA1 0x09 |
| Current remote DMA address 1.
|
#define | PG0_RSAR1 0x09 |
| Remote start address register 1 High byte address to read from the buffer.
|
#define | PG0_RBCR0 0x0a |
| Remote byte count register 0 Low byte of the number of bytes to read from the buffer.
|
#define | PG0_RBCR1 0x0b |
| Remote byte count register 1 High byte of the number of bytes to read from the buffer.
|
#define | PG0_RSR 0x0c |
| Receive status register.
|
#define | PG0_RCR 0x0c |
| Receive configuration register.
|
#define | PG0_CNTR0 0x0d |
| Tally counter 0 (frame alignment errors).
|
#define | PG0_TCR 0x0d |
| Transmit configuration register.
|
#define | PG0_DCR 0x0e |
| Data configuration register.
|
#define | PG0_IMR 0x0f |
| Interrupt mask register.
|
#define | PG1_PAR0 0x01 |
| Physical Address Register 0.
|
#define | PG1_PAR1 0x02 |
| Physical Address Register 1.
|
#define | PG1_PAR2 0x03 |
| Physical Address Register 2.
|
#define | PG1_PAR3 0x04 |
| Physical Address Register 3.
|
#define | PG1_PAR4 0x05 |
| Physical Address Register 4.
|
#define | PG1_PAR5 0x06 |
| Physical Address Register 5.
|
#define | PG1_CPR 0x07 |
| Current Page Register.
|
#define | PG1_MAR0 0x08 |
| Multicast Address Register 0.
|
#define | PG1_MAR1 0x09 |
| Multicast Address Register 1.
|
#define | PG1_MAR2 0x0a |
| Multicast Address Register 2.
|
#define | PG1_MAR3 0x0b |
| Multicast Address Register 3.
|
#define | PG1_MAR4 0x0c |
| Multicast Address Register 4.
|
#define | PG1_MAR5 0x0d |
| Multicast Address Register 5.
|
#define | PG1_MAR6 0x0e |
| Multicast Address Register 6.
|
#define | PG1_MAR7 0x0f |
| Multicast Address Register 7.
|
#define | CR_STOP 0x01 |
| Stop.
|
#define | CR_START 0x02 |
| Start.
|
#define | CR_TXP 0x04 |
| Transmit packet.
|
#define | CR_RD0 0x08 |
| Remote DMA command bit 0.
|
#define | CR_RD1 0x10 |
| Remote DMA command bit 1.
|
#define | CR_RD2 0x20 |
| Remote DMA command bit 2.
|
#define | CR_PS0 0x40 |
| Page select bit 0.
|
#define | CR_PS1 0x80 |
| Page select bit 1.
|
#define | ISR_PRX 0x01 |
| Packet received.
|
#define | ISR_PTX 0x02 |
| Packet transmitted.
|
#define | ISR_RXE 0x04 |
| Receive error.
|
#define | ISR_TXE 0x08 |
| Transmit error.
|
#define | ISR_OVW 0x10 |
| Overwrite warning.
|
#define | ISR_CNT 0x20 |
| Counter overflow.
|
#define | ISR_RDC 0x40 |
| Remote DMA complete.
|
#define | ISR_RST 0x80 |
| Reset status.
|
#define | IMR_PRXE 0x01 |
| Packet received interrupt enable.
|
#define | IMR_PTXE 0x02 |
| Packet transmitted interrupt enable.
|
#define | IMR_RXEE 0x04 |
| Receive error interrupt enable.
|
#define | IMR_TXEE 0x08 |
| Transmit error interrupt enable.
|
#define | IMR_OVWE 0x10 |
| Overwrite warning interrupt enable.
|
#define | IMR_CNTE 0x20 |
| Counter overflow interrupt enable.
|
#define | IMR_RCDE 0x40 |
| Remote DMA complete interrupt enable.
|
#define | DCR_WTS 0x01 |
| Word transfer select.
|
#define | DCR_RDCR 0x80 |
| Remote DMA always completed.
|
#define | TCR_CRC 0x01 |
| Inhibit CRC.
|
#define | TCR_LB0 0x02 |
| Encoded loopback control bit 0.
|
#define | TCR_LB1 0x04 |
| Encoded loopback control bit 1.
|
#define | TCR_RLO 0x20 |
| Full Duplex.
|
#define | TCR_PD 0x40 |
| Pad Disable.
|
#define | TCR_FDU 0x80 |
| Retry of late collision.
|
#define | TSR_PTX 0x01 |
| Packet transmitted.
|
#define | TSR_COL 0x04 |
| Transmit collided.
|
#define | TSR_ABT 0x08 |
| Transmit aborted.
|
#define | TSR_OWC 0x80 |
| Out of window collision.
|
#define | RCR_SEP 0x01 |
| Save errored packets.
|
#define | RCR_AR 0x02 |
| Accept runt packets.
|
#define | RCR_AB 0x04 |
| Accept broadcast.
|
#define | RCR_AM 0x08 |
| Accept multicast.
|
#define | RCR_PRO 0x10 |
| Promiscuous physical.
|
#define | RCR_MON 0x20 |
| Monitor mode.
|
#define | RCR_INTT 0x40 |
| Interrupt Trigger Mode.
|
#define | RSR_PRX 0x01 |
| Packet received intact.
|
#define | RSR_CR 0x02 |
| CRC error.
|
#define | RSR_FAE 0x04 |
| Frame alignment error.
|
#define | RSR_FO 0x08 |
| FIFO overrun.
|
#define | RSR_MPA 0x10 |
| Missed packet.
|
#define | RSR_PHY 0x20 |
| Physical/multicast address.
|
#define | RSR_DIS 0x40 |
| Receiver disabled.
|
#define | MII_EEP_MDC 0x01 |
| MII clock.
|
#define | MII_EEP_MDIR 0x02 |
| MII MDIO directions.
|
#define | MII_EEP_MDI 0x04 |
| MII data In.
|
#define | MII_EEP_MDO 0x08 |
| MII data Out.
|
#define | MII_EEP_EECS 0x10 |
| EEPROM Chip select.
|
#define | MII_EEP_EEI 0x20 |
| EEPROM data in.
|
#define | MII_EEP_EEO 0x40 |
| EEPROM data out.
|
#define | MII_EEP_EECLK 0x80 |
| EEPROM clock.
|
#define | TR_RST_B 0x02 |
| Reset busy.
|
#define | PHY_MR0 0x00 |
| Control.
|
#define | PHY_MR1 0x01 |
| Status.
|
#define | PHY_MR2 0x02 |
| PHY Identifier 1.
|
#define | PHY_MR3 0x03 |
| PHY Identifier 2.
|
#define | PHY_MR4 0x04 |
| Autonegotiation Advertisement.
|
#define | PHY_MR5 0x05 |
| Autonegotiation Link Partner Ability.
|
#define | PHY_MR6 0x06 |
| Autonegotiation Expansion.
|
#define | PHY_MR7 0x07 |
| Next Page Transmit.
|
#define | PHY_MR16 0x10 |
| PCS Control Register.
|
#define | PHY_MR17 0x11 |
| Autonegotiation (read register A).
|
#define | PHY_MR18 0x12 |
| Autonegotiation (read register B).
|
#define | PHY_MR19 0x13 |
| Analog Test Register.
|
#define | PHY_MR20 0x14 |
| User-defined Register.
|
#define | PHY_MR21 0x15 |
| RXER Counter.
|
#define | PHY_MR22 0x16 |
| Analog Test Registers.
|
#define | PHY_MR23 0x17 |
| Analog Test Registers.
|
#define | PHY_MR24 0x18 |
| Analog Test Registers.
|
#define | PHY_MR25 0x19 |
| Analog Test (tuner) Registers.
|
#define | PHY_MR26 0x1a |
| Analog Test (tuner) Registers.
|
#define | PHY_MR27 0x1b |
| Analog Test (tuner) Registers.
|
#define | PHY_MR28 0x1c |
| Device Specific 1.
|
#define | PHY_MR29 0x1d |
| Device Specific 2.
|
#define | PHY_MR30 0x1e |
| Device Specific 3.
|
#define | PHY_MR31 0x1f |
| Quick Status Register.
|
#define | MR0_SW_RESET 0x8000 |
#define | MR0_LOOPBACK 0x4000 |
#define | MR0_SPEED100 0x2000 |
#define | MR0_NWAY_ENA 0x1000 |
#define | MR0_PWRDN 0x0800 |
#define | MR0_ISOLATE 0x0400 |
#define | MR0_REDONWAY 0x0200 |
#define | MR0_FULL_DUP 0x0100 |
#define | MR0_COLTST 0x0080 |
#define | MR1_T4ABLE 0x8000 |
#define | MR1_TXFULDUP 0x4000 |
#define | MR1_TXHAFDUP 0x2000 |
#define | MR1_ENFULDUP 0x1000 |
#define | MR1_ENHAFDUP 0x0800 |
#define | MR1_NO_PA_OK 0x0040 |
#define | MR1_NWAYDONE 0x0020 |
#define | MR1_REM_FLT 0x0010 |
#define | MR1_NWAYABLE 0x0008 |
#define | MR1_LSTAT_OK 0x0004 |
#define | MR1_JABBER 0x0002 |
#define | MR1_EXT_ABLE 0x0001 |
#define | MR31_LSTAT_OK 0x0800 |
#define | MR31_SPEED100 0x0200 |
#define | MR31_FULL_DUP 0x0100 |