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= NPL Tutorial - Step 2 = Previous Contents Next == Creating A New ISE Project == Start the Xi..."

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= NPL Tutorial - Step 2 =

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== Creating A New ISE Project ==

Start the Xilinx ISE Project Navigator and ...

[[File:../../img/ise-new-proj00.png|ISE New Project Start]]
select '''New Project...''' from the '''File''' Menu.

[[File:../../img/ise-new-proj01.png|ISE New Project 01]]
The '''New Project Dialog''' appears. Enter the name of your new project, like '''npltut01''' or similar. The top level module type should be set to '''HDL''', because we will use the Verilog HDL in our tutorial.

Before continuing, you need to copy two files into the project directory:

* '''npltut01.v'''<br />
The Verilog Source File
* '''ethernut30d.ucf'''<br />
The User Contraints File for Ethernut 3.0 Rev-D

When done, return to the '''New Project''' Dialog and press the '''Next''' button.

[[File:../../img/ise-new-proj02.png|ISE New Project 02]]
On the second page we select the '''XC9500XL CPLD''' device family and the '''xc95144xl''' device, because this is exactly the chip we use on Ethernut 3. Also check the other entries and modify them if they differ from the screenshot.

Press the '''Next''' button.

[[File:../../img/ise-new-proj03.png|ISE New Project 03]]
We can leave this page alone, because we will use a prepared source file. Simply press the '''Next''' button.

[[File:../../img/ise-new-proj04.png|ISE New Project 04]]
On the next page press the '''Add''' button and...

[[File:../../img/ise-new-proj05.png|ISE New Project 05]]
...select the file '''npltut01.v'''. Then press the '''Open''' button...

[[File:../../img/ise-new-proj06.png|ISE New Project 06]]
...and specify its type as a '''Verilog Design File'''.

[[File:../../img/ise-new-proj07.png|ISE New Project 07]]
The final page will show a summary of the configuration. Verify the specifications and confirm it.

[[File:../../img/ise-new-proj08.png|ISE New Project 08]]
We are now back to the Project Navigator's main window. Select '''Add Source...''' from the '''Project''' Menu to add the pin layout file of the Ethernut 3 CPLD to our new project.

[[File:../../img/ise-new-proj09.png|ISE New Project 09]]
Select '''ethernut30d.ucf''' and press the '''Open''' button.

[[File:../../img/ise-new-proj10.png|ISE New Project 10]]
The file '''ethernut30d.ucf''' is a so called User Contraints File. Among other things it specifies which signals are connected to which pins of the CPLD. The file we just loaded saves you some work, because all CPLD pins used on Ethernut 3 are pre-defined in this file. Select the file '''ethernut30d.ucf''' in the '''Sources in Project''' Tree and double click on '''Edit Constraints (Text)''' to view its contents.

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Documents/NPL New Project - Revision history

Harald: Created page with " = NPL Tutorial - Step 2 = Previous Contents Next == Creating A New ISE Project == Start the Xi..."

Harald: Created page with "
= NPL Tutorial - Step 2 = Previous Contents Next == Creating A New ISE Project == Start the Xi..."