Go to the documentation of this file.00001 #ifndef _LPC177X_8X_MCI_H_
00002 #define _LPC177X_8X_MCI_H_
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00070 #include <cfg/arch.h>
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00078
00079 #define HIGH_LVL (1)
00080 #define LOW_LVL (0)
00081
00082
00083
00084
00085
00086 #define CMD0_GO_IDLE_STATE 0
00087
00088 #define CMD1_SEND_OP_COND 1
00089
00090 #define CMD2_ALL_SEND_CID 2
00091
00092 #define CMD3_SET_RELATIVE_ADDR 3
00093
00094 #define ACMD6_SET_BUS_WIDTH 6
00095
00096 #define CMD7_SELECT_CARD 7
00097
00098 #define CMD8_SEND_IF_COND 8
00099
00100 #define CMD9_SEND_CSD 9
00101
00102 #define CMD12_STOP_TRANSMISSION 12
00103
00104 #define CMD13_SEND_STATUS 13
00105
00106 #define CMD16_SET_BLOCK_LEN 16
00107
00108 #define CMD17_READ_SINGLE_BLOCK 17
00109
00110 #define CMD18_READ_MULTIPLE_BLOCK 18
00111
00112 #define CMD24_WRITE_BLOCK 24
00113
00114 #define CMD25_WRITE_MULTIPLE_BLOCK 25
00115
00116 #define CMD32_ERASE_WR_BLK_START 32
00117
00118 #define CMD33_ERASE_WR_BLK_END 33
00119
00120 #define CMD38_ERASE 38
00121
00122
00123
00124 #define ACMD41_SEND_APP_OP_COND 41
00125
00126
00127 #define CMD55_APP_CMD 55
00128
00129 #define OCR_INDEX 0x00FF8000
00130
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00132
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00135
00136 #define CARD_STATUS_ACMD_ENABLE (1 << 5)
00137 #define CARD_STATUS_RDY_DATA (1 << 8)
00138 #define CARD_STATUS_CURRENT_STATE (0x0F << 9)
00139 #define CARD_STATUS_ERASE_RESET (1 << 13)
00140
00141 #define MCI_SLOW_RATE 1
00142 #define MCI_NORMAL_RATE 2
00143
00144 #define SD_1_BIT 0
00145 #define SD_4_BIT 1
00146
00147 #define CARD_UNKNOWN 0
00148 #define MMC_CARD 1
00149 #define SD_CARD 2
00150
00151
00152
00153 #if MCI_DMA_ENABLED
00154 #define MCLKDIV_SLOW (60 - 1)
00155 #define MCLKDIV_NORMAL (1 - 1)
00156 #else
00157 #define MCLKDIV_SLOW (75 - 1)
00158 #define MCLKDIV_NORMAL (60 - 1)
00159
00160 #endif
00161
00162 #define DATA_TIMER_VALUE 0x10000
00163
00164 #define EXPECT_NO_RESP 0
00165 #define EXPECT_SHORT_RESP 1
00166 #define EXPECT_LONG_RESP 2
00167
00168 #define MCI_OUTPUT_MODE_PUSHPULL (0)
00169 #define MCI_OUTPUT_MODE_OPENDRAIN (1)
00170
00171 #define NOT_ALLOW_CMD_TIMER 0
00172 #define ALLOW_CMD_TIMER 1
00173
00174 #define MCI_DISABLE_CMD_TIMER (1<<8)
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00207 #define MCI_DMA_SIZE (1000UL)
00208
00209
00210 #define MCI_DMA_SRC_ADDR LPC_PERI_RAM_BASE
00211
00212
00213 #define MCI_DMA_DST_ADDR (MCI_DMA_SRC_ADDR + MCI_DMA_SIZE)
00214
00215
00216 #define MMC_BLOCK_MODE 0
00217 #define MMC_BYTE_MODE 1
00218
00219
00220 #define DATA_BLOCK_LEN 9
00221 #define BLOCK_LENGTH (1 << DATA_BLOCK_LEN)
00222
00223
00224 #define BLOCK_NUM 0x80
00225 #define FIFO_SIZE 16
00226
00227 #define BUS_WIDTH_1BIT 0
00228 #define BUS_WIDTH_4BITS 10
00229
00230
00231 #define MCI_CMD_CRC_FAIL (1 << 0)
00232 #define MCI_DATA_CRC_FAIL (1 << 1)
00233 #define MCI_CMD_TIMEOUT (1 << 2)
00234 #define MCI_DATA_TIMEOUT (1 << 3)
00235 #define MCI_TX_UNDERRUN (1 << 4)
00236 #define MCI_RX_OVERRUN (1 << 5)
00237 #define MCI_CMD_RESP_END (1 << 6)
00238 #define MCI_CMD_SENT (1 << 7)
00239 #define MCI_DATA_END (1 << 8)
00240 #define MCI_START_BIT_ERR (1 << 9)
00241 #define MCI_DATA_BLK_END (1 << 10)
00242 #define MCI_CMD_ACTIVE (1 << 11)
00243 #define MCI_TX_ACTIVE (1 << 12)
00244 #define MCI_RX_ACTIVE (1 << 13)
00245 #define MCI_TX_HALF_EMPTY (1 << 14)
00246 #define MCI_RX_HALF_FULL (1 << 15)
00247 #define MCI_TX_FIFO_FULL (1 << 16)
00248 #define MCI_RX_FIFO_FULL (1 << 17)
00249 #define MCI_TX_FIFO_EMPTY (1 << 18)
00250 #define MCI_RX_FIFO_EMPTY (1 << 19)
00251 #define MCI_TX_DATA_AVAIL (1 << 20)
00252 #define MCI_RX_DATA_AVAIL (1 << 21)
00253
00254
00255
00256
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00258
00259
00260 #define MCI_DATACTRL_ENABLE_POS (0)
00261 #define MCI_DATACTRL_ENABLE_MASK (0x01)
00262 #define MCI_DATACTRL_ENABLE (1 << MCI_DATACTRL_ENABLE_POS)
00263 #define MCI_DATACTRL_DISABLE (0 << MCI_DATACTRL_ENABLE_POS)
00264
00265
00266 #define MCI_DATACTRL_DIR_POS (1)
00267 #define MCI_DATACTRL_DIR_MASK (0x01)
00268 #define MCI_DATACTRL_DIR_FROM_CARD (1 << MCI_DATACTRL_DIR_POS)
00269 #define MCI_DATACTRL_DIR_TO_CARD (0 << MCI_DATACTRL_DIR_POS)
00270
00271
00272
00273 #define MCI_DATACTRL_XFER_MODE_POS (2)
00274 #define MCI_DATACTRL_XFER_MODE_MASK (0x01)
00275 #define MCI_DATACTRL_XFER_MODE_STREAM (1 << MCI_DATACTRL_XFER_MODE_POS)
00276 #define MCI_DATACTRL_XFER_MODE_BLOCK (0 << MCI_DATACTRL_XFER_MODE_POS)
00277
00278
00279 #define MCI_DATACTRL_DMA_ENABLE_POS (3)
00280 #define MCI_DATACTRL_DMA_ENABLE_MASK (0x01)
00281 #define MCI_DATACTRL_DMA_ENABLE (1 << MCI_DATACTRL_DMA_ENABLE_POS)
00282 #define MCI_DATACTRL_DMA_DISABLE (0 << MCI_DATACTRL_DMA_ENABLE_POS)
00283
00285 #define MCI_DTATCTRL_BLOCKSIZE(n) _SBF(4, (n & 0xF))
00286
00287
00288 #define CMD_INT_MASK (MCI_CMD_CRC_FAIL | MCI_CMD_TIMEOUT | MCI_CMD_RESP_END | \
00289 MCI_CMD_SENT | MCI_CMD_ACTIVE)
00290
00291 #define DATA_ERR_INT_MASK (MCI_DATA_CRC_FAIL | MCI_DATA_TIMEOUT | MCI_TX_UNDERRUN | \
00292 MCI_RX_OVERRUN | MCI_START_BIT_ERR)
00293
00294 #define ACTIVE_INT_MASK (MCI_TX_ACTIVE | MCI_RX_ACTIVE)
00295
00296 #define FIFO_INT_MASK (MCI_TX_HALF_EMPTY | MCI_RX_HALF_FULL | \
00297 MCI_TX_FIFO_FULL | MCI_RX_FIFO_FULL | \
00298 MCI_TX_FIFO_EMPTY | MCI_RX_FIFO_EMPTY | \
00299 MCI_DATA_BLK_END )
00300
00301 #define FIFO_TX_INT_MASK (MCI_TX_HALF_EMPTY)
00302 #define FIFO_RX_INT_MASK (MCI_RX_HALF_FULL )
00303
00304 #define DATA_END_INT_MASK (MCI_DATA_END | MCI_DATA_BLK_END)
00305
00306 #define ERR_TX_INT_MASK (MCI_DATA_CRC_FAIL | MCI_DATA_TIMEOUT | MCI_TX_UNDERRUN | MCI_START_BIT_ERR)
00307 #define ERR_RX_INT_MASK (MCI_DATA_CRC_FAIL | MCI_DATA_TIMEOUT | MCI_RX_OVERRUN | MCI_START_BIT_ERR)
00308
00309
00310 #define INVALID_RESPONSE 0xFFFFFFFF
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00318 typedef enum mci_card_state
00319 {
00320 MCI_CARDSTATE_IDLE = 0,
00321 MCI_CARDSTATE_READY,
00322 MCI_CARDSTATE_IDENDTIFIED,
00323 MCI_CARDSTATE_STBY,
00324 MCI_CARDSTATE_TRAN,
00325 MCI_CARDSTATE_DATA,
00326 MCI_CARDSTATE_RCV,
00327 MCI_CARDSTATE_PRG,
00328 MCI_CARDSTATE_DIS,
00329 } en_Mci_CardState;
00330
00331
00332 typedef enum mci_func_error
00333 {
00334 MCI_FUNC_OK = 0,
00335 MCI_FUNC_FAILED = -1,
00336 MCI_FUNC_BAD_PARAMETERS = -2,
00337 MCI_FUNC_BUS_NOT_IDLE = -3,
00338 MCI_FUNC_TIMEOUT = -3,
00339 MCI_FUNC_ERR_STATE = -4,
00340 MCI_FUNC_NOT_READY = -5,
00341 } en_Mci_Func_Error;
00342
00343 typedef enum mci_card_type
00344 {
00345 MCI_SDHC_SDXC_CARD = 3,
00346 MCI_SDSC_V2_CARD = 2,
00347 MCI_MMC_CARD = 1,
00348 MCI_SDSC_V1_CARD = 0,
00349 MCI_CARD_UNKNOWN = -1,
00350 } en_Mci_CardType;
00351
00355 typedef struct mci_cid
00356 {
00357
00358 uint8_t MID;
00359
00360 uint16_t OID;
00361
00362 uint8_t PNM_H;
00363
00364 uint32_t PNM_L;
00365
00366 uint8_t PRV;
00367
00368 uint32_t PSN;
00369
00370 uint8_t reserved;
00371
00372 uint16_t MDT;
00373
00374 uint8_t CRC;
00375
00376 uint8_t unused;
00377 } st_Mci_CardId;
00378
00379
00380
00381
00386 int32_t Lpc177x_8x_MciInit(uint8_t powerActiveLevel);
00387 void Lpc177x_8x_MciSendCmd(uint32_t CmdIndex, uint32_t Argument, uint32_t ExpectResp, uint32_t AllowTimeout);
00388 int32_t Lpc177x_8x_MciGetCmdResp(uint32_t CmdIndex, uint32_t NeedRespFlag, uint32_t *CmdRespStatus);
00389 int32_t Lpc177x_8x_MciCmdResp(uint32_t CmdIndex, uint32_t Argument, uint32_t ExpectResp, uint32_t *CmdResp, uint32_t AllowTimeout);
00390
00391 void Lpc177x_8x_MciSet_MCIClock(uint32_t clockrate);
00392 int32_t Lpc177x_8x_MciSetBusWidth(uint32_t width);
00393 int32_t Lpc177x_8x_MciAcmd_SendOpCond(uint8_t hcsVal);
00394 int32_t Lpc177x_8x_MciCardInit(void);
00395 en_Mci_CardType Lpc177x_8x_MciGetCardType(void);
00396 int32_t Lpc177x_8x_MciCardReset(void);
00397 int32_t Lpc177x_8x_MciCmd_SendIfCond(void);
00398 int32_t Lpc177x_8x_MciGetCID(st_Mci_CardId* cidValue);
00399 int32_t Lpc177x_8x_MciSetCardAddress(void);
00400 uint32_t Lpc177x_8x_MciGetCardAddress(void);
00401 int32_t Lpc177x_8x_MciGetCSD(uint32_t* csdVal);
00402 int32_t Lpc177x_8x_MciCmd_SelectCard(void);
00403 int32_t Lpc177x_8x_MciGetCardStatus(int32_t* cardStatus);
00404 uint32_t Lpc177x_8x_MciGetDataXferEndState(void);
00405 uint32_t Lpc177x_8x_MciGetXferErrState(void);
00406 int32_t Lpc177x_8x_MciSetBlockLen(uint32_t blockLength);
00407 int32_t Lpc177x_8x_MciAcmd_SendBusWidth(uint32_t buswidth);
00408 int32_t Lpc177x_8x_MciCmd_StopTransmission(void);
00409
00410 int32_t Lpc177x_8x_MciCmd_WriteBlock(uint32_t blockNum, uint32_t numOfBlock);
00411 int32_t Lpc177x_8x_MciCmd_ReadBlock(uint32_t blockNum, uint32_t numOfBlock);
00412
00413 int32_t Lpc177x_8x_MciWriteBlock(uint8_t* memblock, uint32_t blockNum, uint32_t numOfBlock);
00414 int32_t Lpc177x_8x_MciReadBlock(uint8_t* destBlock, uint32_t blockNum, uint32_t numOfBlock);
00415
00416 #if MCI_DMA_ENABLED
00417 void Lpc177x_8x_MciDMA_IRQHandler (void);
00418 #endif
00419
00420 #endif