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Nut/OS
5.0.5
API Reference
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Nut/OS
5.0.5
API Reference
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00001 /**************************************************************************/ 00026 #ifndef __LPC17xx_H__ 00027 #define __LPC17xx_H__ 00028 00029 /* 00030 * ========================================================================== 00031 * ---------- Interrupt Number Definition ----------------------------------- 00032 * ========================================================================== 00033 */ 00034 00035 typedef enum IRQn 00036 { 00037 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ 00038 NonMaskableInt_IRQn = -14, 00039 HardFault_IRQn = -13, 00040 MemoryManagement_IRQn = -12, 00041 BusFault_IRQn = -11, 00042 UsageFault_IRQn = -10, 00043 SVCall_IRQn = -5, 00044 DebugMonitor_IRQn = -4, 00045 PendSV_IRQn = -2, 00046 SysTick_IRQn = -1, 00048 /****** LPC17xx Specific Interrupt Numbers *******************************************************/ 00049 WDT_IRQn = 0, 00050 TIMER0_IRQn = 1, 00051 TIMER1_IRQn = 2, 00052 TIMER2_IRQn = 3, 00053 TIMER3_IRQn = 4, 00054 UART0_IRQn = 5, 00055 UART1_IRQn = 6, 00056 UART2_IRQn = 7, 00057 UART3_IRQn = 8, 00058 PWM1_IRQn = 9, 00059 I2C0_IRQn = 10, 00060 I2C1_IRQn = 11, 00061 I2C2_IRQn = 12, 00062 SPI_IRQn = 13, 00063 SSP0_IRQn = 14, 00064 SSP1_IRQn = 15, 00065 PLL0_IRQn = 16, 00066 RTC_IRQn = 17, 00067 EINT0_IRQn = 18, 00068 EINT1_IRQn = 19, 00069 EINT2_IRQn = 20, 00070 EINT3_IRQn = 21, 00071 ADC_IRQn = 22, 00072 BOD_IRQn = 23, 00073 USB_IRQn = 24, 00074 CAN_IRQn = 25, 00075 DMA_IRQn = 26, 00076 I2S_IRQn = 27, 00077 ENET_IRQn = 28, 00078 RIT_IRQn = 29, 00079 MCPWM_IRQn = 30, 00080 QEI_IRQn = 31, 00081 PLL1_IRQn = 32, 00082 } IRQn_Type; 00083 00084 00085 /* 00086 * ========================================================================== 00087 * ----------- Processor and Core Peripheral Section ------------------------ 00088 * ========================================================================== 00089 */ 00090 00091 /* Configuration of the Cortex-M3 Processor and Core Peripherals */ 00092 #define __MPU_PRESENT 1 00093 #define __NVIC_PRIO_BITS 5 00094 #define __Vendor_SysTickConfig 0 00097 #include <arch/cm3/core_cm3.h> /* Cortex-M3 processor and core peripherals */ 00098 #include "system_lpc176x.h" 00099 00100 /******************************************************************************/ 00101 /* Device Specific Peripheral registers structures */ 00102 /******************************************************************************/ 00103 00104 #if defined ( __CC_ARM ) 00105 #pragma anon_unions 00106 #endif 00107 00108 /*------------- System Control (SC) ------------------------------------------*/ 00109 typedef struct 00110 { 00111 __IO uint32_t FLASHCFG; /* Flash Accelerator Module */ 00112 uint32_t RESERVED0[31]; 00113 __IO uint32_t PLL0CON; /* Clocking and Power Control */ 00114 __IO uint32_t PLL0CFG; 00115 __I uint32_t PLL0STAT; 00116 __O uint32_t PLL0FEED; 00117 uint32_t RESERVED1[4]; 00118 __IO uint32_t PLL1CON; 00119 __IO uint32_t PLL1CFG; 00120 __I uint32_t PLL1STAT; 00121 __O uint32_t PLL1FEED; 00122 uint32_t RESERVED2[4]; 00123 __IO uint32_t PCON; 00124 __IO uint32_t PCONP; 00125 uint32_t RESERVED3[15]; 00126 __IO uint32_t CCLKCFG; 00127 __IO uint32_t USBCLKCFG; 00128 __IO uint32_t CLKSRCSEL; 00129 uint32_t RESERVED4[12]; 00130 __IO uint32_t EXTINT; /* External Interrupts */ 00131 uint32_t RESERVED5; 00132 __IO uint32_t EXTMODE; 00133 __IO uint32_t EXTPOLAR; 00134 uint32_t RESERVED6[12]; 00135 __IO uint32_t RSID; /* Reset */ 00136 uint32_t RESERVED7[7]; 00137 __IO uint32_t SCS; /* Syscon Miscellaneous Registers */ 00138 __IO uint32_t IRCTRIM; /* Clock Dividers */ 00139 __IO uint32_t PCLKSEL0; 00140 __IO uint32_t PCLKSEL1; 00141 uint32_t RESERVED8[4]; 00142 __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */ 00143 __IO uint32_t DMAREQSEL; 00144 __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */ 00145 } LPC_SC_TypeDef; 00146 00147 /*------------- Pin Connect Block (PINCON) -----------------------------------*/ 00148 typedef struct 00149 { 00150 __IO uint32_t PINSEL0; 00151 __IO uint32_t PINSEL1; 00152 __IO uint32_t PINSEL2; 00153 __IO uint32_t PINSEL3; 00154 __IO uint32_t PINSEL4; 00155 __IO uint32_t PINSEL5; 00156 __IO uint32_t PINSEL6; 00157 __IO uint32_t PINSEL7; 00158 __IO uint32_t PINSEL8; 00159 __IO uint32_t PINSEL9; 00160 __IO uint32_t PINSEL10; 00161 uint32_t RESERVED0[5]; 00162 __IO uint32_t PINMODE0; 00163 __IO uint32_t PINMODE1; 00164 __IO uint32_t PINMODE2; 00165 __IO uint32_t PINMODE3; 00166 __IO uint32_t PINMODE4; 00167 __IO uint32_t PINMODE5; 00168 __IO uint32_t PINMODE6; 00169 __IO uint32_t PINMODE7; 00170 __IO uint32_t PINMODE8; 00171 __IO uint32_t PINMODE9; 00172 __IO uint32_t PINMODE_OD0; 00173 __IO uint32_t PINMODE_OD1; 00174 __IO uint32_t PINMODE_OD2; 00175 __IO uint32_t PINMODE_OD3; 00176 __IO uint32_t PINMODE_OD4; 00177 __IO uint32_t I2CPADCFG; 00178 } LPC_PINCON_TypeDef; 00179 00180 /*------------- General Purpose Input/Output (GPIO) --------------------------*/ 00181 typedef struct 00182 { 00183 union { 00184 __IO uint32_t FIODIR; 00185 struct { 00186 __IO uint16_t FIODIRL; 00187 __IO uint16_t FIODIRH; 00188 }; 00189 struct { 00190 __IO uint8_t FIODIR0; 00191 __IO uint8_t FIODIR1; 00192 __IO uint8_t FIODIR2; 00193 __IO uint8_t FIODIR3; 00194 }; 00195 }; 00196 uint32_t RESERVED0[3]; 00197 union { 00198 __IO uint32_t FIOMASK; 00199 struct { 00200 __IO uint16_t FIOMASKL; 00201 __IO uint16_t FIOMASKH; 00202 }; 00203 struct { 00204 __IO uint8_t FIOMASK0; 00205 __IO uint8_t FIOMASK1; 00206 __IO uint8_t FIOMASK2; 00207 __IO uint8_t FIOMASK3; 00208 }; 00209 }; 00210 union { 00211 __IO uint32_t FIOPIN; 00212 struct { 00213 __IO uint16_t FIOPINL; 00214 __IO uint16_t FIOPINH; 00215 }; 00216 struct { 00217 __IO uint8_t FIOPIN0; 00218 __IO uint8_t FIOPIN1; 00219 __IO uint8_t FIOPIN2; 00220 __IO uint8_t FIOPIN3; 00221 }; 00222 }; 00223 union { 00224 __IO uint32_t FIOSET; 00225 struct { 00226 __IO uint16_t FIOSETL; 00227 __IO uint16_t FIOSETH; 00228 }; 00229 struct { 00230 __IO uint8_t FIOSET0; 00231 __IO uint8_t FIOSET1; 00232 __IO uint8_t FIOSET2; 00233 __IO uint8_t FIOSET3; 00234 }; 00235 }; 00236 union { 00237 __O uint32_t FIOCLR; 00238 struct { 00239 __O uint16_t FIOCLRL; 00240 __O uint16_t FIOCLRH; 00241 }; 00242 struct { 00243 __O uint8_t FIOCLR0; 00244 __O uint8_t FIOCLR1; 00245 __O uint8_t FIOCLR2; 00246 __O uint8_t FIOCLR3; 00247 }; 00248 }; 00249 } LPC_GPIO_TypeDef; 00250 00251 typedef struct 00252 { 00253 __I uint32_t IntStatus; 00254 __I uint32_t IO0IntStatR; 00255 __I uint32_t IO0IntStatF; 00256 __O uint32_t IO0IntClr; 00257 __IO uint32_t IO0IntEnR; 00258 __IO uint32_t IO0IntEnF; 00259 uint32_t RESERVED0[3]; 00260 __I uint32_t IO2IntStatR; 00261 __I uint32_t IO2IntStatF; 00262 __O uint32_t IO2IntClr; 00263 __IO uint32_t IO2IntEnR; 00264 __IO uint32_t IO2IntEnF; 00265 } LPC_GPIOINT_TypeDef; 00266 00267 /*------------- Timer (TIM) --------------------------------------------------*/ 00268 typedef struct 00269 { 00270 __IO uint32_t IR; 00271 __IO uint32_t TCR; 00272 __IO uint32_t TC; 00273 __IO uint32_t PR; 00274 __IO uint32_t PC; 00275 __IO uint32_t MCR; 00276 __IO uint32_t MR0; 00277 __IO uint32_t MR1; 00278 __IO uint32_t MR2; 00279 __IO uint32_t MR3; 00280 __IO uint32_t CCR; 00281 __I uint32_t CR0; 00282 __I uint32_t CR1; 00283 uint32_t RESERVED0[2]; 00284 __IO uint32_t EMR; 00285 uint32_t RESERVED1[12]; 00286 __IO uint32_t CTCR; 00287 } LPC_TIM_TypeDef; 00288 00289 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/ 00290 typedef struct 00291 { 00292 __IO uint32_t IR; 00293 __IO uint32_t TCR; 00294 __IO uint32_t TC; 00295 __IO uint32_t PR; 00296 __IO uint32_t PC; 00297 __IO uint32_t MCR; 00298 __IO uint32_t MR0; 00299 __IO uint32_t MR1; 00300 __IO uint32_t MR2; 00301 __IO uint32_t MR3; 00302 __IO uint32_t CCR; 00303 __I uint32_t CR0; 00304 __I uint32_t CR1; 00305 __I uint32_t CR2; 00306 __I uint32_t CR3; 00307 uint32_t RESERVED0; 00308 __IO uint32_t MR4; 00309 __IO uint32_t MR5; 00310 __IO uint32_t MR6; 00311 __IO uint32_t PCR; 00312 __IO uint32_t LER; 00313 uint32_t RESERVED1[7]; 00314 __IO uint32_t CTCR; 00315 } LPC_PWM_TypeDef; 00316 00317 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ 00318 typedef struct 00319 { 00320 union { 00321 __I uint8_t RBR; 00322 __O uint8_t THR; 00323 __IO uint8_t DLL; 00324 uint32_t RESERVED0; 00325 }; 00326 union { 00327 __IO uint8_t DLM; 00328 __IO uint32_t IER; 00329 }; 00330 union { 00331 __I uint32_t IIR; 00332 __O uint8_t FCR; 00333 }; 00334 __IO uint8_t LCR; 00335 uint8_t RESERVED1[7]; 00336 __I uint8_t LSR; 00337 uint8_t RESERVED2[7]; 00338 __IO uint8_t SCR; 00339 uint8_t RESERVED3[3]; 00340 __IO uint32_t ACR; 00341 __IO uint8_t ICR; 00342 uint8_t RESERVED4[3]; 00343 __IO uint8_t FDR; 00344 uint8_t RESERVED5[7]; 00345 __IO uint8_t TER; 00346 uint8_t RESERVED6[39]; 00347 __I uint8_t FIFOLVL; 00348 } LPC_UART_TypeDef; 00349 /* 00350 typedef struct 00351 { 00352 union { 00353 __I uint8_t RBR; 00354 __O uint8_t THR; 00355 __IO uint8_t DLL; 00356 uint32_t RESERVED0; 00357 }; 00358 union { 00359 __IO uint8_t DLM; 00360 __IO uint32_t IER; 00361 }; 00362 union { 00363 __I uint32_t IIR; 00364 __O uint8_t FCR; 00365 }; 00366 __IO uint8_t LCR; 00367 uint8_t RESERVED1[7]; 00368 __I uint8_t LSR; 00369 uint8_t RESERVED2[7]; 00370 __IO uint8_t SCR; 00371 uint8_t RESERVED3[3]; 00372 __IO uint32_t ACR; 00373 __IO uint8_t ICR; 00374 uint8_t RESERVED4[3]; 00375 __IO uint8_t FDR; 00376 uint8_t RESERVED5[7]; 00377 __IO uint8_t TER; 00378 uint8_t RESERVED6[39]; 00379 __I uint8_t FIFOLVL; 00380 } LPC_UART0_TypeDef; 00381 */ 00382 typedef struct 00383 { 00384 union { 00385 __I uint8_t RBR; 00386 __O uint8_t THR; 00387 __IO uint8_t DLL; 00388 uint32_t RESERVED0; 00389 }; 00390 union { 00391 __IO uint8_t DLM; 00392 __IO uint32_t IER; 00393 }; 00394 union { 00395 __I uint32_t IIR; 00396 __O uint8_t FCR; 00397 }; 00398 __IO uint8_t LCR; 00399 uint8_t RESERVED1[3]; 00400 __IO uint8_t MCR; 00401 uint8_t RESERVED2[3]; 00402 __I uint8_t LSR; 00403 uint8_t RESERVED3[3]; 00404 __I uint8_t MSR; 00405 uint8_t RESERVED4[3]; 00406 __IO uint8_t SCR; 00407 uint8_t RESERVED5[3]; 00408 __IO uint32_t ACR; 00409 uint32_t RESERVED6; 00410 __IO uint32_t FDR; 00411 uint32_t RESERVED7; 00412 __IO uint8_t TER; 00413 uint8_t RESERVED8[27]; 00414 __IO uint8_t RS485CTRL; 00415 uint8_t RESERVED9[3]; 00416 __IO uint8_t ADRMATCH; 00417 uint8_t RESERVED10[3]; 00418 __IO uint8_t RS485DLY; 00419 uint8_t RESERVED11[3]; 00420 __I uint8_t FIFOLVL; 00421 } LPC_UART1_TypeDef; 00422 00423 /*------------- Serial Peripheral Interface (SPI) ----------------------------*/ 00424 typedef struct 00425 { 00426 __IO uint32_t SPCR; 00427 __I uint32_t SPSR; 00428 __IO uint32_t SPDR; 00429 __IO uint32_t SPCCR; 00430 uint32_t RESERVED0[3]; 00431 __IO uint32_t SPINT; 00432 } LPC_SPI_TypeDef; 00433 00434 /*------------- Synchronous Serial Communication (SSP) -----------------------*/ 00435 typedef struct 00436 { 00437 __IO uint32_t CR0; 00438 __IO uint32_t CR1; 00439 __IO uint32_t DR; 00440 __I uint32_t SR; 00441 __IO uint32_t CPSR; 00442 __IO uint32_t IMSC; 00443 __IO uint32_t RIS; 00444 __IO uint32_t MIS; 00445 __IO uint32_t ICR; 00446 __IO uint32_t DMACR; 00447 } LPC_SSP_TypeDef; 00448 00449 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/ 00450 typedef struct 00451 { 00452 __IO uint32_t I2CONSET; 00453 __I uint32_t I2STAT; 00454 __IO uint32_t I2DAT; 00455 __IO uint32_t I2ADR0; 00456 __IO uint32_t I2SCLH; 00457 __IO uint32_t I2SCLL; 00458 __O uint32_t I2CONCLR; 00459 __IO uint32_t MMCTRL; 00460 __IO uint32_t I2ADR1; 00461 __IO uint32_t I2ADR2; 00462 __IO uint32_t I2ADR3; 00463 __I uint32_t I2DATA_BUFFER; 00464 __IO uint32_t I2MASK0; 00465 __IO uint32_t I2MASK1; 00466 __IO uint32_t I2MASK2; 00467 __IO uint32_t I2MASK3; 00468 } LPC_I2C_TypeDef; 00469 00470 /*------------- Inter IC Sound (I2S) -----------------------------------------*/ 00471 typedef struct 00472 { 00473 __IO uint32_t I2SDAO; 00474 __IO uint32_t I2SDAI; 00475 __O uint32_t I2STXFIFO; 00476 __I uint32_t I2SRXFIFO; 00477 __I uint32_t I2SSTATE; 00478 __IO uint32_t I2SDMA1; 00479 __IO uint32_t I2SDMA2; 00480 __IO uint32_t I2SIRQ; 00481 __IO uint32_t I2STXRATE; 00482 __IO uint32_t I2SRXRATE; 00483 __IO uint32_t I2STXBITRATE; 00484 __IO uint32_t I2SRXBITRATE; 00485 __IO uint32_t I2STXMODE; 00486 __IO uint32_t I2SRXMODE; 00487 } LPC_I2S_TypeDef; 00488 00489 /*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/ 00490 typedef struct 00491 { 00492 __IO uint32_t RICOMPVAL; 00493 __IO uint32_t RIMASK; 00494 __IO uint8_t RICTRL; 00495 uint8_t RESERVED0[3]; 00496 __IO uint32_t RICOUNTER; 00497 } LPC_RIT_TypeDef; 00498 00499 /*------------- Real-Time Clock (RTC) ----------------------------------------*/ 00500 typedef struct 00501 { 00502 __IO uint8_t ILR; 00503 uint8_t RESERVED0[7]; 00504 __IO uint8_t CCR; 00505 uint8_t RESERVED1[3]; 00506 __IO uint8_t CIIR; 00507 uint8_t RESERVED2[3]; 00508 __IO uint8_t AMR; 00509 uint8_t RESERVED3[3]; 00510 __I uint32_t CTIME0; 00511 __I uint32_t CTIME1; 00512 __I uint32_t CTIME2; 00513 __IO uint8_t SEC; 00514 uint8_t RESERVED4[3]; 00515 __IO uint8_t MIN; 00516 uint8_t RESERVED5[3]; 00517 __IO uint8_t HOUR; 00518 uint8_t RESERVED6[3]; 00519 __IO uint8_t DOM; 00520 uint8_t RESERVED7[3]; 00521 __IO uint8_t DOW; 00522 uint8_t RESERVED8[3]; 00523 __IO uint16_t DOY; 00524 uint16_t RESERVED9; 00525 __IO uint8_t MONTH; 00526 uint8_t RESERVED10[3]; 00527 __IO uint16_t YEAR; 00528 uint16_t RESERVED11; 00529 __IO uint32_t CALIBRATION; 00530 __IO uint32_t GPREG0; 00531 __IO uint32_t GPREG1; 00532 __IO uint32_t GPREG2; 00533 __IO uint32_t GPREG3; 00534 __IO uint32_t GPREG4; 00535 __IO uint8_t RTC_AUXEN; 00536 uint8_t RESERVED12[3]; 00537 __IO uint8_t RTC_AUX; 00538 uint8_t RESERVED13[3]; 00539 __IO uint8_t ALSEC; 00540 uint8_t RESERVED14[3]; 00541 __IO uint8_t ALMIN; 00542 uint8_t RESERVED15[3]; 00543 __IO uint8_t ALHOUR; 00544 uint8_t RESERVED16[3]; 00545 __IO uint8_t ALDOM; 00546 uint8_t RESERVED17[3]; 00547 __IO uint8_t ALDOW; 00548 uint8_t RESERVED18[3]; 00549 __IO uint16_t ALDOY; 00550 uint16_t RESERVED19; 00551 __IO uint8_t ALMON; 00552 uint8_t RESERVED20[3]; 00553 __IO uint16_t ALYEAR; 00554 uint16_t RESERVED21; 00555 } LPC_RTC_TypeDef; 00556 00557 /*------------- Watchdog Timer (WDT) -----------------------------------------*/ 00558 typedef struct 00559 { 00560 __IO uint8_t MOD; 00561 uint8_t RESERVED0[3]; 00562 __IO uint32_t TC; 00563 __O uint8_t FEED; 00564 uint8_t RESERVED1[3]; 00565 __I uint32_t TV; 00566 __IO uint32_t CLKSEL; 00567 } LPC_WDT_TypeDef; 00568 00569 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/ 00570 typedef struct 00571 { 00572 __IO uint32_t ADCR; 00573 __IO uint32_t ADGDR; 00574 uint32_t RESERVED0; 00575 __IO uint32_t ADINTEN; 00576 __I uint32_t ADDR0; 00577 __I uint32_t ADDR1; 00578 __I uint32_t ADDR2; 00579 __I uint32_t ADDR3; 00580 __I uint32_t ADDR4; 00581 __I uint32_t ADDR5; 00582 __I uint32_t ADDR6; 00583 __I uint32_t ADDR7; 00584 __I uint32_t ADSTAT; 00585 __IO uint32_t ADTRM; 00586 } LPC_ADC_TypeDef; 00587 00588 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/ 00589 typedef struct 00590 { 00591 __IO uint32_t DACR; 00592 __IO uint32_t DACCTRL; 00593 __IO uint16_t DACCNTVAL; 00594 } LPC_DAC_TypeDef; 00595 00596 /*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/ 00597 typedef struct 00598 { 00599 __I uint32_t MCCON; 00600 __O uint32_t MCCON_SET; 00601 __O uint32_t MCCON_CLR; 00602 __I uint32_t MCCAPCON; 00603 __O uint32_t MCCAPCON_SET; 00604 __O uint32_t MCCAPCON_CLR; 00605 __IO uint32_t MCTIM0; 00606 __IO uint32_t MCTIM1; 00607 __IO uint32_t MCTIM2; 00608 __IO uint32_t MCPER0; 00609 __IO uint32_t MCPER1; 00610 __IO uint32_t MCPER2; 00611 __IO uint32_t MCPW0; 00612 __IO uint32_t MCPW1; 00613 __IO uint32_t MCPW2; 00614 __IO uint32_t MCDEADTIME; 00615 __IO uint32_t MCCCP; 00616 __IO uint32_t MCCR0; 00617 __IO uint32_t MCCR1; 00618 __IO uint32_t MCCR2; 00619 __I uint32_t MCINTEN; 00620 __O uint32_t MCINTEN_SET; 00621 __O uint32_t MCINTEN_CLR; 00622 __I uint32_t MCCNTCON; 00623 __O uint32_t MCCNTCON_SET; 00624 __O uint32_t MCCNTCON_CLR; 00625 __I uint32_t MCINTFLAG; 00626 __O uint32_t MCINTFLAG_SET; 00627 __O uint32_t MCINTFLAG_CLR; 00628 __O uint32_t MCCAP_CLR; 00629 } LPC_MCPWM_TypeDef; 00630 00631 /*------------- Quadrature Encoder Interface (QEI) ---------------------------*/ 00632 typedef struct 00633 { 00634 __O uint32_t QEICON; 00635 __I uint32_t QEISTAT; 00636 __IO uint32_t QEICONF; 00637 __I uint32_t QEIPOS; 00638 __IO uint32_t QEIMAXPOS; 00639 __IO uint32_t CMPOS0; 00640 __IO uint32_t CMPOS1; 00641 __IO uint32_t CMPOS2; 00642 __I uint32_t INXCNT; 00643 __IO uint32_t INXCMP; 00644 __IO uint32_t QEILOAD; 00645 __I uint32_t QEITIME; 00646 __I uint32_t QEIVEL; 00647 __I uint32_t QEICAP; 00648 __IO uint32_t VELCOMP; 00649 __IO uint32_t FILTER; 00650 uint32_t RESERVED0[998]; 00651 __O uint32_t QEIIEC; 00652 __O uint32_t QEIIES; 00653 __I uint32_t QEIINTSTAT; 00654 __I uint32_t QEIIE; 00655 __O uint32_t QEICLR; 00656 __O uint32_t QEISET; 00657 } LPC_QEI_TypeDef; 00658 00659 /*------------- Controller Area Network (CAN) --------------------------------*/ 00660 typedef struct 00661 { 00662 __IO uint32_t mask[512]; /* ID Masks */ 00663 } LPC_CANAF_RAM_TypeDef; 00664 00665 typedef struct /* Acceptance Filter Registers */ 00666 { 00667 __IO uint32_t AFMR; 00668 __IO uint32_t SFF_sa; 00669 __IO uint32_t SFF_GRP_sa; 00670 __IO uint32_t EFF_sa; 00671 __IO uint32_t EFF_GRP_sa; 00672 __IO uint32_t ENDofTable; 00673 __I uint32_t LUTerrAd; 00674 __I uint32_t LUTerr; 00675 __IO uint32_t FCANIE; 00676 __IO uint32_t FCANIC0; 00677 __IO uint32_t FCANIC1; 00678 } LPC_CANAF_TypeDef; 00679 00680 typedef struct /* Central Registers */ 00681 { 00682 __I uint32_t CANTxSR; 00683 __I uint32_t CANRxSR; 00684 __I uint32_t CANMSR; 00685 } LPC_CANCR_TypeDef; 00686 00687 typedef struct /* Controller Registers */ 00688 { 00689 __IO uint32_t MOD; 00690 __O uint32_t CMR; 00691 __IO uint32_t GSR; 00692 __I uint32_t ICR; 00693 __IO uint32_t IER; 00694 __IO uint32_t BTR; 00695 __IO uint32_t EWL; 00696 __I uint32_t SR; 00697 __IO uint32_t RFS; 00698 __IO uint32_t RID; 00699 __IO uint32_t RDA; 00700 __IO uint32_t RDB; 00701 __IO uint32_t TFI1; 00702 __IO uint32_t TID1; 00703 __IO uint32_t TDA1; 00704 __IO uint32_t TDB1; 00705 __IO uint32_t TFI2; 00706 __IO uint32_t TID2; 00707 __IO uint32_t TDA2; 00708 __IO uint32_t TDB2; 00709 __IO uint32_t TFI3; 00710 __IO uint32_t TID3; 00711 __IO uint32_t TDA3; 00712 __IO uint32_t TDB3; 00713 } LPC_CAN_TypeDef; 00714 00715 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/ 00716 typedef struct /* Common Registers */ 00717 { 00718 __I uint32_t DMACIntStat; 00719 __I uint32_t DMACIntTCStat; 00720 __O uint32_t DMACIntTCClear; 00721 __I uint32_t DMACIntErrStat; 00722 __O uint32_t DMACIntErrClr; 00723 __I uint32_t DMACRawIntTCStat; 00724 __I uint32_t DMACRawIntErrStat; 00725 __I uint32_t DMACEnbldChns; 00726 __IO uint32_t DMACSoftBReq; 00727 __IO uint32_t DMACSoftSReq; 00728 __IO uint32_t DMACSoftLBReq; 00729 __IO uint32_t DMACSoftLSReq; 00730 __IO uint32_t DMACConfig; 00731 __IO uint32_t DMACSync; 00732 } LPC_GPDMA_TypeDef; 00733 00734 typedef struct /* Channel Registers */ 00735 { 00736 __IO uint32_t DMACCSrcAddr; 00737 __IO uint32_t DMACCDestAddr; 00738 __IO uint32_t DMACCLLI; 00739 __IO uint32_t DMACCControl; 00740 __IO uint32_t DMACCConfig; 00741 } LPC_GPDMACH_TypeDef; 00742 00743 /*------------- Universal Serial Bus (USB) -----------------------------------*/ 00744 typedef struct 00745 { 00746 __I uint32_t HcRevision; /* USB Host Registers */ 00747 __IO uint32_t HcControl; 00748 __IO uint32_t HcCommandStatus; 00749 __IO uint32_t HcInterruptStatus; 00750 __IO uint32_t HcInterruptEnable; 00751 __IO uint32_t HcInterruptDisable; 00752 __IO uint32_t HcHCCA; 00753 __I uint32_t HcPeriodCurrentED; 00754 __IO uint32_t HcControlHeadED; 00755 __IO uint32_t HcControlCurrentED; 00756 __IO uint32_t HcBulkHeadED; 00757 __IO uint32_t HcBulkCurrentED; 00758 __I uint32_t HcDoneHead; 00759 __IO uint32_t HcFmInterval; 00760 __I uint32_t HcFmRemaining; 00761 __I uint32_t HcFmNumber; 00762 __IO uint32_t HcPeriodicStart; 00763 __IO uint32_t HcLSTreshold; 00764 __IO uint32_t HcRhDescriptorA; 00765 __IO uint32_t HcRhDescriptorB; 00766 __IO uint32_t HcRhStatus; 00767 __IO uint32_t HcRhPortStatus1; 00768 __IO uint32_t HcRhPortStatus2; 00769 uint32_t RESERVED0[40]; 00770 __I uint32_t Module_ID; 00771 00772 __I uint32_t OTGIntSt; /* USB On-The-Go Registers */ 00773 __IO uint32_t OTGIntEn; 00774 __O uint32_t OTGIntSet; 00775 __O uint32_t OTGIntClr; 00776 __IO uint32_t OTGStCtrl; 00777 __IO uint32_t OTGTmr; 00778 uint32_t RESERVED1[58]; 00779 00780 __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */ 00781 __IO uint32_t USBDevIntEn; 00782 __O uint32_t USBDevIntClr; 00783 __O uint32_t USBDevIntSet; 00784 00785 __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */ 00786 __I uint32_t USBCmdData; 00787 00788 __I uint32_t USBRxData; /* USB Device Transfer Registers */ 00789 __O uint32_t USBTxData; 00790 __I uint32_t USBRxPLen; 00791 __O uint32_t USBTxPLen; 00792 __IO uint32_t USBCtrl; 00793 __O uint32_t USBDevIntPri; 00794 00795 __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */ 00796 __IO uint32_t USBEpIntEn; 00797 __O uint32_t USBEpIntClr; 00798 __O uint32_t USBEpIntSet; 00799 __O uint32_t USBEpIntPri; 00800 00801 __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/ 00802 __O uint32_t USBEpInd; 00803 __IO uint32_t USBMaxPSize; 00804 00805 __I uint32_t USBDMARSt; /* USB Device DMA Registers */ 00806 __O uint32_t USBDMARClr; 00807 __O uint32_t USBDMARSet; 00808 uint32_t RESERVED2[9]; 00809 __IO uint32_t USBUDCAH; 00810 __I uint32_t USBEpDMASt; 00811 __O uint32_t USBEpDMAEn; 00812 __O uint32_t USBEpDMADis; 00813 __I uint32_t USBDMAIntSt; 00814 __IO uint32_t USBDMAIntEn; 00815 uint32_t RESERVED3[2]; 00816 __I uint32_t USBEoTIntSt; 00817 __O uint32_t USBEoTIntClr; 00818 __O uint32_t USBEoTIntSet; 00819 __I uint32_t USBNDDRIntSt; 00820 __O uint32_t USBNDDRIntClr; 00821 __O uint32_t USBNDDRIntSet; 00822 __I uint32_t USBSysErrIntSt; 00823 __O uint32_t USBSysErrIntClr; 00824 __O uint32_t USBSysErrIntSet; 00825 uint32_t RESERVED4[15]; 00826 00827 __I uint32_t I2C_RX; /* USB OTG I2C Registers */ 00828 __O uint32_t I2C_WO; 00829 __I uint32_t I2C_STS; 00830 __IO uint32_t I2C_CTL; 00831 __IO uint32_t I2C_CLKHI; 00832 __O uint32_t I2C_CLKLO; 00833 uint32_t RESERVED5[823]; 00834 00835 union { 00836 __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */ 00837 __IO uint32_t OTGClkCtrl; 00838 }; 00839 union { 00840 __I uint32_t USBClkSt; 00841 __I uint32_t OTGClkSt; 00842 }; 00843 } LPC_USB_TypeDef; 00844 00845 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/ 00846 typedef struct 00847 { 00848 __IO uint32_t MAC1; /* MAC Registers */ 00849 __IO uint32_t MAC2; 00850 __IO uint32_t IPGT; 00851 __IO uint32_t IPGR; 00852 __IO uint32_t CLRT; 00853 __IO uint32_t MAXF; 00854 __IO uint32_t SUPP; 00855 __IO uint32_t TEST; 00856 __IO uint32_t MCFG; 00857 __IO uint32_t MCMD; 00858 __IO uint32_t MADR; 00859 __O uint32_t MWTD; 00860 __I uint32_t MRDD; 00861 __I uint32_t MIND; 00862 uint32_t RESERVED0[2]; 00863 __IO uint32_t SA0; 00864 __IO uint32_t SA1; 00865 __IO uint32_t SA2; 00866 uint32_t RESERVED1[45]; 00867 __IO uint32_t Command; /* Control Registers */ 00868 __I uint32_t Status; 00869 __IO uint32_t RxDescriptor; 00870 __IO uint32_t RxStatus; 00871 __IO uint32_t RxDescriptorNumber; 00872 __I uint32_t RxProduceIndex; 00873 __IO uint32_t RxConsumeIndex; 00874 __IO uint32_t TxDescriptor; 00875 __IO uint32_t TxStatus; 00876 __IO uint32_t TxDescriptorNumber; 00877 __IO uint32_t TxProduceIndex; 00878 __I uint32_t TxConsumeIndex; 00879 uint32_t RESERVED2[10]; 00880 __I uint32_t TSV0; 00881 __I uint32_t TSV1; 00882 __I uint32_t RSV; 00883 uint32_t RESERVED3[3]; 00884 __IO uint32_t FlowControlCounter; 00885 __I uint32_t FlowControlStatus; 00886 uint32_t RESERVED4[34]; 00887 __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */ 00888 __IO uint32_t RxFilterWoLStatus; 00889 __IO uint32_t RxFilterWoLClear; 00890 uint32_t RESERVED5; 00891 __IO uint32_t HashFilterL; 00892 __IO uint32_t HashFilterH; 00893 uint32_t RESERVED6[882]; 00894 __I uint32_t IntStatus; /* Module Control Registers */ 00895 __IO uint32_t IntEnable; 00896 __O uint32_t IntClear; 00897 __O uint32_t IntSet; 00898 uint32_t RESERVED7; 00899 __IO uint32_t PowerDown; 00900 uint32_t RESERVED8; 00901 __IO uint32_t Module_ID; 00902 } LPC_EMAC_TypeDef; 00903 00904 #if defined ( __CC_ARM ) 00905 #pragma no_anon_unions 00906 #endif 00907 00908 00909 /******************************************************************************/ 00910 /* Peripheral memory map */ 00911 /******************************************************************************/ 00912 /* Base addresses */ 00913 #define LPC_FLASH_BASE (0x00000000UL) 00914 #define LPC_RAM_BASE (0x10000000UL) 00915 #define LPC_GPIO_BASE (0x2009C000UL) 00916 #define LPC_APB0_BASE (0x40000000UL) 00917 #define LPC_APB1_BASE (0x40080000UL) 00918 #define LPC_AHB_BASE (0x50000000UL) 00919 #define LPC_CM3_BASE (0xE0000000UL) 00920 00921 /* APB0 peripherals */ 00922 #define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000) 00923 #define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000) 00924 #define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000) 00925 #define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000) 00926 #define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000) 00927 #define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000) 00928 #define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000) 00929 #define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000) 00930 #define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000) 00931 #define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080) 00932 #define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000) 00933 #define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000) 00934 #define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000) 00935 #define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000) 00936 #define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000) 00937 #define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000) 00938 #define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000) 00939 #define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000) 00940 #define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000) 00941 00942 /* APB1 peripherals */ 00943 #define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000) 00944 #define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000) 00945 #define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000) 00946 #define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000) 00947 #define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000) 00948 #define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000) 00949 #define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000) 00950 #define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000) 00951 #define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000) 00952 #define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000) 00953 #define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000) 00954 #define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000) 00955 00956 /* AHB peripherals */ 00957 #define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000) 00958 #define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000) 00959 #define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100) 00960 #define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120) 00961 #define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140) 00962 #define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160) 00963 #define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180) 00964 #define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0) 00965 #define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0) 00966 #define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0) 00967 #define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000) 00968 00969 /* GPIOs */ 00970 #define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000) 00971 #define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020) 00972 #define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040) 00973 #define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060) 00974 #define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080) 00975 00976 00977 /******************************************************************************/ 00978 /* Peripheral declaration */ 00979 /******************************************************************************/ 00980 #define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE ) 00981 #define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE ) 00982 #define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE ) 00983 #define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE ) 00984 #define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE ) 00985 #define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE ) 00986 #define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE ) 00987 #define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE ) 00988 #define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE ) 00989 #define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE ) 00990 #define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE ) 00991 #define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE ) 00992 //#define LPC_UART0 ((LPC_UART0_TypeDef *) LPC_UART0_BASE ) 00993 #define LPC_UART0 ((LPC_UART_TypeDef *) LPC_UART0_BASE ) 00994 #define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE ) 00995 #define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE ) 00996 #define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE ) 00997 #define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE ) 00998 #define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE ) 00999 #define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE ) 01000 #define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE ) 01001 #define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE ) 01002 #define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE ) 01003 #define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE ) 01004 #define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE ) 01005 #define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE ) 01006 #define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE ) 01007 #define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE ) 01008 #define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE ) 01009 #define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE ) 01010 #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE) 01011 #define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE ) 01012 #define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE ) 01013 #define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE ) 01014 #define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE ) 01015 #define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE ) 01016 #define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE ) 01017 #define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE ) 01018 #define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE ) 01019 #define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE ) 01020 #define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE ) 01021 #define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE ) 01022 #define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE ) 01023 #define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE ) 01024 #define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE ) 01025 #define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE ) 01026 #define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE ) 01027 #define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE ) 01028 01029 #endif // __LPC17xx_H__