ih_irq0.c

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/*
 * $Log: ih_irq0.c,v $
 *
 */

#include <arch/avr32.h>
#include <dev/irqreg.h>
#include <dev/gpio.h>

#include <arch/avr32/gpio.h>
#include <arch/avr32/ihndlr.h>

#include <avr32/io.h>

#ifdef AVR32_EIC_IRQ_0

#ifndef NUT_IRQPRI_IRQ0
#define NUT_IRQPRI_IRQ0  AVR32_INTC_INT3
#endif

static int Interrupt0Ctl(int cmd, void *param);

IRQ_HANDLER sig_INTERRUPT0 = {
#ifdef NUT_PERFMON
    0,                          /* Interrupt counter, ir_count. */
#endif
    NULL,                       /* Passed argument, ir_arg. */
    NULL,                       /* Handler subroutine, ir_handler. */
    Interrupt0Ctl               /* Interrupt control, ir_ctl. */
};

static SIGNAL(Interrupt0Entry)
{
    IRQ_ENTRY();
#ifdef NUT_PERFMON
    sig_INTERRUPT0.ir_count++;
#endif
    if (sig_INTERRUPT0.ir_handler) {
        (sig_INTERRUPT0.ir_handler) (sig_INTERRUPT0.ir_arg);
    }
    /* Clear interrupt */
    AVR32_EIC.icr = AVR32_EIC_ICR_INT0_MASK;
    AVR32_EIC.isr;

    IRQ_EXIT();
}

static int Interrupt0Ctl(int cmd, void *param)
{
    int rc = 0;
    unsigned int *ival = (unsigned int *) param;
    int_fast8_t enabled = AVR32_EIC.imr & AVR32_EIC_IMR_INT0_MASK;

    /* Disable interrupt. */
    if (enabled) {
        AVR32_EIC.idr = AVR32_EIC_IDR_INT0_MASK;
        AVR32_EIC.imr;
    }

    switch (cmd) {
    case NUT_IRQCTL_INIT:
#if defined(AVR32_EIC_EXTINT_0_PIN)
        /* Setup Peripheral mux for interrupt line */
        gpio_enable_module_pin(AVR32_EIC_EXTINT_0_PIN, AVR32_EIC_EXTINT_0_FUNCTION);
#endif
        /* Set the vector. */
        register_interrupt(Interrupt0Entry, AVR32_EIC_IRQ_0, NUT_IRQPRI_IRQ0);
        /* Initialize to edge triggered with defined priority. */
        AVR32_EIC.mode &= ~AVR32_EIC_MODE_INT0_MASK;
        /* Clear interrupt */
        AVR32_EIC.icr = AVR32_EIC_ICR_INT0_MASK;
        break;
    case NUT_IRQCTL_STATUS:
        if (enabled) {
            *ival |= 1;
        } else {
            *ival &= ~1;
        }
        break;
    case NUT_IRQCTL_ENABLE:
        enabled = 1;
        break;
    case NUT_IRQCTL_DISABLE:
        enabled = 0;
        break;
    case NUT_IRQCTL_GETMODE:
        {
            if (AVR32_EIC.mode & AVR32_EIC_MODE_INT0_MASK) {
                if (AVR32_EIC.level & AVR32_EIC_LEVEL_INT0_MASK)
                    *ival = NUT_IRQMODE_HIGHLEVEL;
                else
                    *ival = NUT_IRQMODE_LOWLEVEL;
            } else {
                if (AVR32_EIC.edge & AVR32_EIC_EDGE_INT0_MASK)
                    *ival = NUT_IRQMODE_RISINGEDGE;
                else
                    *ival = NUT_IRQMODE_FALLINGEDGE;
            }
        }
        break;
    case NUT_IRQCTL_SETMODE:
        if (*ival == NUT_IRQMODE_LOWLEVEL) {
            AVR32_EIC.mode |= AVR32_EIC_MODE_INT0_MASK;
            AVR32_EIC.level &= ~AVR32_EIC_LEVEL_INT0_MASK;
        } else if (*ival == NUT_IRQMODE_HIGHLEVEL) {
            AVR32_EIC.mode |= AVR32_EIC_MODE_INT0_MASK;
            AVR32_EIC.level |= ~AVR32_EIC_LEVEL_INT0_MASK;
        } else if (*ival == NUT_IRQMODE_FALLINGEDGE) {
            AVR32_EIC.mode &= ~AVR32_EIC_MODE_INT0_MASK;
            AVR32_EIC.edge &= ~AVR32_EIC_EDGE_INT0_MASK;
        } else if (*ival == NUT_IRQMODE_RISINGEDGE) {
            AVR32_EIC.mode &= ~AVR32_EIC_MODE_INT0_MASK;
            AVR32_EIC.edge |= ~AVR32_EIC_EDGE_INT0_MASK;
        } else {
            rc = -1;
        }
        break;
    case NUT_IRQCTL_GETPRIO:
        *ival = NUT_IRQPRI_IRQ0;
        break;
#ifdef NUT_PERFMON
    case NUT_IRQCTL_GETCOUNT:
        *ival = (unsigned int) sig_INTERRUPT0.ir_count;
        sig_INTERRUPT0.ir_count = 0;
        break;
#endif
    default:
        rc = -1;
        break;
    }

    /* Enable interrupt. */
    if (enabled) {
        AVR32_EIC.ier = AVR32_EIC_IER_INT0_MASK;
        AVR32_EIC.imr;
#if !defined( __AVR32_AP7000__ )
        AVR32_EIC.en |= AVR32_EIC_EN_INT0_MASK;
#endif
    }
    return rc;
}

#endif // AVR32_EIC_IRQ_1