Instrumentation Trace Macrocell (ITM)

Type definitions for the Instrumentation Trace Macrocell (ITM) More...

Collaboration diagram for Instrumentation Trace Macrocell (ITM):

Data Structures
struct	ITM_Type
	Structure type to access the Instrumentation Trace Macrocell Register (ITM). More...
Defines
#define	ITM_TPR_PRIVMASK_Pos   0
#define	ITM_TPR_PRIVMASK_Msk   (0xFUL << ITM_TPR_PRIVMASK_Pos)
#define	ITM_TCR_BUSY_Pos   23
#define	ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)
#define	ITM_TCR_TraceBusID_Pos   16
#define	ITM_TCR_TraceBusID_Msk   (0x7FUL << ITM_TCR_TraceBusID_Pos)
#define	ITM_TCR_GTSFREQ_Pos   10
#define	ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)
#define	ITM_TCR_TSPrescale_Pos   8
#define	ITM_TCR_TSPrescale_Msk   (3UL << ITM_TCR_TSPrescale_Pos)
#define	ITM_TCR_SWOENA_Pos   4
#define	ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)
#define	ITM_TCR_TXENA_Pos   3
#define	ITM_TCR_TXENA_Msk   (1UL << ITM_TCR_TXENA_Pos)
#define	ITM_TCR_SYNCENA_Pos   2
#define	ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)
#define	ITM_TCR_TSENA_Pos   1
#define	ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)
#define	ITM_TCR_ITMENA_Pos   0
#define	ITM_TCR_ITMENA_Msk   (1UL << ITM_TCR_ITMENA_Pos)
#define	ITM_TPR_PRIVMASK_Pos   0
#define	ITM_TPR_PRIVMASK_Msk   (0xFUL << ITM_TPR_PRIVMASK_Pos)
#define	ITM_TCR_BUSY_Pos   23
#define	ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)
#define	ITM_TCR_TraceBusID_Pos   16
#define	ITM_TCR_TraceBusID_Msk   (0x7FUL << ITM_TCR_TraceBusID_Pos)
#define	ITM_TCR_GTSFREQ_Pos   10
#define	ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)
#define	ITM_TCR_TSPrescale_Pos   8
#define	ITM_TCR_TSPrescale_Msk   (3UL << ITM_TCR_TSPrescale_Pos)
#define	ITM_TCR_SWOENA_Pos   4
#define	ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)
#define	ITM_TCR_DWTENA_Pos   3
#define	ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)
#define	ITM_TCR_SYNCENA_Pos   2
#define	ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)
#define	ITM_TCR_TSENA_Pos   1
#define	ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)
#define	ITM_TCR_ITMENA_Pos   0
#define	ITM_TCR_ITMENA_Msk   (1UL << ITM_TCR_ITMENA_Pos)
#define	ITM_IWR_ATVALIDM_Pos   0
#define	ITM_IWR_ATVALIDM_Msk   (1UL << ITM_IWR_ATVALIDM_Pos)
#define	ITM_IRR_ATREADYM_Pos   0
#define	ITM_IRR_ATREADYM_Msk   (1UL << ITM_IRR_ATREADYM_Pos)
#define	ITM_IMCR_INTEGRATION_Pos   0
#define	ITM_IMCR_INTEGRATION_Msk   (1UL << ITM_IMCR_INTEGRATION_Pos)
#define	ITM_LSR_ByteAcc_Pos   2
#define	ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)
#define	ITM_LSR_Access_Pos   1
#define	ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)
#define	ITM_LSR_Present_Pos   0
#define	ITM_LSR_Present_Msk   (1UL << ITM_LSR_Present_Pos)

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Detailed Description

Type definitions for the Instrumentation Trace Macrocell (ITM)

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Define Documentation

#define ITM_TPR_PRIVMASK_Pos   0

ITM TPR: PRIVMASK Position

#define ITM_TPR_PRIVMASK_Msk   (0xFUL << ITM_TPR_PRIVMASK_Pos)

ITM TPR: PRIVMASK Mask

#define ITM_TCR_BUSY_Pos   23

ITM TCR: BUSY Position

#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

#define ITM_TCR_TraceBusID_Pos   16

ITM TCR: ATBID Position

#define ITM_TCR_TraceBusID_Msk   (0x7FUL << ITM_TCR_TraceBusID_Pos)

ITM TCR: ATBID Mask

#define ITM_TCR_GTSFREQ_Pos   10

ITM TCR: Global timestamp frequency Position

#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

#define ITM_TCR_TSPrescale_Pos   8

ITM TCR: TSPrescale Position

#define ITM_TCR_TSPrescale_Msk   (3UL << ITM_TCR_TSPrescale_Pos)

ITM TCR: TSPrescale Mask

#define ITM_TCR_SWOENA_Pos   4

ITM TCR: SWOENA Position

#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

#define ITM_TCR_TXENA_Pos   3

ITM TCR: TXENA Position

#define ITM_TCR_TXENA_Msk   (1UL << ITM_TCR_TXENA_Pos)

ITM TCR: TXENA Mask

#define ITM_TCR_SYNCENA_Pos   2

ITM TCR: SYNCENA Position

#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

#define ITM_TCR_TSENA_Pos   1

ITM TCR: TSENA Position

#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

#define ITM_TCR_ITMENA_Pos   0

ITM TCR: ITM Enable bit Position

#define ITM_TCR_ITMENA_Msk   (1UL << ITM_TCR_ITMENA_Pos)

ITM TCR: ITM Enable bit Mask

Referenced by ITM_SendChar().

#define ITM_TPR_PRIVMASK_Pos   0

ITM TPR: PRIVMASK Position

#define ITM_TPR_PRIVMASK_Msk   (0xFUL << ITM_TPR_PRIVMASK_Pos)

ITM TPR: PRIVMASK Mask

#define ITM_TCR_BUSY_Pos   23

ITM TCR: BUSY Position

#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

#define ITM_TCR_TraceBusID_Pos   16

ITM TCR: ATBID Position

#define ITM_TCR_TraceBusID_Msk   (0x7FUL << ITM_TCR_TraceBusID_Pos)

ITM TCR: ATBID Mask

#define ITM_TCR_GTSFREQ_Pos   10

ITM TCR: Global timestamp frequency Position

#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

#define ITM_TCR_TSPrescale_Pos   8

ITM TCR: TSPrescale Position

#define ITM_TCR_TSPrescale_Msk   (3UL << ITM_TCR_TSPrescale_Pos)

ITM TCR: TSPrescale Mask

#define ITM_TCR_SWOENA_Pos   4

ITM TCR: SWOENA Position

#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

#define ITM_TCR_DWTENA_Pos   3

ITM TCR: DWTENA Position

#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

#define ITM_TCR_SYNCENA_Pos   2

ITM TCR: SYNCENA Position

#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

#define ITM_TCR_TSENA_Pos   1

ITM TCR: TSENA Position

#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

#define ITM_TCR_ITMENA_Pos   0

ITM TCR: ITM Enable bit Position

#define ITM_TCR_ITMENA_Msk   (1UL << ITM_TCR_ITMENA_Pos)

ITM TCR: ITM Enable bit Mask

#define ITM_IWR_ATVALIDM_Pos   0

ITM IWR: ATVALIDM Position

#define ITM_IWR_ATVALIDM_Msk   (1UL << ITM_IWR_ATVALIDM_Pos)

ITM IWR: ATVALIDM Mask

#define ITM_IRR_ATREADYM_Pos   0

ITM IRR: ATREADYM Position

#define ITM_IRR_ATREADYM_Msk   (1UL << ITM_IRR_ATREADYM_Pos)

ITM IRR: ATREADYM Mask

#define ITM_IMCR_INTEGRATION_Pos   0

ITM IMCR: INTEGRATION Position

#define ITM_IMCR_INTEGRATION_Msk   (1UL << ITM_IMCR_INTEGRATION_Pos)

ITM IMCR: INTEGRATION Mask

#define ITM_LSR_ByteAcc_Pos   2

ITM LSR: ByteAcc Position

#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

#define ITM_LSR_Access_Pos   1

ITM LSR: Access Position

#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

#define ITM_LSR_Present_Pos   0

ITM LSR: Present Position

#define ITM_LSR_Present_Msk   (1UL << ITM_LSR_Present_Pos)

ITM LSR: Present Mask