Collaboration diagram for Peripheral_declaration:

Defines
#define	TIM2 ((TIM_TypeDef *) TIM2_BASE)
#define	TIM3 ((TIM_TypeDef *) TIM3_BASE)
#define	TIM4 ((TIM_TypeDef *) TIM4_BASE)
#define	TIM5 ((TIM_TypeDef *) TIM5_BASE)
#define	TIM6 ((TIM_TypeDef *) TIM6_BASE)
#define	TIM7 ((TIM_TypeDef *) TIM7_BASE)
#define	TIM12 ((TIM_TypeDef *) TIM12_BASE)
#define	TIM13 ((TIM_TypeDef *) TIM13_BASE)
#define	TIM14 ((TIM_TypeDef *) TIM14_BASE)
#define	RTC ((RTC_TypeDef *) RTC_BASE)
#define	WWDG ((WWDG_TypeDef *) WWDG_BASE)
#define	IWDG ((IWDG_TypeDef *) IWDG_BASE)
#define	SPI2 ((SPI_TypeDef *) SPI2_BASE)
#define	SPI3 ((SPI_TypeDef *) SPI3_BASE)
#define	USART2 ((USART_TypeDef *) USART2_BASE)
#define	USART3 ((USART_TypeDef *) USART3_BASE)
#define	UART4 ((USART_TypeDef *) UART4_BASE)
#define	UART5 ((USART_TypeDef *) UART5_BASE)
#define	I2C1 ((I2C_TypeDef *) I2C1_BASE)
#define	I2C2 ((I2C_TypeDef *) I2C2_BASE)
#define	CAN1 ((CAN_TypeDef *) CAN1_BASE)
#define	CAN2 ((CAN_TypeDef *) CAN2_BASE)
#define	BKP ((BKP_TypeDef *) BKP_BASE)
#define	PWR ((PWR_TypeDef *) PWR_BASE)
#define	DAC ((DAC_TypeDef *) DAC_BASE)
#define	CEC ((CEC_TypeDef *) CEC_BASE)
#define	AFIO ((AFIO_TypeDef *) AFIO_BASE)
#define	EXTI ((EXTI_TypeDef *) EXTI_BASE)
#define	GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
#define	GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
#define	GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
#define	GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
#define	GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
#define	GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
#define	GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
#define	ADC1 ((ADC_TypeDef *) ADC1_BASE)
#define	ADC2 ((ADC_TypeDef *) ADC2_BASE)
#define	TIM1 ((TIM_TypeDef *) TIM1_BASE)
#define	SPI1 ((SPI_TypeDef *) SPI1_BASE)
#define	TIM8 ((TIM_TypeDef *) TIM8_BASE)
#define	USART1 ((USART_TypeDef *) USART1_BASE)
#define	ADC3 ((ADC_TypeDef *) ADC3_BASE)
#define	TIM15 ((TIM_TypeDef *) TIM15_BASE)
#define	TIM16 ((TIM_TypeDef *) TIM16_BASE)
#define	TIM17 ((TIM_TypeDef *) TIM17_BASE)
#define	TIM9 ((TIM_TypeDef *) TIM9_BASE)
#define	TIM10 ((TIM_TypeDef *) TIM10_BASE)
#define	TIM11 ((TIM_TypeDef *) TIM11_BASE)
#define	SDIO ((SDIO_TypeDef *) SDIO_BASE)
#define	DMA1 ((DMA_TypeDef *) DMA1_BASE)
#define	DMA2 ((DMA_TypeDef *) DMA2_BASE)
#define	DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
#define	DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
#define	DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
#define	DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
#define	DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
#define	DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
#define	DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
#define	DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
#define	DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
#define	DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
#define	DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
#define	DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
#define	RCC ((RCC_TypeDef *) RCC_BASE)
#define	CRC ((CRC_TypeDef *) CRC_BASE)
#define	FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
#define	OB ((OB_TypeDef *) OB_BASE)
#define	ETH ((ETH_TypeDef *) ETH_BASE)
#define	FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
#define	FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
#define	FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
#define	FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
#define	FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
#define	DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
#define	TIM2 ((TIM_TypeDef *) TIM2_BASE)
#define	TIM3 ((TIM_TypeDef *) TIM3_BASE)
#define	TIM4 ((TIM_TypeDef *) TIM4_BASE)
#define	TIM5 ((TIM_TypeDef *) TIM5_BASE)
#define	TIM6 ((TIM_TypeDef *) TIM6_BASE)
#define	TIM7 ((TIM_TypeDef *) TIM7_BASE)
#define	TIM12 ((TIM_TypeDef *) TIM12_BASE)
#define	TIM13 ((TIM_TypeDef *) TIM13_BASE)
#define	TIM14 ((TIM_TypeDef *) TIM14_BASE)
#define	RTC ((RTC_TypeDef *) RTC_BASE)
#define	WWDG ((WWDG_TypeDef *) WWDG_BASE)
#define	IWDG ((IWDG_TypeDef *) IWDG_BASE)
#define	SPI2 ((SPI_TypeDef *) SPI2_BASE)
#define	SPI3 ((SPI_TypeDef *) SPI3_BASE)
#define	USART2 ((USART_TypeDef *) USART2_BASE)
#define	USART3 ((USART_TypeDef *) USART3_BASE)
#define	UART4 ((USART_TypeDef *) UART4_BASE)
#define	UART5 ((USART_TypeDef *) UART5_BASE)
#define	I2C1 ((I2C_TypeDef *) I2C1_BASE)
#define	I2C2 ((I2C_TypeDef *) I2C2_BASE)
#define	I2C3 ((I2C_TypeDef *) I2C3_BASE)
#define	CAN1 ((CAN_TypeDef *) CAN1_BASE)
#define	CAN2 ((CAN_TypeDef *) CAN2_BASE)
#define	PWR ((PWR_TypeDef *) PWR_BASE)
#define	DAC ((DAC_TypeDef *) DAC_BASE)
#define	TIM1 ((TIM_TypeDef *) TIM1_BASE)
#define	TIM8 ((TIM_TypeDef *) TIM8_BASE)
#define	USART1 ((USART_TypeDef *) USART1_BASE)
#define	USART6 ((USART_TypeDef *) USART6_BASE)
#define	ADC ((ADC_Common_TypeDef *) ADC_BASE)
#define	ADC1 ((ADC_TypeDef *) ADC1_BASE)
#define	ADC2 ((ADC_TypeDef *) ADC2_BASE)
#define	ADC3 ((ADC_TypeDef *) ADC3_BASE)
#define	SDIO ((SDIO_TypeDef *) SDIO_BASE)
#define	SPI1 ((SPI_TypeDef *) SPI1_BASE)
#define	SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
#define	EXTI ((EXTI_TypeDef *) EXTI_BASE)
#define	TIM9 ((TIM_TypeDef *) TIM9_BASE)
#define	TIM10 ((TIM_TypeDef *) TIM10_BASE)
#define	TIM11 ((TIM_TypeDef *) TIM11_BASE)
#define	GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
#define	GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
#define	GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
#define	GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
#define	GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
#define	GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
#define	GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
#define	GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
#define	GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
#define	CRC ((CRC_TypeDef *) CRC_BASE)
#define	RCC ((RCC_TypeDef *) RCC_BASE)
#define	FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
#define	DMA1 ((DMA_TypeDef *) DMA1_BASE)
#define	DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
#define	DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
#define	DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
#define	DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
#define	DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
#define	DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
#define	DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
#define	DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
#define	DMA2 ((DMA_TypeDef *) DMA2_BASE)
#define	DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
#define	DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
#define	DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
#define	DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
#define	DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
#define	DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
#define	DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
#define	DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
#define	ETH ((ETH_TypeDef *) ETH_BASE)
#define	DCMI ((DCMI_TypeDef *) DCMI_BASE)
#define	CRYP ((CRYP_TypeDef *) CRYP_BASE)
#define	HASH ((HASH_TypeDef *) HASH_BASE)
#define	RNG ((RNG_TypeDef *) RNG_BASE)
#define	FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
#define	FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
#define	FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
#define	FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
#define	FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
#define	DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
#define	TIM2 ((TIM_TypeDef *) TIM2_BASE)
#define	TIM3 ((TIM_TypeDef *) TIM3_BASE)
#define	TIM4 ((TIM_TypeDef *) TIM4_BASE)
#define	TIM5 ((TIM_TypeDef *) TIM5_BASE)
#define	TIM6 ((TIM_TypeDef *) TIM6_BASE)
#define	TIM7 ((TIM_TypeDef *) TIM7_BASE)
#define	TIM12 ((TIM_TypeDef *) TIM12_BASE)
#define	TIM13 ((TIM_TypeDef *) TIM13_BASE)
#define	TIM14 ((TIM_TypeDef *) TIM14_BASE)
#define	RTC ((RTC_TypeDef *) RTC_BASE)
#define	WWDG ((WWDG_TypeDef *) WWDG_BASE)
#define	IWDG ((IWDG_TypeDef *) IWDG_BASE)
#define	I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
#define	SPI2 ((SPI_TypeDef *) SPI2_BASE)
#define	SPI3 ((SPI_TypeDef *) SPI3_BASE)
#define	I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
#define	USART2 ((USART_TypeDef *) USART2_BASE)
#define	USART3 ((USART_TypeDef *) USART3_BASE)
#define	UART4 ((USART_TypeDef *) UART4_BASE)
#define	UART5 ((USART_TypeDef *) UART5_BASE)
#define	I2C1 ((I2C_TypeDef *) I2C1_BASE)
#define	I2C2 ((I2C_TypeDef *) I2C2_BASE)
#define	I2C3 ((I2C_TypeDef *) I2C3_BASE)
#define	CAN1 ((CAN_TypeDef *) CAN1_BASE)
#define	CAN2 ((CAN_TypeDef *) CAN2_BASE)
#define	PWR ((PWR_TypeDef *) PWR_BASE)
#define	DAC ((DAC_TypeDef *) DAC_BASE)
#define	TIM1 ((TIM_TypeDef *) TIM1_BASE)
#define	TIM8 ((TIM_TypeDef *) TIM8_BASE)
#define	USART1 ((USART_TypeDef *) USART1_BASE)
#define	USART6 ((USART_TypeDef *) USART6_BASE)
#define	ADC ((ADC_Common_TypeDef *) ADC_BASE)
#define	ADC1 ((ADC_TypeDef *) ADC1_BASE)
#define	ADC2 ((ADC_TypeDef *) ADC2_BASE)
#define	ADC3 ((ADC_TypeDef *) ADC3_BASE)
#define	SDIO ((SDIO_TypeDef *) SDIO_BASE)
#define	SPI1 ((SPI_TypeDef *) SPI1_BASE)
#define	SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
#define	EXTI ((EXTI_TypeDef *) EXTI_BASE)
#define	TIM9 ((TIM_TypeDef *) TIM9_BASE)
#define	TIM10 ((TIM_TypeDef *) TIM10_BASE)
#define	TIM11 ((TIM_TypeDef *) TIM11_BASE)
#define	GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
#define	GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
#define	GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
#define	GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
#define	GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
#define	GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
#define	GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
#define	GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
#define	GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
#define	CRC ((CRC_TypeDef *) CRC_BASE)
#define	RCC ((RCC_TypeDef *) RCC_BASE)
#define	FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
#define	DMA1 ((DMA_TypeDef *) DMA1_BASE)
#define	DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
#define	DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
#define	DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
#define	DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
#define	DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
#define	DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
#define	DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
#define	DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
#define	DMA2 ((DMA_TypeDef *) DMA2_BASE)
#define	DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
#define	DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
#define	DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
#define	DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
#define	DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
#define	DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
#define	DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
#define	DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
#define	ETH ((ETH_TypeDef *) ETH_BASE)
#define	DCMI ((DCMI_TypeDef *) DCMI_BASE)
#define	CRYP ((CRYP_TypeDef *) CRYP_BASE)
#define	HASH ((HASH_TypeDef *) HASH_BASE)
#define	RNG ((RNG_TypeDef *) RNG_BASE)
#define	FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
#define	FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
#define	FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
#define	FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
#define	FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
#define	DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
#define	TIM2 ((TIM_TypeDef *) TIM2_BASE)
#define	TIM3 ((TIM_TypeDef *) TIM3_BASE)
#define	TIM4 ((TIM_TypeDef *) TIM4_BASE)
#define	TIM5 ((TIM_TypeDef *) TIM5_BASE)
#define	TIM6 ((TIM_TypeDef *) TIM6_BASE)
#define	TIM7 ((TIM_TypeDef *) TIM7_BASE)
#define	LCD ((LCD_TypeDef *) LCD_BASE)
#define	RTC ((RTC_TypeDef *) RTC_BASE)
#define	WWDG ((WWDG_TypeDef *) WWDG_BASE)
#define	IWDG ((IWDG_TypeDef *) IWDG_BASE)
#define	SPI2 ((SPI_TypeDef *) SPI2_BASE)
#define	SPI3 ((SPI_TypeDef *) SPI3_BASE)
#define	USART2 ((USART_TypeDef *) USART2_BASE)
#define	USART3 ((USART_TypeDef *) USART3_BASE)
#define	UART4 ((USART_TypeDef *) UART4_BASE)
#define	UART5 ((USART_TypeDef *) UART5_BASE)
#define	I2C1 ((I2C_TypeDef *) I2C1_BASE)
#define	I2C2 ((I2C_TypeDef *) I2C2_BASE)
#define	PWR ((PWR_TypeDef *) PWR_BASE)
#define	DAC ((DAC_TypeDef *) DAC_BASE)
#define	COMP ((COMP_TypeDef *) COMP_BASE)
#define	RI ((RI_TypeDef *) RI_BASE)
#define	OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
#define	SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
#define	EXTI ((EXTI_TypeDef *) EXTI_BASE)
#define	ADC1 ((ADC_TypeDef *) ADC1_BASE)
#define	ADC ((ADC_Common_TypeDef *) ADC_BASE)
#define	SDIO ((SDIO_TypeDef *) SDIO_BASE)
#define	TIM9 ((TIM_TypeDef *) TIM9_BASE)
#define	TIM10 ((TIM_TypeDef *) TIM10_BASE)
#define	TIM11 ((TIM_TypeDef *) TIM11_BASE)
#define	SPI1 ((SPI_TypeDef *) SPI1_BASE)
#define	USART1 ((USART_TypeDef *) USART1_BASE)
#define	DMA1 ((DMA_TypeDef *) DMA1_BASE)
#define	DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
#define	DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
#define	DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
#define	DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
#define	DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
#define	DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
#define	DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
#define	DMA2 ((DMA_TypeDef *) DMA2_BASE)
#define	DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
#define	DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
#define	DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
#define	DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
#define	DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
#define	RCC ((RCC_TypeDef *) RCC_BASE)
#define	CRC ((CRC_TypeDef *) CRC_BASE)
#define	GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
#define	GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
#define	GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
#define	GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
#define	GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
#define	GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
#define	GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
#define	GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
#define	FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
#define	OB ((OB_TypeDef *) OB_BASE)
#define	AES ((AES_TypeDef *) AES_BASE)
#define	FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
#define	FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
#define	DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)

Define Documentation

#define TIM2 ((TIM_TypeDef *) TIM2_BASE)

Referenced by TIM_DeInit(), and TIM_TimeBaseInit().

#define TIM3 ((TIM_TypeDef *) TIM3_BASE)

Referenced by TIM_DeInit(), and TIM_TimeBaseInit().

#define TIM4 ((TIM_TypeDef *) TIM4_BASE)

Referenced by TIM_DeInit(), and TIM_TimeBaseInit().

#define TIM5 ((TIM_TypeDef *) TIM5_BASE)

Referenced by TIM_DeInit(), and TIM_TimeBaseInit().

#define TIM6 ((TIM_TypeDef *) TIM6_BASE)

Referenced by TIM_DeInit(), and TIM_TimeBaseInit().

#define TIM7 ((TIM_TypeDef *) TIM7_BASE)

Referenced by TIM_DeInit(), and TIM_TimeBaseInit().

#define TIM12 ((TIM_TypeDef *) TIM12_BASE)

Referenced by TIM_DeInit().

#define TIM13 ((TIM_TypeDef *) TIM13_BASE)

Referenced by TIM_DeInit().

#define TIM14 ((TIM_TypeDef *) TIM14_BASE)

Referenced by TIM_DeInit().

#define RTC ((RTC_TypeDef *) RTC_BASE)

Referenced by Stm32RtcGetClock(), Stm32RtcInit(), and Stm32RtcSetClock().

#define WWDG ((WWDG_TypeDef *) WWDG_BASE)

#define IWDG ((IWDG_TypeDef *) IWDG_BASE)

#define SPI2 ((SPI_TypeDef *) SPI2_BASE)

#define SPI3 ((SPI_TypeDef *) SPI3_BASE)

#define USART2 ((USART_TypeDef *) USART2_BASE)

Referenced by USART_DeInit().

#define USART3 ((USART_TypeDef *) USART3_BASE)

Referenced by USART_DeInit().

#define UART4 ((USART_TypeDef *) UART4_BASE)

Referenced by USART_DeInit().

#define UART5 ((USART_TypeDef *) UART5_BASE)

Referenced by USART_DeInit().

#define I2C1 ((I2C_TypeDef *) I2C1_BASE)

#define I2C2 ((I2C_TypeDef *) I2C2_BASE)

#define CAN1 ((CAN_TypeDef *) CAN1_BASE)

Referenced by CanAddFilter(), Stm32CanHw1Init(), and Stm32CanHw2Init().

#define CAN2 ((CAN_TypeDef *) CAN2_BASE)

#define BKP ((BKP_TypeDef *) BKP_BASE)

#define PWR ((PWR_TypeDef *) PWR_BASE)

Referenced by Stm32RtcInit().

#define DAC ((DAC_TypeDef *) DAC_BASE)

#define CEC ((CEC_TypeDef *) CEC_BASE)

#define AFIO ((AFIO_TypeDef *) AFIO_BASE)

Referenced by GPIO_EventOutputConfig(), GPIO_EXTILineConfig(), GPIO_PinRemapConfig(), GpioRegisterIrqHandler(), and Stm32Usart3BusSelect().

#define EXTI ((EXTI_TypeDef *) EXTI_BASE)

Referenced by GpioRegisterIrqHandler().

#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)

#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)

#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)

#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)

#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)

#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)

#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)

#define ADC1 ((ADC_TypeDef *) ADC1_BASE)

#define ADC2 ((ADC_TypeDef *) ADC2_BASE)

#define TIM1 ((TIM_TypeDef *) TIM1_BASE)

Referenced by TIM_DeInit(), TIM_OC1Init(), TIM_OC2Init(), TIM_OC3Init(), TIM_OC4Init(), and TIM_TimeBaseInit().

#define SPI1 ((SPI_TypeDef *) SPI1_BASE)

#define TIM8 ((TIM_TypeDef *) TIM8_BASE)

Referenced by TIM_DeInit(), TIM_OC1Init(), TIM_OC2Init(), TIM_OC3Init(), TIM_OC4Init(), and TIM_TimeBaseInit().

#define USART1 ((USART_TypeDef *) USART1_BASE)

Referenced by USART_DeInit().

#define ADC3 ((ADC_TypeDef *) ADC3_BASE)

#define TIM15 ((TIM_TypeDef *) TIM15_BASE)

Referenced by TIM_DeInit(), TIM_OC1Init(), and TIM_TimeBaseInit().

#define TIM16 ((TIM_TypeDef *) TIM16_BASE)

Referenced by TIM_DeInit(), TIM_OC1Init(), and TIM_TimeBaseInit().

#define TIM17 ((TIM_TypeDef *) TIM17_BASE)

Referenced by TIM_DeInit(), TIM_OC1Init(), and TIM_TimeBaseInit().

#define TIM9 ((TIM_TypeDef *) TIM9_BASE)

Referenced by TIM_DeInit().

#define TIM10 ((TIM_TypeDef *) TIM10_BASE)

Referenced by TIM_DeInit().

#define TIM11 ((TIM_TypeDef *) TIM11_BASE)

Referenced by TIM_DeInit().

#define SDIO ((SDIO_TypeDef *) SDIO_BASE)

#define DMA1 ((DMA_TypeDef *) DMA1_BASE)

Referenced by DMA_ClearFlag(), DMA_Handler_IRQ(), and DMA_Init().

#define DMA2 ((DMA_TypeDef *) DMA2_BASE)

Referenced by DMA_ClearFlag(), DMA_Handler_IRQ(), and DMA_Init().

#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)

Referenced by DMA_Register_Interrupt().

#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)

Referenced by DMA_Register_Interrupt().

#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)

Referenced by DMA_Register_Interrupt().

#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)

Referenced by DMA_Register_Interrupt().

#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)

Referenced by DMA_Register_Interrupt().

#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)

Referenced by DMA_Register_Interrupt().

#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)

Referenced by DMA_Register_Interrupt().

#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)

Referenced by DMA_Register_Interrupt().

#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)

Referenced by DMA_Register_Interrupt().

#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)

Referenced by DMA_Register_Interrupt().

#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)

Referenced by DMA_Register_Interrupt().

#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)

Referenced by DMA_Register_Interrupt().

#define RCC ((RCC_TypeDef *) RCC_BASE)

Referenced by ADCInit(), CRC_Init(), CtlHseClock(), CtlHsiClock(), CtlPllClock(), DMA_Init(), DMA_Setup(), GpioPortConfigSet(), RCC_ADCCLKConfig(), RCC_AdjustHSICalibrationValue(), RCC_AHB1PeriphClockCmd(), RCC_AHB1PeriphClockLPModeCmd(), RCC_AHB1PeriphResetCmd(), RCC_AHB2PeriphClockCmd(), RCC_AHB2PeriphClockLPModeCmd(), RCC_AHB2PeriphResetCmd(), RCC_AHB3PeriphClockCmd(), RCC_AHB3PeriphClockLPModeCmd(), RCC_AHB3PeriphResetCmd(), RCC_AHBPeriphClockCmd(), RCC_AHBPeriphClockLPModeCmd(), RCC_AHBPeriphResetCmd(), RCC_APB1PeriphClockCmd(), RCC_APB1PeriphClockLPModeCmd(), RCC_APB1PeriphResetCmd(), RCC_APB2PeriphClockCmd(), RCC_APB2PeriphClockLPModeCmd(), RCC_APB2PeriphResetCmd(), RCC_ClearFlag(), RCC_DeInit(), RCC_GetClocksFreq(), RCC_GetFlagStatus(), RCC_GetITStatus(), RCC_GetSYSCLKSource(), RCC_HCLKConfig(), RCC_HSEConfig(), RCC_MCO1Config(), RCC_MCO2Config(), RCC_MSIRangeConfig(), RCC_PCLK1Config(), RCC_PCLK2Config(), RCC_PLLConfig(), RCC_PLLI2SConfig(), RCC_RTCCLKConfig(), RCC_SYSCLKConfig(), Set_USBClock(), SetPllClockSource(), SetSysClock(), SetSysClockSource(), Stm32RtcInit(), Stm32Usart3BusSelect(), SystemCoreClockUpdate(), and SystemInit().

#define CRC ((CRC_TypeDef *) CRC_BASE)

Referenced by CRC_CalcBlockCRC(), CRC_CalcCRC(), CRC_GetCRC(), CRC_GetIDRegister(), CRC_Init(), CRC_ResetDR(), and CRC_SetIDRegister().

#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)

Referenced by FLASH_ClearFlag(), FLASH_EraseAllBank1Pages(), FLASH_EraseAllBank2Pages(), FLASH_EraseAllPages(), FLASH_GetStatus(), FLASH_HalfCycleAccessCmd(), FLASH_ITConfig(), FLASH_Lock(), FLASH_PrefetchBufferCmd(), FLASH_SetLatency(), FLASH_Unlock(), and SetSysClock().

#define OB ((OB_TypeDef *) OB_BASE)

Referenced by FLASH_EraseAllPages().

#define ETH ((ETH_TypeDef *) ETH_BASE)

Referenced by EmacRxThread().

#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)

#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)

#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)

#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)

#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)

#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)

#define TIM2 ((TIM_TypeDef *) TIM2_BASE)

#define TIM3 ((TIM_TypeDef *) TIM3_BASE)

#define TIM4 ((TIM_TypeDef *) TIM4_BASE)

#define TIM5 ((TIM_TypeDef *) TIM5_BASE)

#define TIM6 ((TIM_TypeDef *) TIM6_BASE)

#define TIM7 ((TIM_TypeDef *) TIM7_BASE)

#define TIM12 ((TIM_TypeDef *) TIM12_BASE)

#define TIM13 ((TIM_TypeDef *) TIM13_BASE)

#define TIM14 ((TIM_TypeDef *) TIM14_BASE)

#define RTC ((RTC_TypeDef *) RTC_BASE)

#define WWDG ((WWDG_TypeDef *) WWDG_BASE)

#define IWDG ((IWDG_TypeDef *) IWDG_BASE)

#define SPI2 ((SPI_TypeDef *) SPI2_BASE)

#define SPI3 ((SPI_TypeDef *) SPI3_BASE)

#define USART2 ((USART_TypeDef *) USART2_BASE)

#define USART3 ((USART_TypeDef *) USART3_BASE)

#define UART4 ((USART_TypeDef *) UART4_BASE)

#define UART5 ((USART_TypeDef *) UART5_BASE)

#define I2C1 ((I2C_TypeDef *) I2C1_BASE)

#define I2C2 ((I2C_TypeDef *) I2C2_BASE)

#define I2C3 ((I2C_TypeDef *) I2C3_BASE)

#define CAN1 ((CAN_TypeDef *) CAN1_BASE)

#define CAN2 ((CAN_TypeDef *) CAN2_BASE)

#define PWR ((PWR_TypeDef *) PWR_BASE)

#define DAC ((DAC_TypeDef *) DAC_BASE)

#define TIM1 ((TIM_TypeDef *) TIM1_BASE)

#define TIM8 ((TIM_TypeDef *) TIM8_BASE)

#define USART1 ((USART_TypeDef *) USART1_BASE)

#define USART6 ((USART_TypeDef *) USART6_BASE)

#define ADC ((ADC_Common_TypeDef *) ADC_BASE)

#define ADC1 ((ADC_TypeDef *) ADC1_BASE)

#define ADC2 ((ADC_TypeDef *) ADC2_BASE)

#define ADC3 ((ADC_TypeDef *) ADC3_BASE)

#define SDIO ((SDIO_TypeDef *) SDIO_BASE)

#define SPI1 ((SPI_TypeDef *) SPI1_BASE)

#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)

#define EXTI ((EXTI_TypeDef *) EXTI_BASE)

#define TIM9 ((TIM_TypeDef *) TIM9_BASE)

#define TIM10 ((TIM_TypeDef *) TIM10_BASE)

#define TIM11 ((TIM_TypeDef *) TIM11_BASE)

#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)

#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)

#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)

#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)

#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)

#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)

#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)

#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)

#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)

#define CRC ((CRC_TypeDef *) CRC_BASE)

#define RCC ((RCC_TypeDef *) RCC_BASE)

#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)

#define DMA1 ((DMA_TypeDef *) DMA1_BASE)

#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)

#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)

#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)

#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)

#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)

#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)

#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)

#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)

#define DMA2 ((DMA_TypeDef *) DMA2_BASE)

#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)

#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)

#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)

#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)

#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)

#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)

#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)

#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)

#define ETH ((ETH_TypeDef *) ETH_BASE)

#define DCMI ((DCMI_TypeDef *) DCMI_BASE)

#define CRYP ((CRYP_TypeDef *) CRYP_BASE)

#define HASH ((HASH_TypeDef *) HASH_BASE)

#define RNG ((RNG_TypeDef *) RNG_BASE)

#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)

#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)

#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)

#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)

#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)

#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)

#define TIM2 ((TIM_TypeDef *) TIM2_BASE)

#define TIM3 ((TIM_TypeDef *) TIM3_BASE)

#define TIM4 ((TIM_TypeDef *) TIM4_BASE)

#define TIM5 ((TIM_TypeDef *) TIM5_BASE)

#define TIM6 ((TIM_TypeDef *) TIM6_BASE)

#define TIM7 ((TIM_TypeDef *) TIM7_BASE)

#define TIM12 ((TIM_TypeDef *) TIM12_BASE)

#define TIM13 ((TIM_TypeDef *) TIM13_BASE)

#define TIM14 ((TIM_TypeDef *) TIM14_BASE)

#define RTC ((RTC_TypeDef *) RTC_BASE)

#define WWDG ((WWDG_TypeDef *) WWDG_BASE)

#define IWDG ((IWDG_TypeDef *) IWDG_BASE)

#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)

#define SPI2 ((SPI_TypeDef *) SPI2_BASE)

#define SPI3 ((SPI_TypeDef *) SPI3_BASE)

#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)