A/D Converter. More...

Collaboration diagram for ADC:

Defines
#define	AT91_ADC_INITIAL_MODE SINGLE_CONVERSION
#define	AT91_ADC_INITIAL_PRESCALE 55
#define	AT91_ADC_BUF_SIZE 16
#define	_adc_buf_head AT91_ADC_BUF_SIZE
#define	_adc_buf_tail AT91_ADC_BUF_SIZE+1
Functions
int	ADCBufRead (uint16_t channel, uint16_t *read)
	Reads data from the adc buffer.
void	ADCSetMode (TADCMode mode)
	Sets the data aquisition mode for the adc.
void	ADCEnableChannel (TADCChannel channel)
	Enable a channel used to sample when conversion started.
void	ADCDisableChannel (TADCChannel channel)
	Disable a channel.
void	ADCSetPrescale (uint32_t prescale)
	Set the prescaler for the adc.
void	ADCStartConversion (void)
	Start conversion.
void	ADCInit (void)
	Initialize the adc to the configured default values and enable interrupt.
Variables
uint16_t **	ADC_Buffer = NULL
ADC Control Register
#define	ADC_CR_OFF 0x00000000
	Control register offset.
#define	ADC_CR (ADC_BASE + ADC_CR_OFF)
	Control register address.
#define	ADC_SWRST 0x00000001
	Software reset.
#define	ADC_START 0x00000002
	Start a conversion.
ADC Mode Register
#define	ADC_MR_OFF 0x00000004
	Mode register offset.
#define	ADC_MR (ADC_BASE + ADC_MR_OFF)
	Mode register address.
#define	ADC_TRGEN 0x00000001
	Hardware trigger enable.
#define	ADC_TRGSEL 0x0000000E
	Trigger select mask.
#define	ADC_TRGSEL_TIOA0 0x00000000
	Trigger select timer counter 0 output.
#define	ADC_TRGSEL_TIOA1 0x00000002
	Trigger select timer counter 1 output.
#define	ADC_TRGSEL_TIOA2 0x00000004
	Trigger select timer counter 2 output.
#define	ADC_TRGSEL_EXT 0x0000000C
	Single trigger.
#define	ADC_LOWRES 0x00000010
	10bit / 8bit selection
#define	ADC_SLEEP 0x00000020
	Enter sleep mode.
#define	ADC_PRESCAL 0x00003F00
	Prescaler mask.
#define	ADC_PRESCAL_LSB 8
	Prescaler LSB.
#define	ADC_STARTUP 0x001F0000
	Startup time mask.
#define	ADC_STARTUP_LSB 16
	Startup time LSB.
#define	ADC_SHTIM 0x0F000000
	Sample hold time mask.
#define	ADC_SHTIM_LSB 24
	Sample hold time LSB.
ADC Channel Enable Register
#define	ADC_CHER_OFF 0x00000010
	Channel enable register offset.
#define	ADC_CHER (ADC_BASE + ADC_CHER_OFF)
	Channel enable register address.
#define	ADC_CH(x) ((unsigned long)BV(x))
	macro to access channel by numer
#define	ADC_CH0 0x00000001
	ADC Channel 0.
#define	ADC_CH1 0x00000002
	ADC Channel 1.
#define	ADC_CH2 0x00000004
	ADC Channel 2.
#define	ADC_CH3 0x00000008
	ADC Channel 3.
#define	ADC_CH4 0x00000010
	ADC Channel 4.
#define	ADC_CH5 0x00000020
	ADC Channel 5.
#define	ADC_CH6 0x00000040
	ADC Channel 6.
#define	ADC_CH7 0x00000080
	ADC Channel 7.
ADC Channel Disable Register
#define	ADC_CHDR_OFF 0x00000014
	Channel disable register offset.
#define	ADC_CHDR (ADC_BASE + ADC_CHDR_OFF)
	Channel disable register address.
ADC Channel Status Register
#define	ADC_CHSR_OFF 0x00000018
	Channel status register offset.
#define	ADC_CHSR (ADC_BASE + ADC_CHSR_OFF)
	Channel status register address.
ADC Status Register
#define	ADC_SR_OFF 0x0000001C
	ADC status register offset.
#define	ADC_SR (ADC_BASE + ADC_SR_OFF)
	ADC status register address.
#define	ADC_EOC(x) ((unsigned long)BV(x))
	Macro to access EOC flag by channel number.
#define	ADC_EOC0 0x00000001
	End of conversion channel 0.
#define	ADC_EOC1 0x00000002
	End of conversion channel 1.
#define	ADC_EOC2 0x00000004
	End of conversion channel 2.
#define	ADC_EOC3 0x00000008
	End of conversion channel 3.
#define	ADC_EOC4 0x00000010
	End of conversion channel 4.
#define	ADC_EOC5 0x00000020
	End of conversion channel 5.
#define	ADC_EOC6 0x00000040
	End of conversion channel 6.
#define	ADC_EOC7 0x00000080
	End of conversion channel 7.
#define	ADC_OVRE(x) ((unsigned long)BV(x+8))
	Macto to acces overrun error flag by channel number.
#define	ADC_OVRE0 0x00000100
	Overrun error flag channel 0.
#define	ADC_OVRE1 0x00000200
	Overrun error flag channel 1.
#define	ADC_OVRE2 0x00000400
	Overrun error flag channel 2.
#define	ADC_OVRE3 0x00000800
	Overrun error flag channel 3.
#define	ADC_OVRE4 0x00001000
	Overrun error flag channel 4.
#define	ADC_OVRE5 0x00002000
	Overrun error flag channel 5.
#define	ADC_OVRE6 0x00004000
	Overrun error flag channel 6.
#define	ADC_OVRE7 0x00008000
	Overrun error flag channel 7.
#define	ADC_DRDY 0x00010000
	Data ready flag.
#define	ADC_GOVRE 0x00020000
	General data overrun error flag.
#define	ADC_ENDRX 0x00040000
	End of rx buffer flag.
#define	ADC_RXBUF 0x00080000
	Rx buffer full flag.
ADC Last Converted Data Register
#define	ADC_LCDR_OFF 0x00000020
	Last converted data register offset.
#define	ADC_LCDR (ADC_BASE + ADC_LCDR_OFF)
	Last converted data register.
#define	ADC_LCDR_MASK 0x000003FF
	Last converted data mask (10bit)
ADC Interrupt Enable Register
#define	ADC_IER_OFF 0x00000024
	Interrupt enable register offset.
#define	ADC_IER (ADC_BASE + ADC_IER_OFF)
	Last converted data register.
ADC Interrupt Disable Register
#define	ADC_IDR_OFF 0x00000028
	Interrupt disable register offset.
#define	ADC_IDR (ADC_BASE + ADC_IDR_OFF)
	Interrupt disable register.
ADC Interrupt Mask Register
#define	ADC_IMR_OFF 0x0000002C
	Interrupt mask register offset.
#define	ADC_IMR (ADC_BASE + ADC_IMR_OFF)
	Interrupt mask register.
ADC Channel Data Register
#define	ADC_CDR_OFF 0x00000030
	Channel data register offset.
#define	ADC_CDR(x) (ADC_BASE + ADC_CDR_OFF + ((x) << 2))
	Channel data register.
#define	ADC_CDR_MASK 0x000003FF
	Channel data mask (10bit)

Detailed Description

A/D Converter.

Define Documentation

#define ADC_CR_OFF 0x00000000

Control register offset.

#define ADC_CR (ADC_BASE + ADC_CR_OFF)

Control register address.

Referenced by ADCInit(), and ADCStartConversion().

#define ADC_SWRST 0x00000001

Software reset.

Referenced by ADCInit().

#define ADC_START 0x00000002

Start a conversion.

Referenced by ADCStartConversion().

#define ADC_MR_OFF 0x00000004

Mode register offset.

#define ADC_MR (ADC_BASE + ADC_MR_OFF)

Mode register address.

Referenced by ADCSetMode(), and ADCSetPrescale().

#define ADC_TRGEN 0x00000001

Hardware trigger enable.

Referenced by ADCSetMode().

#define ADC_TRGSEL 0x0000000E

Trigger select mask.

Referenced by ADCSetMode().

#define ADC_TRGSEL_TIOA0 0x00000000

Trigger select timer counter 0 output.

Referenced by ADCSetMode().

#define ADC_TRGSEL_TIOA1 0x00000002

Trigger select timer counter 1 output.

Referenced by ADCSetMode().

#define ADC_TRGSEL_TIOA2 0x00000004

Trigger select timer counter 2 output.

Referenced by ADCSetMode().

#define ADC_TRGSEL_EXT 0x0000000C

Single trigger.

Referenced by ADCSetMode().

#define ADC_LOWRES 0x00000010

10bit / 8bit selection

#define ADC_SLEEP 0x00000020

Enter sleep mode.

Referenced by ADCSetMode().

#define ADC_PRESCAL 0x00003F00

Prescaler mask.

Referenced by ADCSetPrescale().

#define ADC_PRESCAL_LSB 8

Prescaler LSB.

Referenced by ADCSetPrescale().

#define ADC_STARTUP 0x001F0000

Startup time mask.

Referenced by ADCSetPrescale().

#define ADC_STARTUP_LSB 16

Startup time LSB.

#define ADC_SHTIM 0x0F000000

Sample hold time mask.

Referenced by ADCSetPrescale().

#define ADC_SHTIM_LSB 24

Sample hold time LSB.

#define ADC_CHER_OFF 0x00000010

Channel enable register offset.

#define ADC_CHER (ADC_BASE + ADC_CHER_OFF)

Channel enable register address.

Referenced by ADCDisableChannel(), and ADCEnableChannel().

#define ADC_CH ( x ) ((unsigned long)BV(x))

macro to access channel by numer

#define ADC_CH0 0x00000001

ADC Channel 0.

Referenced by ADCInit().

#define ADC_CH1 0x00000002

ADC Channel 1.

Referenced by ADCInit().

#define ADC_CH2 0x00000004

ADC Channel 2.

Referenced by ADCInit().

#define ADC_CH3 0x00000008

ADC Channel 3.

Referenced by ADCInit().

#define ADC_CH4 0x00000010

ADC Channel 4.

Referenced by ADCInit().

#define ADC_CH5 0x00000020

ADC Channel 5.

Referenced by ADCInit().

#define ADC_CH6 0x00000040

ADC Channel 6.

Referenced by ADCInit().

#define ADC_CH7 0x00000080

ADC Channel 7.

Referenced by ADCInit().

#define ADC_CHDR_OFF 0x00000014

Channel disable register offset.

#define ADC_CHDR (ADC_BASE + ADC_CHDR_OFF)

Channel disable register address.

Referenced by ADCDisableChannel(), and ADCInit().

#define ADC_CHSR_OFF 0x00000018

Channel status register offset.

#define ADC_CHSR (ADC_BASE + ADC_CHSR_OFF)

Channel status register address.

Referenced by ADCEnableChannel().

#define ADC_SR_OFF 0x0000001C

ADC status register offset.

#define ADC_SR (ADC_BASE + ADC_SR_OFF)

ADC status register address.

#define ADC_EOC ( x ) ((unsigned long)BV(x))

Macro to access EOC flag by channel number.

#define ADC_EOC0 0x00000001

End of conversion channel 0.

#define ADC_EOC1 0x00000002

End of conversion channel 1.

#define ADC_EOC2 0x00000004

End of conversion channel 2.

#define ADC_EOC3 0x00000008

End of conversion channel 3.

#define ADC_EOC4 0x00000010

End of conversion channel 4.

#define ADC_EOC5 0x00000020

End of conversion channel 5.

#define ADC_EOC6 0x00000040

End of conversion channel 6.

#define ADC_EOC7 0x00000080

End of conversion channel 7.

#define ADC_OVRE ( x ) ((unsigned long)BV(x+8))

Macto to acces overrun error flag by channel number.

#define ADC_OVRE0 0x00000100

Overrun error flag channel 0.

#define ADC_OVRE1 0x00000200

Overrun error flag channel 1.

#define ADC_OVRE2 0x00000400

Overrun error flag channel 2.

#define ADC_OVRE3 0x00000800

Overrun error flag channel 3.

#define ADC_OVRE4 0x00001000

Overrun error flag channel 4.

#define ADC_OVRE5 0x00002000

Overrun error flag channel 5.

#define ADC_OVRE6 0x00004000

Overrun error flag channel 6.

#define ADC_OVRE7 0x00008000

Overrun error flag channel 7.

#define ADC_DRDY 0x00010000

Data ready flag.

#define ADC_GOVRE 0x00020000

General data overrun error flag.

#define ADC_ENDRX 0x00040000

End of rx buffer flag.

#define ADC_RXBUF 0x00080000

Rx buffer full flag.

#define ADC_LCDR_OFF 0x00000020

Last converted data register offset.

#define ADC_LCDR (ADC_BASE + ADC_LCDR_OFF)

Last converted data register.

#define ADC_LCDR_MASK 0x000003FF

Last converted data mask (10bit)

#define ADC_IER_OFF 0x00000024

Interrupt enable register offset.

#define ADC_IER (ADC_BASE + ADC_IER_OFF)

Last converted data register.

Referenced by ADCEnableChannel().

#define ADC_IDR_OFF 0x00000028

Interrupt disable register offset.

#define ADC_IDR (ADC_BASE + ADC_IDR_OFF)

Interrupt disable register.

Referenced by ADCDisableChannel(), and ADCEnableChannel().

#define ADC_IMR_OFF 0x0000002C

Interrupt mask register offset.

#define ADC_IMR (ADC_BASE + ADC_IMR_OFF)

Interrupt mask register.

#define ADC_CDR_OFF 0x00000030

Channel data register offset.

#define ADC_CDR ( x ) (ADC_BASE + ADC_CDR_OFF + ((x) << 2))

Channel data register.

#define ADC_CDR_MASK 0x000003FF

Channel data mask (10bit)

#define AT91_ADC_INITIAL_MODE SINGLE_CONVERSION

Referenced by ADCInit().

#define AT91_ADC_INITIAL_PRESCALE 55

Referenced by ADCInit().

#define AT91_ADC_BUF_SIZE 16

Referenced by ADCBufRead(), and ADCInit().

#define _adc_buf_head AT91_ADC_BUF_SIZE

Referenced by ADCBufRead(), and ADCInit().

#define _adc_buf_tail AT91_ADC_BUF_SIZE+1

Referenced by ADCBufRead(), and ADCInit().

Function Documentation

int ADCBufRead	(	uint16_t	channel,
		uint16_t *	read
	)

Reads data from the adc buffer.

Parameters:

channel	Specifies the channel to read data from
read	Variable to store the data in

Returns:: 0: data read succesfully, 1: no data available

References _adc_buf_head, _adc_buf_tail, ADC_Buffer, and AT91_ADC_BUF_SIZE.

void ADCSetMode ( TADCMode mode )

Sets the data aquisition mode for the adc.

Parameters:

mode	Mode to set

References ADC_MR, ADC_OFF, ADC_SLEEP, ADC_TRGEN, ADC_TRGSEL, ADC_TRGSEL_EXT, ADC_TRGSEL_TIOA0, ADC_TRGSEL_TIOA1, ADC_TRGSEL_TIOA2, FREE_RUNNING_EXT, FREE_RUNNING_T0, FREE_RUNNING_T1, FREE_RUNNING_T2, inr, outr, and SINGLE_CONVERSION.

void ADCEnableChannel ( TADCChannel channel )

Enable a channel used to sample when conversion started.

Parameters:

channel Specifies the channel to enable

References _BV, ADC_CHER, ADC_CHSR, ADC_IDR, ADC_IER, inr, max, and outr.

void ADCDisableChannel ( TADCChannel channel )

Disable a channel.

Parameters:

channel Specifies the channel to disable

References _BV, ADC_CHDR, ADC_IDR, and outr.

void ADCSetPrescale ( uint32_t prescale )

Set the prescaler for the adc.

Parameters:

prescale Prescaler value 0-128

References ADC_MR, ADC_PRESCAL, ADC_PRESCAL_LSB, ADC_SHTIM, ADC_STARTUP, inr, and outr.

void ADCStartConversion ( void )

Start conversion.

References ADC_CR, ADC_START, and outr.

void ADCInit ( void )

Initialize the adc to the configured default values and enable interrupt.

References _adc_buf_head, _adc_buf_tail, _BV, ADC_Buffer, ADC_CH0, ADC_CH1, ADC_CH2, ADC_CH3, ADC_CH4, ADC_CH5, ADC_CH6, ADC_CH7, ADC_CHDR, ADC_CR, ADC_ID, ADC_MAX_CHANNEL, ADC_SWRST, ADCSetMode(), ADCSetPrescale(), AT91_ADC_BUF_SIZE, AT91_ADC_INITIAL_MODE, AT91_ADC_INITIAL_PRESCALE, NULL, NutHeapAlloc, NutIrqEnable(), NutRegisterIrqHandler(), outr, PMC_PCER, and sig_ADC.

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Variable Documentation

uint16_t** ADC_Buffer = NULL

Referenced by ADCBufRead(), and ADCInit().

Defines

Functions

Variables

ADC Control Register

ADC Mode Register

ADC Channel Enable Register

ADC Channel Disable Register

ADC Channel Status Register

ADC Status Register

ADC Last Converted Data Register

ADC Interrupt Enable Register

ADC Interrupt Disable Register

ADC Interrupt Mask Register

ADC Channel Data Register

Detailed Description

Define Documentation

Function Documentation

Variable Documentation