AT91 Watchdog Registers

Watchdog timer registers. More...

Collaboration diagram for AT91 Watchdog Registers:

Watch Dog Control Register
#define	WDT_CR_OFF   0x00000000
	Watchdog control register offset.
#define	WDT_CR   (WDT_BASE + WDT_CR_OFF)
	Watchdog control register address.
#define	WDT_WDRSTT   0x00000001
	Watchdog restart.
#define	WDT_KEY   0xA5000000
	Watchdog password.
Watch Dog Mode Register
#define	WDT_MR_OFF   0x00000004
	Mode register offset.
#define	WDT_MR   (WDT_BASE + WDT_MR_OFF)
	Mode register address.
#define	WDT_WDV   0x00000FFF
	Counter value mask.
#define	WDT_WDV_LSB   0
	Counter value LSB.
#define	WDT_WDFIEN   0x00001000
	Fault interrupt enable.
#define	WDT_WDRSTEN   0x00002000
	Reset enable.
#define	WDT_WDRPROC   0x00004000
	Eset processor enable.
#define	WDT_WDDIS   0x00008000
	Watchdog disable.
#define	WDT_WDD   0x0FFF0000
	Delta value mask.
#define	WDT_WDD_LSB   16
	Delta value LSB.
#define	WDT_WDDBGHLT   0x10000000
	Watchdog debug halt.
#define	WDT_WDIDLEHLT   0x20000000
	Watchdog idle halt.
Watch Dog Status Register
#define	WDT_SR_OFF   0x00000008
	Status register offset.
#define	WDT_SR   (WDT_BASE + WDT_SR_OFF)
	Status register address.
#define	WDT_WDUNF   0x00000001
	Watchdog underflow.
#define	WDT_WDERR   0x00000002
	Watchdog error.

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Detailed Description

Watchdog timer registers.

The Watch Dog is used to prevent system lock-up if the software becomes trapped in a deadlock. It can generate an internal reset or interrupt.

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Define Documentation

#define WDT_CR_OFF   0x00000000

Watchdog control register offset.

#define WDT_CR   (WDT_BASE + WDT_CR_OFF)

Watchdog control register address.

Referenced by At91WatchDogRestart().

#define WDT_WDRSTT   0x00000001

Watchdog restart.

Referenced by At91WatchDogRestart().

#define WDT_KEY   0xA5000000

Watchdog password.

Referenced by At91WatchDogRestart().

#define WDT_MR_OFF   0x00000004

Mode register offset.

#define WDT_MR   (WDT_BASE + WDT_MR_OFF)

Mode register address.

Referenced by __init2(), At91WatchDogDisable(), and At91WatchDogStart().

#define WDT_WDV   0x00000FFF

Counter value mask.

#define WDT_WDV_LSB   0

Counter value LSB.

#define WDT_WDFIEN   0x00001000

Fault interrupt enable.

#define WDT_WDRSTEN   0x00002000

Reset enable.

Referenced by At91WatchDogStart().

#define WDT_WDRPROC   0x00004000

Eset processor enable.

#define WDT_WDDIS   0x00008000

Watchdog disable.

Referenced by __init2(), and At91WatchDogDisable().

#define WDT_WDD   0x0FFF0000

Delta value mask.

#define WDT_WDD_LSB   16

Delta value LSB.

#define WDT_WDDBGHLT   0x10000000

Watchdog debug halt.

Referenced by At91WatchDogStart().

#define WDT_WDIDLEHLT   0x20000000

Watchdog idle halt.

Referenced by At91WatchDogStart().

#define WDT_SR_OFF   0x00000008

Status register offset.

#define WDT_SR   (WDT_BASE + WDT_SR_OFF)

Status register address.

#define WDT_WDUNF   0x00000001

Watchdog underflow.

#define WDT_WDERR   0x00000002

Watchdog error.