Go to the source code of this file.
Defines |
#define | XTAL (12000000UL) |
#define | OSC_CLK ( XTAL) |
#define | RTC_CLK ( 32000UL) |
#define | IRC_OSC ( 4000000UL) |
#define | CLKPWR_PCLKSEL_WDT 0 |
#define | CLKPWR_PCLKSEL_TIMER0 2 |
#define | CLKPWR_PCLKSEL_TIMER1 4 |
#define | CLKPWR_PCLKSEL_UART0 6 |
#define | CLKPWR_PCLKSEL_UART1 8 |
#define | CLKPWR_PCLKSEL_PWM1 12 |
#define | CLKPWR_PCLKSEL_I2C0 14 |
#define | CLKPWR_PCLKSEL_SPI 16 |
#define | CLKPWR_PCLKSEL_SSP1 20 |
#define | CLKPWR_PCLKSEL_DAC 22 |
#define | CLKPWR_PCLKSEL_ADC 24 |
#define | CLKPWR_PCLKSEL_CAN1 26 |
#define | CLKPWR_PCLKSEL_CAN2 28 |
#define | CLKPWR_PCLKSEL_ACF 30 |
#define | CLKPWR_PCLKSEL_QEI 32 |
#define | CLKPWR_PCLKSEL_PCB 36 |
#define | CLKPWR_PCLKSEL_I2C1 38 |
#define | CLKPWR_PCLKSEL_SSP0 42 |
#define | CLKPWR_PCLKSEL_TIMER2 44 |
#define | CLKPWR_PCLKSEL_TIMER3 46 |
#define | CLKPWR_PCLKSEL_UART2 48 |
#define | CLKPWR_PCLKSEL_UART3 50 |
#define | CLKPWR_PCLKSEL_I2C2 52 |
#define | CLKPWR_PCLKSEL_I2S 54 |
#define | CLKPWR_PCLKSEL_RIT 58 |
#define | CLKPWR_PCLKSEL_SYSCON 60 |
#define | CLKPWR_PCLKSEL_MC 62 |
#define | CLKPWR_PCLKSEL_CCLK_DIV_4 0 |
#define | CLKPWR_PCLKSEL_CCLK_DIV_1 1 |
#define | CLKPWR_PCLKSEL_CCLK_DIV_2 2 |
#define | CLKPWR_PCONP_PCTIM0 1 |
#define | CLKPWR_PCONP_PCTIM1 2 |
#define | CLKPWR_PCONP_PCUART0 3 |
#define | CLKPWR_PCONP_PCUART1 4 |
#define | CLKPWR_PCONP_PCPWM1 6 |
#define | CLKPWR_PCONP_PCI2C0 7 |
#define | CLKPWR_PCONP_PCSPI 8 |
#define | CLKPWR_PCONP_PCRTC 9 |
#define | CLKPWR_PCONP_PCSSP1 10 |
#define | CLKPWR_PCONP_PCAD 12 |
#define | CLKPWR_PCONP_PCAN1 13 |
#define | CLKPWR_PCONP_PCAN2 14 |
#define | CLKPWR_PCONP_PCGPIO 15 |
#define | CLKPWR_PCONP_PCRIT 16 |
#define | CLKPWR_PCONP_PCMC 17 |
#define | CLKPWR_PCONP_PCQEI 18 |
#define | CLKPWR_PCONP_PCI2C1 19 |
#define | CLKPWR_PCONP_PCSSP0 21 |
#define | CLKPWR_PCONP_PCTIM2 22 |
#define | CLKPWR_PCONP_PCTIM3 23 |
#define | CLKPWR_PCONP_PCUART2 24 |
#define | CLKPWR_PCONP_PCUART3 25 |
#define | CLKPWR_PCONP_PCI2C2 26 |
#define | CLKPWR_PCONP_PCI2S 27 |
#define | CLKPWR_PCONP_PCGPDMA 29 |
#define | CLKPWR_PCONP_PCENET 30 |
#define | CLKPWR_PCONP_PCUSB 31 |
#define | SysCtlPeripheralClkEnable(bit) CM3BBREG(LPC_SC_BASE, LPC_SC_TypeDef, PCONP, (bit)) = 1 |
#define | SysCtlPeripheralClkDisable(bit) CM3BBREG(LPC_SC_BASE, LPC_SC_TypeDef, PCONP, (bit)) = 0 |
#define | SysCtlPeripheralClkGet(bit) CM3BBREG(LPC_SC_BASE, LPC_SC_TypeDef, PCONP, (bit)) |
#define | NS_2_CLKS(clock, ns) (((((((clock) >> 4)*69) >> 20)*(ns))>>12)+1) |
Functions |
uint32_t | SysCtlClockGet (void) |
| requests System clock frequency
|
int | SetSysClock (void) |
| Update SystemCoreClock according to Clock Register Values.
|
uint32_t | Lpc17xx_ClockGet (int idx) |
| requests frequency of the given clock
|
Define Documentation
#define XTAL (12000000UL) |
#define RTC_CLK ( 32000UL) |
#define IRC_OSC ( 4000000UL) |
#define CLKPWR_PCLKSEL_WDT 0 |
#define CLKPWR_PCLKSEL_TIMER0 2 |
#define CLKPWR_PCLKSEL_TIMER1 4 |
#define CLKPWR_PCLKSEL_UART0 6 |
#define CLKPWR_PCLKSEL_UART1 8 |
#define CLKPWR_PCLKSEL_PWM1 12 |
#define CLKPWR_PCLKSEL_I2C0 14 |
#define CLKPWR_PCLKSEL_SPI 16 |
#define CLKPWR_PCLKSEL_SSP1 20 |
#define CLKPWR_PCLKSEL_DAC 22 |
#define CLKPWR_PCLKSEL_ADC 24 |
#define CLKPWR_PCLKSEL_CAN1 26 |
#define CLKPWR_PCLKSEL_CAN2 28 |
#define CLKPWR_PCLKSEL_ACF 30 |
#define CLKPWR_PCLKSEL_QEI 32 |
#define CLKPWR_PCLKSEL_PCB 36 |
#define CLKPWR_PCLKSEL_I2C1 38 |
#define CLKPWR_PCLKSEL_SSP0 42 |
#define CLKPWR_PCLKSEL_TIMER2 44 |
#define CLKPWR_PCLKSEL_TIMER3 46 |
#define CLKPWR_PCLKSEL_UART2 48 |
#define CLKPWR_PCLKSEL_UART3 50 |
#define CLKPWR_PCLKSEL_I2C2 52 |
#define CLKPWR_PCLKSEL_I2S 54 |
#define CLKPWR_PCLKSEL_RIT 58 |
#define CLKPWR_PCLKSEL_SYSCON 60 |
#define CLKPWR_PCLKSEL_MC 62 |
#define CLKPWR_PCLKSEL_CCLK_DIV_4 0 |
#define CLKPWR_PCLKSEL_CCLK_DIV_1 1 |
#define CLKPWR_PCLKSEL_CCLK_DIV_2 2 |
#define CLKPWR_PCONP_PCTIM0 1 |
#define CLKPWR_PCONP_PCTIM1 2 |
#define CLKPWR_PCONP_PCUART0 3 |
#define CLKPWR_PCONP_PCUART1 4 |
#define CLKPWR_PCONP_PCPWM1 6 |
#define CLKPWR_PCONP_PCI2C0 7 |
#define CLKPWR_PCONP_PCSPI 8 |
#define CLKPWR_PCONP_PCRTC 9 |
#define CLKPWR_PCONP_PCSSP1 10 |
#define CLKPWR_PCONP_PCAD 12 |
#define CLKPWR_PCONP_PCAN1 13 |
#define CLKPWR_PCONP_PCAN2 14 |
#define CLKPWR_PCONP_PCGPIO 15 |
#define CLKPWR_PCONP_PCRIT 16 |
#define CLKPWR_PCONP_PCMC 17 |
#define CLKPWR_PCONP_PCQEI 18 |
#define CLKPWR_PCONP_PCI2C1 19 |
#define CLKPWR_PCONP_PCSSP0 21 |
#define CLKPWR_PCONP_PCTIM2 22 |
#define CLKPWR_PCONP_PCTIM3 23 |
#define CLKPWR_PCONP_PCUART2 24 |
#define CLKPWR_PCONP_PCUART3 25 |
#define CLKPWR_PCONP_PCI2C2 26 |
#define CLKPWR_PCONP_PCI2S 27 |
#define CLKPWR_PCONP_PCGPDMA 29 |
#define CLKPWR_PCONP_PCENET 30 |
#define CLKPWR_PCONP_PCUSB 31 |
#define SysCtlPeripheralClkEnable |
( |
|
bit | ) |
CM3BBREG(LPC_SC_BASE, LPC_SC_TypeDef, PCONP, (bit)) = 1 |
#define SysCtlPeripheralClkDisable |
( |
|
bit | ) |
CM3BBREG(LPC_SC_BASE, LPC_SC_TypeDef, PCONP, (bit)) = 0 |
#define SysCtlPeripheralClkGet |
( |
|
bit | ) |
CM3BBREG(LPC_SC_BASE, LPC_SC_TypeDef, PCONP, (bit)) |
#define NS_2_CLKS |
( |
|
clock, |
|
|
|
ns |
|
) |
| (((((((clock) >> 4)*69) >> 20)*(ns))>>12)+1) |
Function Documentation
requests System clock frequency
- Note:
- This function should be used only after reset.
- Parameters:
-
- Return values:
-
Referenced by NutRegisterTimer().
Update SystemCoreClock according to Clock Register Values.
This function reads out the CPUs clock and PLL registers and assembles the actual clock speed values into the SystemCoreClock global variable. Sets System clock frequency to the configured defaults.
- Note:
- This function should be used only after reset.
- Parameters:
-
- Return values:
-
None | Update SystemCoreClock according to Clock Register Values. |
- Note:
- This function should be used only after reset.
- Parameters:
-
- Return values:
-
None | Update SystemCoreClock according to Clock Register Values. |
Enable HSI/HSE clock and setup HCLK, PCLK2 and PCLK1 prescalers.
- Parameters:
-
- Returns:
- 0 on success, -1 on fault of HSE.
Referenced by SystemInit().