Go to the documentation of this file.00001 #ifndef _ARCH_CM3_NXP_MACH_LPC_SC_H_
00002 #define _ARCH_CM3_NXP_MACH_LPC_SC_H_
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00052 #define SC_EXTINT_OFF 0x00000140
00053 #define SC_EXTINT (LPC_SC_BASE + SC_EXTINT_OFF)
00054 #define SC_EINT0 (1 << 0)
00055 #define SC_EINT1 (1 << 1)
00056 #define SC_EINT2 (1 << 2)
00057 #define SC_EINT3 (1 << 3)
00059
00060
00062 #define SC_EXTMODE_OFF 0x00000148
00063 #define SC_EXTMODE (LPC_SC_BASE + SC_EXTMODE_OFF)
00064 #define SC_EXTMODE0 (1 << 0)
00065 #define SC_EXTMODE1 (1 << 1)
00066 #define SC_EXTMODE2 (1 << 2)
00067 #define SC_EXTMODE3 (1 << 3)
00069
00070
00072 #define SC_EXTPOLAR_OFF 0x0000014C
00073 #define SC_EXTPOLAR (LPC_SC_BASE + SC_EXTPOLAR_OFF)
00074 #define SC_EXTPOLAR0 (1 << 0)
00075 #define SC_EXTPOLAR1 (1 << 1)
00076 #define SC_EXTPOLAR2 (1 << 2)
00077 #define SC_EXTPOLAR3 (1 << 3)
00079
00080
00082 #define SC_RSID_OFF 0x00000180
00083 #define SC_RSID (LPC_SC_BASE + SC_RSID_OFF)
00084 #define SC_RSID_POR (1 << 0)
00085 #define SC_RSID_EXTR (1 << 1)
00086 #define SC_RSID_WDTR (1 << 2)
00087 #define SC_RSID_BODR (1 << 3)
00089
00090
00092 #define SC_SCS_OFF 0x000001A0
00093 #define SC_SCS (LPC_SC_BASE + SC_SCS_OFF)
00094 #define SC_OSCRANGE (1 << 4)
00095 #define SC_OSCEN (1 << 5)
00096 #define SC_OSCSTAT (1 << 6)
00098
00099
00101 #define SC_CLKSRCSEL_OFF 0x0000010C
00102 #define SC_CLKSRCSEL (LPC_SC_BASE + SC_CLKSRCSEL_OFF)
00103 #define SC_CLKSRC 0x00000003
00104 #define SC_CLKSRC_RCCLK 0x00000000
00105 #define SC_CLKSRC_MCLK 0x00000001
00106 #define SC_CLKSRC_RTCCLK 0x00000002
00107
00111 #define SC_PLL0CON_OFF 0x00000080
00112 #define SC_PLL0CON (LPC_SC_BASE + SC_PLL0CON_OFF)
00113 #define SC_PLL1CON_OFF 0x000000A0
00114 #define SC_PLL1CON (LPC_SC_BASE + SC_PLL1CON_OFF)
00115 #define SC_PLLE (1 << 0)
00116 #define SC_PLLC (1 << 1)
00117
00121 #define SC_PLL0CFG_OFF 0x00000084
00122 #define SC_PLL0CFG (LPC_SC_BASE + SC_PLL0CFG_OFF)
00123 #define SC_PLL1CFG_OFF 0x000000A4
00124 #define SC_PLL1CFG (LPC_SC_BASE + SC_PLL1CFG_OFF)
00125 #define SC_MSEL_LSB 0
00126 #define SC_MSEL 0x00007FFF
00127 #define SC_NSEL_LSB 16
00128 #define SC_NSEL 0x00FF0000
00129
00133 #define SC_PLL0STAT_OFF 0x00000088
00134 #define SC_PLL0STAT (LPC_SC_BASE + SC_PLL0STAT_OFF)
00135 #define SC_PLL1STAT_OFF 0x000000A8
00136 #define SC_PLL1STAT (LPC_SC_BASE + SC_PLL1STAT_OFF)
00137 #define SC_PLLE_STAT (1 << 24)
00138 #define SC_PLLC_STAT (1 << 25)
00139 #define SC_PLOCK (1 << 26)
00140
00144 #define SC_PLL0FEED_OFF 0x0000008C
00145 #define SC_PLL0FEED (LPC_SC_BASE + SC_PLL0FEED_OFF)
00146 #define SC_PLL1FEED_OFF 0x000000AC
00147 #define SC_PLL1FEED (LPC_SC_BASE + SC_PLL1FEED_OFF)
00148 #define PLLFEED_FEED1 0xAA
00149 #define PLLFEED_FEED2 0x55
00150
00154 #define SC_CCLKCFG_OFF 0x00000104
00155 #define SC_CCLKCFG (LPC_SC_BASE + SC_CCLKCFG_OFF)
00156 #define SC_CCLKSEL 0x000000FF
00157 #define SC_CCLKSEL_LSB 0
00158
00162 #define SC_USBCLKCFG_OFF 0x00000108
00163 #define SC_USBCLKCFG (LPC_SC_BASE + SC_USBCLKCFG_OFF)
00164 #define SC_USBSEL 0x0000000F
00165 #define SC_USBSEL_LSB 0
00166
00170 #define SC_PCLKSEL0_OFF 0x000001A8
00171 #define SC_PCLKSEL0 (LPC_SC_BASE + SC_PCLKSEL0_OFF)
00172 #define SC_PCLK_DIV1 0x1
00173 #define SC_PCLK_DIV2 0x2
00174 #define SC_PCLK_DIV4 0x0
00175 #define SC_PCLK_DIV8 0x3
00176 #define SC_PCLK_WDT_LSB 0
00177 #define SC_PCLK_WDT (0x3 << SC_PCLK_WDT_LSB)
00178 #define SC_PCLK_TIMER0_LSB 2
00179 #define SC_PCLK_TIMER0 (0x3 << SC_PCLK_TIMER0_LSB)
00180 #define SC_PCLK_TIMER1_LSB 4
00181 #define SC_PCLK_TIMER1 (0x3 << SC_PCLK_TIMER1_LSB)
00182 #define SC_PCLK_UART0_LSB 6
00183 #define SC_PCLK_UART0 (0x3 << SC_PCLK_UART0_LSB)
00184 #define SC_PCLK_UART1_LSB 8
00185 #define SC_PCLK_UART1 (0x3 << SC_PCLK_UART1_LSB)
00186 #define SC_PCLK_PWM1_LSB 12
00187 #define SC_PCLK_PWM1 (0x3 << SC_PCLK_PWM1_LSB)
00188 #define SC_PCLK_I2C0_LSB 14
00189 #define SC_PCLK_I2C0 (0x3 << SC_PCLK_I2C0_LSB)
00190 #define SC_PCLK_SPI_LSB 16
00191 #define SC_PCLK_SPI (0x3 << SC_PCLK_SPI_LSB)
00192 #define SC_PCLK_SSP1_LSB 20
00193 #define SC_PCLK_SSP1 (0x3 << SC_PCLK_SSP1_LSB)
00194 #define SC_PCLK_DAC_LSB 22
00195 #define SC_PCLK_DAC (0x3 << SC_PCLK_DAC_LSB)
00196 #define SC_PCLK_ADC_LSB 24
00197 #define SC_PCLK_ADC (0x3 << SC_PCLK_ADC_LSB)
00198 #define SC_PCLK_CAN1_LSB 26
00199 #define SC_PCLK_CAN1 (0x3 << SC_PCLK_CAN1_LSB)
00200 #define SC_PCLK_CAN2_LSB 28
00201 #define SC_PCLK_CAN2 (0x3 << SC_PCLK_CAN2_LSB)
00202 #define SC_PCLK_ACF_LSB 30
00203 #define SC_PCLK_ACF (0x3 << SC_PCLK_ACF_LSB)
00204
00209 #define SC_PCLKSEL1_OFF 0x000001AC
00210 #define SC_PCLKSEL1 (LPC_SC_BASE + SC_PCLKSEL1_OFF)
00211 #define SC_PCLK_QEI_LSB 0
00212 #define SC_PCLK_QEI (0x3 << SC_PCLK_QEI_LSB)
00213 #define SC_PCLK_GPIOINT_LSB 2
00214 #define SC_PCLK_GPIOINT (0x3 << SC_PCLK_GPIOINT_LSB)
00215 #define SC_PCLK_PCB_LSB 4
00216 #define SC_PCLK_PCB (0x3 << SC_PCLK_PCB_LSB)
00217 #define SC_PCLK_I2C1_LSB 6
00218 #define SC_PCLK_I2C1 (0x3 << SC_PCLK_I2C1_LSB)
00219 #define SC_PCLK_SSP0_LSB 10
00220 #define SC_PCLK_SSP0 (0x3 << SC_PCLK_SSP0_LSB)
00221 #define SC_PCLK_TIMER2_LSB 12
00222 #define SC_PCLK_TIMER2 (0x3 << SC_PCLK_TIMER2_LSB)
00223 #define SC_PCLK_TIMER3_LSB 14
00224 #define SC_PCLK_TIMER3 (0x3 << SC_PCLK_TIMER3_LSB)
00225 #define SC_PCLK_UART2_LSB 16
00226 #define SC_PCLK_UART2 (0x3 << SC_PCLK_UART2_LSB)
00227 #define SC_PCLK_UART3_LSB 18
00228 #define SC_PCLK_UART3 (0x3 << SC_PCLK_UART3_LSB)
00229 #define SC_PCLK_I2C2_LSB 20
00230 #define SC_PCLK_I2C2 (0x3 << SC_PCLK_I2C2_LSB)
00231 #define SC_PCLK_I2S_LSB 22
00232 #define SC_PCLK_I2S (0x3 << SC_PCLK_I2S_LSB)
00233 #define SC_PCLK_RIT_LSB 26
00234 #define SC_PCLK_RIT (0x3 << SC_PCLK_RIT_LSB)
00235 #define SC_PCLK_SYSCON_LSB 28
00236 #define SC_PCLK_SYSCON (0x3 << SC_PCLK_SYSCON_LSB)
00237 #define SC_PCLK_MC_LSB 30
00238 #define SC_PCLK_MC (0x3 << SC_PCLK_MC_LSB)
00239
00243 #define SC_PCON_OFF 0x000000C0
00244 #define SC_PCON (LPC_SC_BASE + SC_PCON_OFF)
00245 #define SC_PM0 (1 << 0)
00246 #define SC_PM1 (1 << 1)
00247 #define SC_BODRPM (1 << 2)
00248 #define SC_BOGD (1 << 3)
00249 #define SC_BORD (1 << 4)
00250 #define SC_SMFLAG (1 << 8)
00251 #define SC_DSFLAG (1 << 9)
00252 #define SC_PDFLAG (1 << 10)
00253 #define SC_DPDFLAG (1 << 11)
00254
00258 #define SC_PCONP_OFF 0x000000C4
00259 #define SC_PCONP (LPC_SC_BASE + SC_PCONP_OFF)
00260 #define SC_PCTIM0 (1 << 1)
00261 #define SC_PCTIM1 (1 << 2)
00262 #define SC_PCUART0 (1 << 3)
00263 #define SC_PCUART1 (1 << 4)
00264 #define SC_PCPWM1 (1 << 6)
00265 #define SC_PCI2C0 (1 << 7)
00266 #define SC_PCSPI (1 << 8)
00267 #define SC_PCRTC (1 << 9)
00268 #define SC_PCSSP1 (1 << 10)
00269 #define SC_PCADC (1 << 12)
00270 #define SC_PCCAN1 (1 << 13)
00271 #define SC_PCCAN2 (1 << 14)
00272 #define SC_PCGPIO (1 << 15)
00273 #define SC_PCRIT (1 << 16)
00274 #define SC_PCMCPWM (1 << 17)
00275 #define SC_PCQEI (1 << 18)
00276 #define SC_PCI2C1 (1 << 19)
00277 #define SC_PCSSP0 (1 << 21)
00278 #define SC_PCTIM2 (1 << 22)
00279 #define SC_PCTIM3 (1 << 23)
00280 #define SC_PCUART2 (1 << 24)
00281 #define SC_PCUART3 (1 << 25)
00282 #define SC_PCI2C2 (1 << 26)
00283 #define SC_PCI2S (1 << 27)
00284 #define SC_PCGPDMA (1 << 29)
00285 #define SC_PCENET (1 << 30)
00286 #define SC_PCUSB (1 << 31)
00287
00291 #define SC_CLKOUTCFG_OFF 0x000001C8
00292 #define SC_CLKOUTCFG (LPC_SC_BASE + SC_CLKOUTCFG_OFF)
00293 #define SC_CLKOUTSEL 0x0000000F
00294 #define SC_CLKOUTSEL_CCLK 0x0
00295 #define SC_CLKOUTSEL_MCLK 0x1
00296 #define SC_CLKOUTSEL_RCCLK 0x2
00297 #define SC_CLKOUTSEL_USBCLK 0x3
00298 #define SC_CLKOUTSEL_RTCCLK 0x4
00299 #define SC_CLKOUTDIV 0x000000F0
00300 #define SC_CLKOUTDIV_LSB 4
00301 #define SC_CLKOUT_EN (1 << 8)
00302 #define SC_CLKOUT_ACT (1 << 9)
00303
00307 #define SC_FLASHCFG_OFF 0x00000000
00308 #define SC_FLASHCFG (LPC_SC_BASE + SC_FLASHCFG_OFF)
00309 #define SC_FLASHTIM_LSB 12
00310 #define SC_FLASHTIM 0x0000F000
00311
00315
00316 #endif