Structure type to access the Trace Port Interface Register (TPI). More...
#include <core_cm3.h>
Data Fields | |
__IO uint32_t | SSPSR |
__IO uint32_t | CSPSR |
uint32_t | RESERVED0 [2] |
__IO uint32_t | ACPR |
uint32_t | RESERVED1 [55] |
__IO uint32_t | SPPR |
uint32_t | RESERVED2 [131] |
__I uint32_t | FFSR |
__IO uint32_t | FFCR |
__I uint32_t | FSCR |
uint32_t | RESERVED3 [759] |
__I uint32_t | TRIGGER |
__I uint32_t | FIFO0 |
__I uint32_t | ITATBCTR2 |
uint32_t | RESERVED4 [1] |
__I uint32_t | ITATBCTR0 |
__I uint32_t | FIFO1 |
__IO uint32_t | ITCTRL |
uint32_t | RESERVED5 [39] |
__IO uint32_t | CLAIMSET |
__IO uint32_t | CLAIMCLR |
uint32_t | RESERVED7 [8] |
__I uint32_t | DEVID |
__I uint32_t | DEVTYPE |
Structure type to access the Trace Port Interface Register (TPI).
__IO uint32_t TPI_Type::SSPSR |
Offset: 0x000 (R/ ) Supported Parallel Port Size Register
__IO uint32_t TPI_Type::CSPSR |
Offset: 0x004 (R/W) Current Parallel Port Size Register
__IO uint32_t TPI_Type::ACPR |
Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register
__IO uint32_t TPI_Type::SPPR |
Offset: 0x0F0 (R/W) Selected Pin Protocol Register
Offset: 0x300 (R/ ) Formatter and Flush Status Register
__IO uint32_t TPI_Type::FFCR |
Offset: 0x304 (R/W) Formatter and Flush Control Register
Offset: 0x308 (R/ ) Formatter Synchronization Counter Register
Offset: 0xEE8 (R/ ) TRIGGER
Offset: 0xEEC (R/ ) Integration ETM Data
Offset: 0xEF0 (R/ ) ITATBCTR2
Offset: 0xEF8 (R/ ) ITATBCTR0
Offset: 0xEFC (R/ ) Integration ITM Data
__IO uint32_t TPI_Type::ITCTRL |
Offset: 0xF00 (R/W) Integration Mode Control
Offset: 0xFA0 (R/W) Claim tag set
Offset: 0xFA4 (R/W) Claim tag clear
Offset: 0xFC8 (R/ ) TPIU_DEVID
Offset: 0xFCC (R/ ) TPIU_DEVTYPE