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Defines | |
#define | MATRIX_MASTER_I 0 |
#define | MATRIX_MASTER_D 1 |
#define | MATRIX_MASTER_PDC 2 |
#define | MATRIX_MASTER_ISI 3 |
#define | MATRIX_MASTER_EMAC 4 |
#define | MATRIX_MASTER_USB 5 |
#define | MATRIX_SLAVE_SRAM0 0 |
#define | MATRIX_SLAVE_SRAM1 1 |
#define | MATRIX_SLAVE_ROM_USB 2 |
#define | MATRIX_SLAVE_EBI 3 |
#define | MATRIX_SLAVE_PERIPHERALS 4 |
Master Configuration Registers | |
#define | MATRIX_MCFG_OFF 0x00000000 |
Master configuration register offset. | |
#define | MATRIX_MCFG(i) (MATRIX_BASE + MATRIX_MCFG_OFF + (i) * 4) |
Master configuration register addresses. | |
Slave Configuration Registers | |
#define | MATRIX_SCFG_OFF 0x00000040 |
Slave configuration register offset. | |
#define | MATRIX_SCFG(i) (MATRIX_BASE + MATRIX_SCFG_OFF + (i) * 4) |
Slave configuration register addresses. | |
Slave Priority Registers | |
#define | MATRIX_PRAS_OFF 0x00000080 |
Slave priority register A offset. | |
#define | MATRIX_PRAS(i) (MATRIX_BASE + MATRIX_PRAS_OFF + (i) * 8) |
Slave priority register A addresses. | |
Master Remap Control Register | |
#define | MATRIX_MRCR_OFF 0x00000100 |
Remap control register offset. | |
#define | MATRIX_MRCR (MATRIX_BASE + MATRIX_MRCR_OFF) |
Remap control register address. | |
#define | MATRIX_MRCR_RCB0 0x00000001 |
Enable remap for master 0. | |
#define | MATRIX_MRCR_RCB1 0x00000002 |
Enable remap for master 1. |