at91_shdwc.h

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#ifndef _ARCH_ARM_AT91_SHDWC_H_
#define _ARCH_ARM_AT91_SHDWC_H_

/*
 * Copyright (C) 2010 by egnite GmbH
 *
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the name of the copyright holders nor the names of
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
 * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 * For additional information see http://www.ethernut.de/
 */


#define SHDWC_CR_OFF                0x00000000  
#define SHDWC_CR    (SHDWC_BASE + SHDWC_CR_OFF) 
#define SHDWC_SHDW                  0x00000001  
#define SHDWC_KEY                   0xA5000000  


#define SHDWC_MR_OFF                0x00000004  
#define SHDWC_MR    (SHDWC_BASE + SHDWC_MR_OFF) 
#define SHDWC_WKMODE0               0x00000003  
#define SHDWC_WKMODE0_NONE          0x00000000  
#define SHDWC_WKMODE0_HIGH          0x00000001  
#define SHDWC_WKMODE0_LOW           0x00000002  
#define SHDWC_WKMODE0_ANYLEVEL      0x00000003  
#define SHDWC_CPTWK0                0x000000F0  
#define SHDWC_CPTWK0_LSB                    4   
#define SHDWC_WKMODE1               0x00000300  
#define SHDWC_WKMODE1_NONE          0x00000000  
#define SHDWC_WKMODE1_HIGH          0x00000100  
#define SHDWC_WKMODE1_LOW           0x00000200  
#define SHDWC_WKMODE1_ANYLEVEL      0x00000300  
#define SHDWC_CPTWK1                0x0000F000  
#define SHDWC_CPTWK1_LSB                    12  
#define SHDWC_RTTWKEN               0x00010000  
#define SHDWC_RTCWKEN               0x00020000  


#define SHDWC_SR_OFF                0x00000008  
#define SHDWC_SR    (SHDWC_BASE + SHDWC_SR_OFF) 
#define SHDWC_WAKEUP0               0x00000001  
#define SHDWC_WAKEUP1               0x00000002  
#define SHDWC_FWKUP                 0x00000004  
#define SHDWC_RTTWK                 0x00010000  
#define SHDWC_RTCWK                 0x00020000  


#endif /* _ARCH_ARM_AT91_SHDWC_H_ */