at91_wd.h File Reference

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Watch Dog Overflow Mode Register
#define	WD_OMR   (WD_BASE + 0x00)
	Overflow mode register address.
#define	WD_WDEN   0x00000001
	Watch Dog enable.
#define	WD_RSTEN   0x00000002
	Internal reset enable.
#define	WD_IRQEN   0x00000004
	Interrupt enable.
#define	WD_EXTEN   0x00000008
	External signal enable.
#define	WD_OKEY   0x00002340
	Overflow mode register access key.
Watch Dog Clock Register
#define	WD_CMR   (WD_BASE + 0x04)
	Clock mode register address.
#define	WD_WDCLKS   0x00000003
	Clock selection mask.
#define	WD_WDCLKS_MCK8   0x00000000
	Selects MCK/8.
#define	WD_WDCLKS_MCK32   0x00000001
	Selects MCK/32.
#define	WD_WDCLKS_MCK128   0x00000002
	Selects MCK/128.
#define	WD_WDCLKS_MCK1024   0x00000003
	Selects MCK/1024.
#define	WD_HPCV   0x0000003C
	High preload counter value.
#define	WD_CKEY   (0x06E<<7)
	Clock register access key.
Watch Dog Control Register
#define	WD_CR   (WD_BASE + 0x08)
	Control register address.
#define	WD_RSTKEY   0x0000C071
	Watch Dog restart key.
Watch Dog Status Register
#define	WD_SR   (WD_BASE + 0x0C)
	Status register address.
#define	WD_WDOVF   0x00000001
	Watch Dog overflow status.