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Nut/OS
4.10.3
API Reference
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Nut/OS
4.10.3
API Reference
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Ports used by the Medianut MP3 Add-On. More...
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Defines | |
| #define | VS_SCK_PORT PORTB |
| #define | VS_SCK_DDR DDRB |
| #define | VS_SCK_BIT 0 |
| VS1001 serial control interface clock input bit. The first rising clock edge after XCS has gone low marks the first bit to be written to the decoder. | |
| #define | VS_SS_PORT PORTB |
| #define | VS_SS_DDR DDRB |
| #define | VS_SS_BIT 1 |
| VS1001 serial data interface clock input bit. | |
| #define | VS_SI_PORT PORTB |
| #define | VS_SI_DDR DDRB |
| #define | VS_SI_BIT 2 |
| VS1001 serial control interface data input. The decoder samples this input on the rising edge of SCK if XCS is low. | |
| #define | VS_SO_PIN PINB |
| #define | VS_SO_DDR DDRB |
| #define | VS_SO_BIT 3 |
| VS1001 serial control interface data output. If data is transfered from the decoder, bits are shifted out on the falling SCK edge. If data is transfered to the decoder, SO is at a high impedance state. | |
| #define | VS_XCS_PORT PORTB |
| #define | VS_XCS_DDR DDRB |
| #define | VS_XCS_BIT 4 |
| VS1001 active low chip select input. A high level forces the serial interface into standby mode, ending the current operation. A high level also forces serial output (SO) to high impedance state. | |
| #define | VS_BSYNC_PORT PORTB |
| #define | VS_BSYNC_DDR DDRB |
| #define | VS_BSYNC_BIT 5 |
| VS1001 serial data interface bit sync. The first DCLK sampling edge, during which BSYNC is high, marks the first bit of a data byte. | |
| #define | VS_RESET_PORT PORTB |
| #define | VS_RESET_DDR DDRB |
| #define | VS_RESET_BIT 7 |
| VS1001 hardware reset input. | |
| #define | VS_DREQ_PORT PORTE |
| #define | VS_DREQ_PIN PINE |
| #define | VS_DREQ_DDR DDRE |
| #define | VS_DREQ_BIT 6 |
| VS1001 data request output. | |
| #define | LCD_DATA_PORT PORTD |
| #define | LCD_DATA_DDR DDRD |
| #define | LCD_DATA_BITS 0xF0 |
| LCD data lines, either upper or lower 4 bits. | |
| #define | LCD_ENABLE_PORT PORTE |
| #define | LCD_ENABLE_DDR DDRE |
| #define | LCD_ENABLE_BIT 3 |
| LCD enable output. | |
| #define | LCD_REGSEL_PORT PORTE |
| #define | LCD_REGSEL_DDR DDRE |
| #define | LCD_REGSEL_BIT 2 |
| LCD register select output. | |
| #define | LCD_LIGHT_PORT PORTB |
| #define | LCD_LIGHT_DDR DDRB |
| #define | LCD_LIGHT_BIT 6 |
| LCD output to switch backlight. | |
| #define | IR_SIGNAL_PORT PORTE |
| #define | IR_SIGNAL_PIN PINE |
| #define | IR_SIGNAL_DDR DDRE |
| #define | IR_SIGNAL_BIT 4 |
| Infrared decoder signal bit. | |
Ports used by the Medianut MP3 Add-On.
Medianut is an add-on board and can be attached to the Ethernut expansion port. It contains a VS1001K MP3 decoder, a LCD interface and an infrared receiver.
| #define VS_SCK_PORT PORTB |
Port register of VS_SCK_BIT.
Definition at line 66 of file medianut.h.
| #define VS_SCK_DDR DDRB |
Data direction register of VS_SCK_BIT.
Definition at line 67 of file medianut.h.
| #define VS_SCK_BIT 0 |
VS1001 serial control interface clock input bit. The first rising clock edge after XCS has gone low marks the first bit to be written to the decoder.
Definition at line 68 of file medianut.h.
| #define VS_SS_PORT PORTB |
Port output register of VS_SS_BIT.
Definition at line 73 of file medianut.h.
| #define VS_SS_DDR DDRB |
Data direction register of VS_SS_BIT.
Definition at line 74 of file medianut.h.
| #define VS_SS_BIT 1 |
VS1001 serial data interface clock input bit.
Definition at line 75 of file medianut.h.
| #define VS_SI_PORT PORTB |
Port output register of VS_SI_BIT.
Definition at line 77 of file medianut.h.
| #define VS_SI_DDR DDRB |
Data direction register of VS_SI_BIT.
Definition at line 78 of file medianut.h.
| #define VS_SI_BIT 2 |
VS1001 serial control interface data input. The decoder samples this input on the rising edge of SCK if XCS is low.
Definition at line 79 of file medianut.h.
| #define VS_SO_PIN PINB |
Port input register of VS_SO_BIT.
Definition at line 84 of file medianut.h.
| #define VS_SO_DDR DDRB |
Data direction register of VS_SO_BIT.
Definition at line 85 of file medianut.h.
| #define VS_SO_BIT 3 |
VS1001 serial control interface data output. If data is transfered from the decoder, bits are shifted out on the falling SCK edge. If data is transfered to the decoder, SO is at a high impedance state.
Definition at line 86 of file medianut.h.
| #define VS_XCS_PORT PORTB |
Port output register of VS_XCS_BIT.
Definition at line 93 of file medianut.h.
| #define VS_XCS_DDR DDRB |
Data direction register of VS_XCS_BIT.
Definition at line 94 of file medianut.h.
| #define VS_XCS_BIT 4 |
VS1001 active low chip select input. A high level forces the serial interface into standby mode, ending the current operation. A high level also forces serial output (SO) to high impedance state.
Definition at line 95 of file medianut.h.
| #define VS_BSYNC_PORT PORTB |
Port output register of VS_BSYNC_BIT.
Definition at line 102 of file medianut.h.
| #define VS_BSYNC_DDR DDRB |
Data direction register of VS_BSYNC_BIT.
Definition at line 103 of file medianut.h.
| #define VS_BSYNC_BIT 5 |
VS1001 serial data interface bit sync. The first DCLK sampling edge, during which BSYNC is high, marks the first bit of a data byte.
Definition at line 104 of file medianut.h.
| #define VS_RESET_PORT PORTB |
Port output register of VS_RESET_BIT.
Definition at line 110 of file medianut.h.
| #define VS_RESET_DDR DDRB |
Data direction register of VS_RESET_BIT.
Definition at line 111 of file medianut.h.
| #define VS_RESET_BIT 7 |
VS1001 hardware reset input.
Definition at line 112 of file medianut.h.
| #define VS_DREQ_PORT PORTE |
Port output register of VS_DREQ_BIT.
Definition at line 114 of file medianut.h.
| #define VS_DREQ_PIN PINE |
Port input register of VS_DREQ_BIT.
Definition at line 115 of file medianut.h.
| #define VS_DREQ_DDR DDRE |
Data direction register of VS_DREQ_BIT.
Definition at line 116 of file medianut.h.
| #define VS_DREQ_BIT 6 |
VS1001 data request output.
Definition at line 117 of file medianut.h.
| #define LCD_DATA_PORT PORTD |
Port output register of LCD_DATA_BITS.
Definition at line 121 of file medianut.h.
| #define LCD_DATA_DDR DDRD |
Data direction register of LCD_DATA_BITS.
Definition at line 122 of file medianut.h.
| #define LCD_DATA_BITS 0xF0 |
LCD data lines, either upper or lower 4 bits.
Definition at line 123 of file medianut.h.
| #define LCD_ENABLE_PORT PORTE |
Port output register of LCD_ENABLE_BIT.
Definition at line 125 of file medianut.h.
| #define LCD_ENABLE_DDR DDRE |
Data direction register of LCD_ENABLE_BIT.
Definition at line 126 of file medianut.h.
| #define LCD_ENABLE_BIT 3 |
LCD enable output.
Definition at line 127 of file medianut.h.
| #define LCD_REGSEL_PORT PORTE |
Port output register of LCD_REGSEL_BIT.
Definition at line 129 of file medianut.h.
| #define LCD_REGSEL_DDR DDRE |
Data direction register of LCD_REGSEL_BIT.
Definition at line 130 of file medianut.h.
| #define LCD_REGSEL_BIT 2 |
LCD register select output.
Definition at line 131 of file medianut.h.
| #define LCD_LIGHT_PORT PORTB |
Port output register of LCD_LIGHT_BIT.
Definition at line 133 of file medianut.h.
| #define LCD_LIGHT_DDR DDRB |
Data direction register of LCD_LIGHT_BIT.
Definition at line 134 of file medianut.h.
| #define LCD_LIGHT_BIT 6 |
LCD output to switch backlight.
Definition at line 135 of file medianut.h.
| #define IR_SIGNAL_PORT PORTE |
Port output register of IR_SIGNAL_BIT.
Definition at line 137 of file medianut.h.
| #define IR_SIGNAL_PIN PINE |
Port input register of IR_SIGNAL_BIT.
Definition at line 138 of file medianut.h.
Referenced by SIG_INTERRUPT4().
| #define IR_SIGNAL_DDR DDRE |
Data direction register of IR_SIGNAL_BIT.
Definition at line 139 of file medianut.h.
Referenced by NutIrInitSony().
| #define IR_SIGNAL_BIT 4 |
Infrared decoder signal bit.
Definition at line 140 of file medianut.h.
Referenced by NutIrInitSony(), and SIG_INTERRUPT4().