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Nut/OS
4.10.3
API Reference
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Nut/OS
4.10.3
API Reference
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Advanced interrupt controller registers. More...
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Interrupt Source Mode Registers | |
| #define | AIC_SMR(i) (AIC_BASE + i * 4) |
| Source mode register array. | |
| #define | AIC_PRIOR 0x00000007 |
| Priority mask. | |
| #define | AIC_SRCTYPE 0x00000060 |
| Interrupt source type mask. | |
| #define | AIC_SRCTYPE_INT_LEVEL_SENSITIVE 0x00000000 |
| Internal level sensitive. | |
| #define | AIC_SRCTYPE_INT_EDGE_TRIGGERED 0x00000020 |
| Internal edge triggered. | |
| #define | AIC_SRCTYPE_EXT_LOW_LEVEL 0x00000000 |
| External low level. | |
| #define | AIC_SRCTYPE_EXT_NEGATIVE_EDGE 0x00000020 |
| External falling edge. | |
| #define | AIC_SRCTYPE_EXT_HIGH_LEVEL 0x00000040 |
| External high level. | |
| #define | AIC_SRCTYPE_EXT_POSITIVE_EDGE 0x00000060 |
| External rising edge. | |
Interrupt Source Vector Registers | |
| #define | AIC_SVR(i) (AIC_BASE + 0x80 + i * 4) |
| Source vector register array. | |
Interrupt Vector Register | |
| #define | AIC_IVR_OFF 0x00000100 |
| IRQ vector register offset. | |
| #define | AIC_IVR (AIC_BASE + AIC_IVR_OFF) |
| IRQ vector register address. | |
Fast Interrupt Vector Register | |
| #define | AIC_FVR_OFF 0x00000104 |
| FIQ vector register offset. | |
| #define | AIC_FVR (AIC_BASE + AIC_FVR_OFF) |
| FIQ vector register address. | |
Interrupt Status Register | |
| #define | AIC_ISR_OFF 0x00000108 |
| Interrupt status register offset. | |
| #define | AIC_ISR (AIC_BASE + AIC_ISR_OFF) |
| Interrupt status register address. | |
| #define | AIC_IRQID 0x0000001F |
| Current interrupt identifier mask. | |
Interrupt Pending Register | |
| #define | AIC_IPR_OFF 0x0000010C |
| Interrupt pending register offset. | |
| #define | AIC_IPR (AIC_BASE + AIC_IPR_OFF) |
| Interrupt pending register address. | |
Interrupt Mask Register | |
| #define | AIC_IMR_OFF 0x00000110 |
| Interrupt mask register offset. | |
| #define | AIC_IMR (AIC_BASE + AIC_IMR_OFF) |
| Interrupt mask register address. | |
Interrupt Core Status Register | |
| #define | AIC_CISR_OFF 0x00000114 |
| Core interrupt status register offset. | |
| #define | AIC_CISR (AIC_BASE + AIC_CISR_OFF) |
| Core interrupt status register address. | |
| #define | AIC_NFIQ 0x00000001 |
| Core FIQ Status. | |
| #define | AIC_NIRQ 0x00000002 |
| Core IRQ Status. | |
Interrupt Enable Command Register | |
| #define | AIC_IECR_OFF 0x00000120 |
| Interrupt enable command register offset. | |
| #define | AIC_IECR (AIC_BASE + AIC_IECR_OFF) |
| Interrupt enable command register address. | |
Interrupt Disable Command Register | |
| #define | AIC_IDCR_OFF 0x00000124 |
| Interrupt disable command register offset. | |
| #define | AIC_IDCR (AIC_BASE + AIC_IDCR_OFF) |
| Interrupt disable command register address. | |
Interrupt Clear Command Register | |
| #define | AIC_ICCR_OFF 0x00000128 |
| Interrupt clear command register offset. | |
| #define | AIC_ICCR (AIC_BASE + AIC_ICCR_OFF) |
| Interrupt clear command register address. | |
Interrupt Set Command Register | |
| #define | AIC_ISCR_OFF 0x0000012C |
| Interrupt set command register offset. | |
| #define | AIC_ISCR (AIC_BASE + AIC_ISCR_OFF) |
| Interrupt set command register address. | |
End Of Interrupt Command Register | |
| #define | AIC_EOICR_OFF 0x00000130 |
| End of interrupt command register offset. | |
| #define | AIC_EOICR (AIC_BASE + AIC_EOICR_OFF) |
| End of interrupt command register address. | |
Spurious Interrupt Vector Register | |
| #define | AIC_SPU_OFF 0x00000134 |
| Spurious vector register offset. | |
| #define | AIC_SPU (AIC_BASE + AIC_SPU_OFF) |
| Spurious vector register address. | |
Debug Control Register | |
| #define | AIC_DCR_OFF 0x0000138 |
| Debug control register offset. | |
| #define | AIC_DCR (AIC_BASE + AIC_DCR_OFF) |
| Debug control register address. | |
Fast Forcing Enable Register | |
| #define | AIC_FFER_OFF 0x00000140 |
| Fast forcing enable register offset. | |
| #define | AIC_FFER (AIC_BASE + AIC_FFER_OFF) |
| Fast forcing enable register address. | |
Fast Forcing Disable Register | |
| #define | AIC_FFDR_OFF 0x00000144 |
| Fast forcing disable register address. | |
| #define | AIC_FFDR (AIC_BASE + AIC_FFDR_OFF) |
| Fast forcing disable register address. | |
Fast Forcing Status Register | |
| #define | AIC_FFSR_OFF 0x00000148 |
| Fast forcing status register address. | |
| #define | AIC_FFSR (AIC_BASE + AIC_FFSR_OFF) |
| Fast forcing status register address. | |
Advanced interrupt controller registers.
The AT91 series provides an 8-level priority, individually maskable, vectored interrupt controller.
| #define AIC_SMR | ( | i | ) | (AIC_BASE + i * 4) |
Source mode register array.
Definition at line 62 of file at91_aic.h.
Referenced by AsixInit(), and NutRegisterTimer().
| #define AIC_PRIOR 0x00000007 |
Priority mask.
Priority levels can be between 0 (lowest) and 7 (highest).
Definition at line 68 of file at91_aic.h.
| #define AIC_SRCTYPE 0x00000060 |
Interrupt source type mask.
Internal interrupts can level sensitive or edge triggered.
External interrupts can triggered on positive or negative levels or on rising or falling edges.
Definition at line 77 of file at91_aic.h.
| #define AIC_SRCTYPE_INT_LEVEL_SENSITIVE 0x00000000 |
Internal level sensitive.
Definition at line 79 of file at91_aic.h.
Referenced by NutRegisterTimer().
| #define AIC_SRCTYPE_INT_EDGE_TRIGGERED 0x00000020 |
Internal edge triggered.
Definition at line 80 of file at91_aic.h.
| #define AIC_SRCTYPE_EXT_LOW_LEVEL 0x00000000 |
External low level.
Definition at line 81 of file at91_aic.h.
| #define AIC_SRCTYPE_EXT_NEGATIVE_EDGE 0x00000020 |
| #define AIC_SRCTYPE_EXT_HIGH_LEVEL 0x00000040 |
External high level.
Definition at line 83 of file at91_aic.h.
| #define AIC_SRCTYPE_EXT_POSITIVE_EDGE 0x00000060 |
External rising edge.
Definition at line 84 of file at91_aic.h.
| #define AIC_SVR | ( | i | ) | (AIC_BASE + 0x80 + i * 4) |
Source vector register array.
Stores the addresses of the corresponding interrupt handlers.
Definition at line 93 of file at91_aic.h.
Referenced by AsixInit(), and NutRegisterTimer().
| #define AIC_IVR_OFF 0x00000100 |
IRQ vector register offset.
Definition at line 98 of file at91_aic.h.
| #define AIC_IVR (AIC_BASE + AIC_IVR_OFF) |
IRQ vector register address.
Definition at line 99 of file at91_aic.h.
| #define AIC_FVR_OFF 0x00000104 |
FIQ vector register offset.
Definition at line 104 of file at91_aic.h.
| #define AIC_FVR (AIC_BASE + AIC_FVR_OFF) |
FIQ vector register address.
Definition at line 105 of file at91_aic.h.
| #define AIC_ISR_OFF 0x00000108 |
Interrupt status register offset.
Definition at line 110 of file at91_aic.h.
| #define AIC_ISR (AIC_BASE + AIC_ISR_OFF) |
Interrupt status register address.
Definition at line 111 of file at91_aic.h.
| #define AIC_IRQID 0x0000001F |
Current interrupt identifier mask.
Definition at line 112 of file at91_aic.h.
| #define AIC_IPR_OFF 0x0000010C |
Interrupt pending register offset.
Definition at line 117 of file at91_aic.h.
| #define AIC_IPR (AIC_BASE + AIC_IPR_OFF) |
Interrupt pending register address.
Definition at line 118 of file at91_aic.h.
| #define AIC_IMR_OFF 0x00000110 |
Interrupt mask register offset.
Definition at line 123 of file at91_aic.h.
| #define AIC_IMR (AIC_BASE + AIC_IMR_OFF) |
Interrupt mask register address.
Definition at line 124 of file at91_aic.h.
| #define AIC_CISR_OFF 0x00000114 |
Core interrupt status register offset.
Definition at line 129 of file at91_aic.h.
| #define AIC_CISR (AIC_BASE + AIC_CISR_OFF) |
Core interrupt status register address.
Definition at line 130 of file at91_aic.h.
| #define AIC_NFIQ 0x00000001 |
Core FIQ Status.
Definition at line 131 of file at91_aic.h.
| #define AIC_NIRQ 0x00000002 |
Core IRQ Status.
Definition at line 132 of file at91_aic.h.
| #define AIC_IECR_OFF 0x00000120 |
Interrupt enable command register offset.
Definition at line 137 of file at91_aic.h.
| #define AIC_IECR (AIC_BASE + AIC_IECR_OFF) |
Interrupt enable command register address.
Definition at line 138 of file at91_aic.h.
Referenced by AsixInit(), and NutRegisterTimer().
| #define AIC_IDCR_OFF 0x00000124 |
Interrupt disable command register offset.
Definition at line 143 of file at91_aic.h.
| #define AIC_IDCR (AIC_BASE + AIC_IDCR_OFF) |
Interrupt disable command register address.
Definition at line 144 of file at91_aic.h.
Referenced by AsixInit(), and NutRegisterTimer().
| #define AIC_ICCR_OFF 0x00000128 |
Interrupt clear command register offset.
Definition at line 149 of file at91_aic.h.
| #define AIC_ICCR (AIC_BASE + AIC_ICCR_OFF) |
Interrupt clear command register address.
Definition at line 150 of file at91_aic.h.
Referenced by AsixInit(), and NutRegisterTimer().
| #define AIC_ISCR_OFF 0x0000012C |
Interrupt set command register offset.
Definition at line 155 of file at91_aic.h.
| #define AIC_ISCR (AIC_BASE + AIC_ISCR_OFF) |
Interrupt set command register address.
Definition at line 156 of file at91_aic.h.
| #define AIC_EOICR_OFF 0x00000130 |
End of interrupt command register offset.
Definition at line 161 of file at91_aic.h.
| #define AIC_EOICR (AIC_BASE + AIC_EOICR_OFF) |
End of interrupt command register address.
Definition at line 162 of file at91_aic.h.
| #define AIC_SPU_OFF 0x00000134 |
Spurious vector register offset.
Definition at line 167 of file at91_aic.h.
| #define AIC_SPU (AIC_BASE + AIC_SPU_OFF) |
Spurious vector register address.
Definition at line 168 of file at91_aic.h.
Referenced by McuInit().
| #define AIC_DCR_OFF 0x0000138 |
Debug control register offset.
Definition at line 173 of file at91_aic.h.
| #define AIC_DCR (AIC_BASE + AIC_DCR_OFF) |
Debug control register address.
Definition at line 174 of file at91_aic.h.
| #define AIC_FFER_OFF 0x00000140 |
Fast forcing enable register offset.
Definition at line 179 of file at91_aic.h.
| #define AIC_FFER (AIC_BASE + AIC_FFER_OFF) |
Fast forcing enable register address.
Definition at line 180 of file at91_aic.h.
| #define AIC_FFDR_OFF 0x00000144 |
Fast forcing disable register address.
Definition at line 185 of file at91_aic.h.
| #define AIC_FFDR (AIC_BASE + AIC_FFDR_OFF) |
Fast forcing disable register address.
Definition at line 186 of file at91_aic.h.
| #define AIC_FFSR_OFF 0x00000148 |
Fast forcing status register address.
Definition at line 191 of file at91_aic.h.
| #define AIC_FFSR (AIC_BASE + AIC_FFSR_OFF) |
Fast forcing status register address.
Definition at line 192 of file at91_aic.h.