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Nut/OS
4.10.3
API Reference
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Nut/OS
4.10.3
API Reference
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Multimedia card registers. More...
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MMC Control Register | |
| #define | MCI_CR_OFF 0x00000000 |
| Control register offset. | |
| #define | MCI_CR (MCI_BASE + MCI_CR_OFF) |
| Control register address. | |
| #define | MCI_MCIEN 0x00000001 |
| Interface enable. | |
| #define | MCI_MCIDIS 0x00000002 |
| Interface disable. | |
| #define | MCI_PWSEN 0x00000004 |
| Power save mode enable. | |
| #define | MCI_PWSDIS 0x00000008 |
| Power save mode disable. | |
| #define | MCI_SWRST 0x00000080 |
| Software reset. | |
MMC Mode Register | |
| #define | MCI_MR_OFF 0x00000004 |
| Mode register offset. | |
| #define | MCI_MR (MCI_BASE + MCI_MR_OFF) |
| Mode register address. | |
| #define | MCI_CLKDIV 0x000000FF |
| Clock divider mask. | |
| #define | MCI_CLKDIV_LSB 0 |
| Clock divider LSB. | |
| #define | MCI_PWSDIV 0x00000700 |
| Power saving divider mask. | |
| #define | MCI_PWSDIV_LSB 8 |
| Power saving divider LSB. | |
| #define | MCI_RDPROOF 0x00000800 |
| Enable read proof. | |
| #define | MCI_WRPROOF 0x00001000 |
| Enable write proof. | |
| #define | MCI_PDCFBYTE 0x00002000 |
| Force PDC byte transfer. | |
| #define | MCI_PDCPADV 0x00004000 |
| PDC padding value. | |
| #define | MCI_PDCMODE 0x00008000 |
| PDC-oriented mode. | |
| #define | MCI_BLKLEN 0xFFFF0000 |
| Data block length mask. | |
| #define | MCI_BLKLEN_LSB 16 |
| Data block length LSB. | |
MMC Data Timeout Register | |
| #define | MCI_DTOR_OFF 0x00000008 |
| Data timeout register offset. | |
| #define | MCI_DTOR (MCI_BASE + MCI_DTOR_OFF) |
| Data timeout register address. | |
| #define | MCI_DTOCYC 0x0000000F |
| Data timeout cycle number mask. | |
| #define | MCI_DTOCYC_LSB 0 |
| Data timeout cycle number LSB. | |
| #define | MCI_DTOMUL 0x00000070 |
| Data timeout multiplier mask. | |
| #define | MCI_DTOMUL_1 0x00000000 |
| Data timeout multiplier 1. | |
| #define | MCI_DTOMUL_16 0x00000010 |
| Data timeout multiplier 16. | |
| #define | MCI_DTOMUL_128 0x00000020 |
| Data timeout multiplier 128. | |
| #define | MCI_DTOMUL_256 0x00000030 |
| Data timeout multiplier 256. | |
| #define | MCI_DTOMUL_1K 0x00000040 |
| Data timeout multiplier 1024. | |
| #define | MCI_DTOMUL_4K 0x00000050 |
| Data timeout multiplier 4096. | |
| #define | MCI_DTOMUL_64K 0x00000060 |
| Data timeout multiplier 65536. | |
| #define | MCI_DTOMUL_1M 0x00000070 |
| Data timeout multiplier 1048576. | |
MMC SDCard/SDIO Register | |
| #define | MCI_SDCR_OFF 0x0000000C |
| SDC/SDIO register offset. | |
| #define | MCI_SDCR (MCI_BASE + MCI_SDCR_OFF) |
| SDC/SDIO register address. | |
| #define | MCI_SDCSEL 0x00000003 |
| SDC/SDIO slot mask. | |
| #define | MCI_SDCSEL_SLOTA 0x00000000 |
| Slot A selected. | |
| #define | MCI_SDCSEL_SLOTB 0x00000001 |
| Slot B selected. | |
| #define | MCI_SDCBUS 0x00000080 |
| SDC/SDIO 4-bit bus. | |
MMC Argument Register | |
| #define | MCI_ARGR_OFF 0x00000010 |
| Argument register offset. | |
| #define | MCI_ARGR (MCI_BASE + MCI_ARGR_OFF) |
| Argument register address. | |
MMC Command Register | |
| #define | MCI_CMDR_OFF 0x00000014 |
| Command register offset. | |
| #define | MCI_CMDR (MCI_BASE + MCI_CMDR_OFF) |
| Command register address. | |
| #define | MCI_CMDNB 0x0000003F |
| Command number mask. | |
| #define | MCI_CMDNB_LSB 0 |
| Command number LSB. | |
| #define | MCI_RSPTYP 0x000000C0 |
| Response type mask. | |
| #define | MCI_RSPTYP_NONE 0x00000000 |
| No response. | |
| #define | MCI_RSPTYP_48 0x00000040 |
| 48-bit response. | |
| #define | MCI_RSPTYP_136 0x00000080 |
| 136-bit response. | |
| #define | MCI_SPCMD 0x00000700 |
| Special command mask. | |
| #define | MCI_SPCMD_NONE 0x00000000 |
| Not a special command. | |
| #define | MCI_SPCMD_INIT 0x00000100 |
| Initialization command. | |
| #define | MCI_SPCMD_SYNC 0x00000200 |
| Synchronized command. | |
| #define | MCI_SPCMD_ICMD 0x00000400 |
| Interrupt command. | |
| #define | MCI_SPCMD_IRSP 0x00000500 |
| Interrupt response. | |
| #define | MCI_OPDCMD 0x00000800 |
| Open drain command. | |
| #define | MCI_OPCMD MCI_OPDCMD |
| Open drain command. Deprecated spelling. | |
| #define | MCI_MAXLAT 0x00001000 |
| Maximum latency for command to response. | |
| #define | MCI_TRCMD 0x00030000 |
| Transfer command mask. | |
| #define | MCI_TRCMD_NONE 0x00000000 |
| No data transfer. | |
| #define | MCI_TRCMD_START 0x00010000 |
| Start data transfer. | |
| #define | MCI_TRCMD_STOP 0x00020000 |
| Stop data transfer. | |
| #define | MCI_TRDIR 0x00040000 |
| Read transfer. | |
| #define | MCI_TRTYP 0x00380000 |
| Transfer type mask. | |
| #define | MCI_TRTYP_MMC_SBLK 0x00000000 |
| MMC/SDC single block transfer. | |
| #define | MCI_TRTYP_MMC_MBLK 0x00080000 |
| MMC/SDC multiple block transfer. | |
| #define | MCI_TRTYP_MMC_STREAM 0x00100000 |
| MMC stream transfer. | |
| #define | MCI_TRTYP_SDIO_BYTE 0x00200000 |
| SDIO byte transfer. | |
| #define | MCI_TRTYP_SDIO_BLK 0x00280000 |
| SDIO block transfer. | |
| #define | MCI_IOSPCMD 0x03000000 |
| Specila SDIO command mask. | |
| #define | MCI_IOSPCMD_NONE 0x00000000 |
| Not a special SDIO command. | |
| #define | MCI_IOSPCMD_SUSPEND 0x01000000 |
| SDIO suspend command. | |
| #define | MCI_IOSPCMD_RESUME 0x02000000 |
| SDIO resume command. | |
MMC Block Register | |
| #define | MCI_BLKR_OFF 0x00000018 |
| Block register offset. | |
| #define | MCI_BLKR (MCI_BASE + MCI_BLKR_OFF) |
| Block register address. | |
| #define | MCI_BCNT 0x0000FFFF |
| MMC/SDIO block count or SDIO byte count mask. | |
| #define | MCI_BCNT_LSB 0 |
| MMC/SDIO block count or SDIO byte count LSB. | |
MMC Response Register | |
| #define | MCI_RSPR_OFF 0x00000020 |
| Response register offset. | |
| #define | MCI_RSPR (MCI_BASE + MCI_RSPR_OFF) |
| Response register address. | |
MMC Receive Data Register | |
| #define | MCI_RDR_OFF 0x00000030 |
| Receive data register offset. | |
| #define | MCI_RDR (MCI_BASE + MCI_RDR_OFF) |
| Receive data register address. | |
MMC Transmit Data Register | |
| #define | MCI_TDR_OFF 0x00000034 |
| Transmit data register offset. | |
| #define | MCI_TDR (MCI_BASE + MCI_TDR_OFF) |
| Transmit data register address. | |
MMC Interrupt and Status Registers | |
| #define | MCI_SR_OFF 0x00000040 |
| Status register offset. | |
| #define | MCI_SR (MCI_BASE + MCI_SR_OFF) |
| Status register address. | |
| #define | MCI_IER_OFF 0x00000044 |
| Enable register offset. | |
| #define | MCI_IER (MCI_BASE + MCI_IER_OFF) |
| Enable register address. | |
| #define | MCI_IDR_OFF 0x00000048 |
| Disable register offset. | |
| #define | MCI_IDR (MCI_BASE + MCI_IDR_OFF) |
| Disable register address. | |
| #define | MCI_IMR_OFF 0x0000004C |
| Mask register offset. | |
| #define | MCI_IMR (MCI_BASE + MCI_IMR_OFF) |
| Mask register address. | |
| #define | MCI_CMDRDY 0x00000001 |
| Command ready. | |
| #define | MCI_RXRDY 0x00000002 |
| Receiver ready. | |
| #define | MCI_TXRDY 0x00000004 |
| Transmit ready. | |
| #define | MCI_BLKE 0x00000008 |
| Data block ended. | |
| #define | MCI_DTIP 0x00000010 |
| Data transfer in progress. | |
| #define | MCI_NOTBUSY 0x00000020 |
| MCI not busy. | |
| #define | MCI_ENDRX 0x00000040 |
| End of receive buffer. | |
| #define | MCI_ENDTX 0x00000080 |
| End of transmit buffer. | |
| #define | MCI_SDIOIRQA 0x00000100 |
| Undocumented. | |
| #define | MCI_SDIOIRQB 0x00000200 |
| Undocumented. | |
| #define | MCI_RXBUFF 0x00004000 |
| Receive buffer full. | |
| #define | MCI_TXBUFE 0x00008000 |
| Transmit buffer empty. | |
| #define | MCI_RINDE 0x00010000 |
| Response index error. | |
| #define | MCI_RDIRE 0x00020000 |
| Response direction error. | |
| #define | MCI_RCRCE 0x00040000 |
| Response CRC error. | |
| #define | MCI_RENDE 0x00080000 |
| Response end bit error. | |
| #define | MCI_RTOE 0x00100000 |
| Response timeout error. | |
| #define | MCI_DCRCE 0x00200000 |
| Data CRC error. | |
| #define | MCI_DTOE 0x00400000 |
| Date timeout error. | |
| #define | MCI_OVRE 0x40000000 |
| Overrun error. | |
| #define | MCI_UNRE 0x80000000 |
| Underrun error. | |
Multimedia card registers.
| #define MCI_CR_OFF 0x00000000 |
Control register offset.
Definition at line 66 of file at91_mci.h.
| #define MCI_CR (MCI_BASE + MCI_CR_OFF) |
Control register address.
Definition at line 67 of file at91_mci.h.
| #define MCI_MCIEN 0x00000001 |
Interface enable.
Definition at line 68 of file at91_mci.h.
| #define MCI_MCIDIS 0x00000002 |
Interface disable.
Definition at line 69 of file at91_mci.h.
| #define MCI_PWSEN 0x00000004 |
Power save mode enable.
Definition at line 70 of file at91_mci.h.
| #define MCI_PWSDIS 0x00000008 |
Power save mode disable.
Definition at line 71 of file at91_mci.h.
| #define MCI_SWRST 0x00000080 |
Software reset.
Definition at line 72 of file at91_mci.h.
| #define MCI_MR_OFF 0x00000004 |
Mode register offset.
Definition at line 77 of file at91_mci.h.
| #define MCI_MR (MCI_BASE + MCI_MR_OFF) |
Mode register address.
Definition at line 78 of file at91_mci.h.
| #define MCI_CLKDIV 0x000000FF |
Clock divider mask.
Definition at line 79 of file at91_mci.h.
| #define MCI_CLKDIV_LSB 0 |
Clock divider LSB.
Definition at line 80 of file at91_mci.h.
| #define MCI_PWSDIV 0x00000700 |
Power saving divider mask.
Definition at line 81 of file at91_mci.h.
| #define MCI_PWSDIV_LSB 8 |
Power saving divider LSB.
Definition at line 82 of file at91_mci.h.
| #define MCI_RDPROOF 0x00000800 |
Enable read proof.
Definition at line 83 of file at91_mci.h.
| #define MCI_WRPROOF 0x00001000 |
Enable write proof.
Definition at line 84 of file at91_mci.h.
| #define MCI_PDCFBYTE 0x00002000 |
Force PDC byte transfer.
Definition at line 85 of file at91_mci.h.
| #define MCI_PDCPADV 0x00004000 |
PDC padding value.
Definition at line 86 of file at91_mci.h.
| #define MCI_PDCMODE 0x00008000 |
PDC-oriented mode.
Definition at line 87 of file at91_mci.h.
| #define MCI_BLKLEN 0xFFFF0000 |
Data block length mask.
Definition at line 88 of file at91_mci.h.
| #define MCI_BLKLEN_LSB 16 |
Data block length LSB.
Definition at line 89 of file at91_mci.h.
| #define MCI_DTOR_OFF 0x00000008 |
Data timeout register offset.
Definition at line 94 of file at91_mci.h.
| #define MCI_DTOR (MCI_BASE + MCI_DTOR_OFF) |
Data timeout register address.
Definition at line 95 of file at91_mci.h.
| #define MCI_DTOCYC 0x0000000F |
Data timeout cycle number mask.
Definition at line 96 of file at91_mci.h.
| #define MCI_DTOCYC_LSB 0 |
Data timeout cycle number LSB.
Definition at line 97 of file at91_mci.h.
| #define MCI_DTOMUL 0x00000070 |
Data timeout multiplier mask.
Definition at line 98 of file at91_mci.h.
| #define MCI_DTOMUL_1 0x00000000 |
Data timeout multiplier 1.
Definition at line 99 of file at91_mci.h.
| #define MCI_DTOMUL_16 0x00000010 |
Data timeout multiplier 16.
Definition at line 100 of file at91_mci.h.
| #define MCI_DTOMUL_128 0x00000020 |
Data timeout multiplier 128.
Definition at line 101 of file at91_mci.h.
| #define MCI_DTOMUL_256 0x00000030 |
Data timeout multiplier 256.
Definition at line 102 of file at91_mci.h.
| #define MCI_DTOMUL_1K 0x00000040 |
Data timeout multiplier 1024.
Definition at line 103 of file at91_mci.h.
| #define MCI_DTOMUL_4K 0x00000050 |
Data timeout multiplier 4096.
Definition at line 104 of file at91_mci.h.
| #define MCI_DTOMUL_64K 0x00000060 |
Data timeout multiplier 65536.
Definition at line 105 of file at91_mci.h.
| #define MCI_DTOMUL_1M 0x00000070 |
Data timeout multiplier 1048576.
Definition at line 106 of file at91_mci.h.
| #define MCI_SDCR_OFF 0x0000000C |
SDC/SDIO register offset.
Definition at line 111 of file at91_mci.h.
| #define MCI_SDCR (MCI_BASE + MCI_SDCR_OFF) |
SDC/SDIO register address.
Definition at line 112 of file at91_mci.h.
| #define MCI_SDCSEL 0x00000003 |
SDC/SDIO slot mask.
Definition at line 113 of file at91_mci.h.
| #define MCI_SDCSEL_SLOTA 0x00000000 |
Slot A selected.
Definition at line 114 of file at91_mci.h.
| #define MCI_SDCSEL_SLOTB 0x00000001 |
Slot B selected.
Definition at line 115 of file at91_mci.h.
| #define MCI_SDCBUS 0x00000080 |
SDC/SDIO 4-bit bus.
Definition at line 116 of file at91_mci.h.
| #define MCI_ARGR_OFF 0x00000010 |
Argument register offset.
Definition at line 121 of file at91_mci.h.
| #define MCI_ARGR (MCI_BASE + MCI_ARGR_OFF) |
Argument register address.
Definition at line 122 of file at91_mci.h.
| #define MCI_CMDR_OFF 0x00000014 |
Command register offset.
Definition at line 127 of file at91_mci.h.
| #define MCI_CMDR (MCI_BASE + MCI_CMDR_OFF) |
Command register address.
Definition at line 128 of file at91_mci.h.
| #define MCI_CMDNB 0x0000003F |
Command number mask.
Definition at line 129 of file at91_mci.h.
| #define MCI_CMDNB_LSB 0 |
Command number LSB.
Definition at line 130 of file at91_mci.h.
| #define MCI_RSPTYP 0x000000C0 |
Response type mask.
Definition at line 131 of file at91_mci.h.
| #define MCI_RSPTYP_NONE 0x00000000 |
No response.
Definition at line 132 of file at91_mci.h.
| #define MCI_RSPTYP_48 0x00000040 |
48-bit response.
Definition at line 133 of file at91_mci.h.
| #define MCI_RSPTYP_136 0x00000080 |
136-bit response.
Definition at line 134 of file at91_mci.h.
| #define MCI_SPCMD 0x00000700 |
Special command mask.
Definition at line 135 of file at91_mci.h.
| #define MCI_SPCMD_NONE 0x00000000 |
Not a special command.
Definition at line 136 of file at91_mci.h.
| #define MCI_SPCMD_INIT 0x00000100 |
Initialization command.
Definition at line 137 of file at91_mci.h.
| #define MCI_SPCMD_SYNC 0x00000200 |
Synchronized command.
Definition at line 138 of file at91_mci.h.
| #define MCI_SPCMD_ICMD 0x00000400 |
Interrupt command.
Definition at line 139 of file at91_mci.h.
| #define MCI_SPCMD_IRSP 0x00000500 |
Interrupt response.
Definition at line 140 of file at91_mci.h.
| #define MCI_OPDCMD 0x00000800 |
Open drain command.
Definition at line 141 of file at91_mci.h.
| #define MCI_OPCMD MCI_OPDCMD |
Open drain command. Deprecated spelling.
Definition at line 142 of file at91_mci.h.
| #define MCI_MAXLAT 0x00001000 |
Maximum latency for command to response.
Definition at line 143 of file at91_mci.h.
| #define MCI_TRCMD 0x00030000 |
Transfer command mask.
Definition at line 144 of file at91_mci.h.
| #define MCI_TRCMD_NONE 0x00000000 |
No data transfer.
Definition at line 145 of file at91_mci.h.
| #define MCI_TRCMD_START 0x00010000 |
Start data transfer.
Definition at line 146 of file at91_mci.h.
| #define MCI_TRCMD_STOP 0x00020000 |
Stop data transfer.
Definition at line 147 of file at91_mci.h.
| #define MCI_TRDIR 0x00040000 |
Read transfer.
Definition at line 148 of file at91_mci.h.
| #define MCI_TRTYP 0x00380000 |
Transfer type mask.
Definition at line 149 of file at91_mci.h.
| #define MCI_TRTYP_MMC_SBLK 0x00000000 |
MMC/SDC single block transfer.
Definition at line 150 of file at91_mci.h.
| #define MCI_TRTYP_MMC_MBLK 0x00080000 |
MMC/SDC multiple block transfer.
Definition at line 151 of file at91_mci.h.
| #define MCI_TRTYP_MMC_STREAM 0x00100000 |
MMC stream transfer.
Definition at line 152 of file at91_mci.h.
| #define MCI_TRTYP_SDIO_BYTE 0x00200000 |
SDIO byte transfer.
Definition at line 153 of file at91_mci.h.
| #define MCI_TRTYP_SDIO_BLK 0x00280000 |
SDIO block transfer.
Definition at line 154 of file at91_mci.h.
| #define MCI_IOSPCMD 0x03000000 |
Specila SDIO command mask.
Definition at line 155 of file at91_mci.h.
| #define MCI_IOSPCMD_NONE 0x00000000 |
Not a special SDIO command.
Definition at line 156 of file at91_mci.h.
| #define MCI_IOSPCMD_SUSPEND 0x01000000 |
SDIO suspend command.
Definition at line 157 of file at91_mci.h.
| #define MCI_IOSPCMD_RESUME 0x02000000 |
SDIO resume command.
Definition at line 158 of file at91_mci.h.
| #define MCI_BLKR_OFF 0x00000018 |
Block register offset.
Definition at line 163 of file at91_mci.h.
| #define MCI_BLKR (MCI_BASE + MCI_BLKR_OFF) |
Block register address.
Definition at line 164 of file at91_mci.h.
| #define MCI_BCNT 0x0000FFFF |
MMC/SDIO block count or SDIO byte count mask.
Definition at line 165 of file at91_mci.h.
| #define MCI_BCNT_LSB 0 |
MMC/SDIO block count or SDIO byte count LSB.
Definition at line 166 of file at91_mci.h.
| #define MCI_RSPR_OFF 0x00000020 |
Response register offset.
Definition at line 171 of file at91_mci.h.
| #define MCI_RSPR (MCI_BASE + MCI_RSPR_OFF) |
Response register address.
Definition at line 172 of file at91_mci.h.
| #define MCI_RDR_OFF 0x00000030 |
Receive data register offset.
Definition at line 177 of file at91_mci.h.
| #define MCI_RDR (MCI_BASE + MCI_RDR_OFF) |
Receive data register address.
Definition at line 178 of file at91_mci.h.
| #define MCI_TDR_OFF 0x00000034 |
Transmit data register offset.
Definition at line 183 of file at91_mci.h.
| #define MCI_TDR (MCI_BASE + MCI_TDR_OFF) |
Transmit data register address.
Definition at line 184 of file at91_mci.h.
| #define MCI_SR_OFF 0x00000040 |
Status register offset.
Definition at line 189 of file at91_mci.h.
| #define MCI_SR (MCI_BASE + MCI_SR_OFF) |
Status register address.
Definition at line 190 of file at91_mci.h.
| #define MCI_IER_OFF 0x00000044 |
Enable register offset.
Definition at line 192 of file at91_mci.h.
| #define MCI_IER (MCI_BASE + MCI_IER_OFF) |
Enable register address.
Definition at line 193 of file at91_mci.h.
| #define MCI_IDR_OFF 0x00000048 |
Disable register offset.
Definition at line 195 of file at91_mci.h.
| #define MCI_IDR (MCI_BASE + MCI_IDR_OFF) |
Disable register address.
Definition at line 196 of file at91_mci.h.
| #define MCI_IMR_OFF 0x0000004C |
Mask register offset.
Definition at line 198 of file at91_mci.h.
| #define MCI_IMR (MCI_BASE + MCI_IMR_OFF) |
Mask register address.
Definition at line 199 of file at91_mci.h.
| #define MCI_CMDRDY 0x00000001 |
Command ready.
Definition at line 201 of file at91_mci.h.
| #define MCI_RXRDY 0x00000002 |
Receiver ready.
Definition at line 202 of file at91_mci.h.
| #define MCI_TXRDY 0x00000004 |
Transmit ready.
Definition at line 203 of file at91_mci.h.
| #define MCI_BLKE 0x00000008 |
Data block ended.
Definition at line 204 of file at91_mci.h.
| #define MCI_DTIP 0x00000010 |
Data transfer in progress.
Definition at line 205 of file at91_mci.h.
| #define MCI_NOTBUSY 0x00000020 |
MCI not busy.
Definition at line 206 of file at91_mci.h.
| #define MCI_ENDRX 0x00000040 |
End of receive buffer.
Definition at line 207 of file at91_mci.h.
| #define MCI_ENDTX 0x00000080 |
End of transmit buffer.
Definition at line 208 of file at91_mci.h.
| #define MCI_SDIOIRQA 0x00000100 |
Undocumented.
Definition at line 209 of file at91_mci.h.
| #define MCI_SDIOIRQB 0x00000200 |
Undocumented.
Definition at line 210 of file at91_mci.h.
| #define MCI_RXBUFF 0x00004000 |
Receive buffer full.
Definition at line 211 of file at91_mci.h.
| #define MCI_TXBUFE 0x00008000 |
Transmit buffer empty.
Definition at line 212 of file at91_mci.h.
| #define MCI_RINDE 0x00010000 |
Response index error.
Definition at line 213 of file at91_mci.h.
| #define MCI_RDIRE 0x00020000 |
Response direction error.
Definition at line 214 of file at91_mci.h.
| #define MCI_RCRCE 0x00040000 |
Response CRC error.
Definition at line 215 of file at91_mci.h.
| #define MCI_RENDE 0x00080000 |
Response end bit error.
Definition at line 216 of file at91_mci.h.
| #define MCI_RTOE 0x00100000 |
Response timeout error.
Definition at line 217 of file at91_mci.h.
| #define MCI_DCRCE 0x00200000 |
Data CRC error.
Definition at line 218 of file at91_mci.h.
| #define MCI_DTOE 0x00400000 |
Date timeout error.
Definition at line 219 of file at91_mci.h.
| #define MCI_OVRE 0x40000000 |
Overrun error.
Definition at line 220 of file at91_mci.h.
| #define MCI_UNRE 0x80000000 |
Underrun error.
Definition at line 221 of file at91_mci.h.