reg_ax88796.h

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#ifndef _DEV_REG_AX88796_H_
#define _DEV_REG_AX88796_H_


/*
 * Register offset applicable to all register pages.
 */
#define CR 0x00        
#define DATAPORT 0x10  
#define IFGS1 0x12     
#define IFGS2 0x13     
#define MII_EEP 0x14   
#define TR 0x15        
#define IFG 0x16       
#define GPI 0x17       
#define GPOC 0x17      
#define SPP1 0x18      
#define SPP2 0x19      
#define SPP3 0x1a      
#define RESET 0x1f     
/*
 * Page 0 register offsets.
 */
#define PG0_PSTART 0x01   
#define PG0_PSTOP 0x02    
#define PG0_BNRY 0x03     
#define PG0_TSR 0x04      
#define PG0_TPSR 0x04     
#define PG0_NCR 0x05      
#define PG0_TBCR0 0x05    
#define PG0_CPR 0x06      
#define PG0_TBCR1 0x06    
#define PG0_ISR 0x07      
#define PG0_CRDA0 0x08    
#define PG0_RSAR0 0x08    
#define PG0_CRDA1 0x09    
#define PG0_RSAR1 0x09    
#define PG0_RBCR0 0x0a    
#define PG0_RBCR1 0x0b    
#define PG0_RSR 0x0c      
#define PG0_RCR 0x0c      
#define PG0_CNTR0 0x0d    
#define PG0_TCR 0x0d      
#define PG0_DCR 0x0e      
#define PG0_IMR 0x0f      
/*
 * Page 1 register offsets.
 */
#define PG1_PAR0 0x01      
#define PG1_PAR1 0x02      
#define PG1_PAR2 0x03      
#define PG1_PAR3 0x04      
#define PG1_PAR4 0x05      
#define PG1_PAR5 0x06      
#define PG1_CPR 0x07       
#define PG1_MAR0 0x08      
#define PG1_MAR1 0x09      
#define PG1_MAR2 0x0a      
#define PG1_MAR3 0x0b      
#define PG1_MAR4 0x0c      
#define PG1_MAR5 0x0d      
#define PG1_MAR6 0x0e      
#define PG1_MAR7 0x0f      
/*
 * Command register bits. (0x00, Read/Write)
 */
#define CR_STOP 0x01   
#define CR_START 0x02  
#define CR_TXP 0x04    
#define CR_RD0 0x08    
#define CR_RD1 0x10    
#define CR_RD2 0x20    
#define CR_PS0 0x40    
#define CR_PS1 0x80    
/*
 * Interrupt status register bits. (0x07, Read/Write)
 */
#define ISR_PRX 0x01      
#define ISR_PTX 0x02      
#define ISR_RXE 0x04      
#define ISR_TXE 0x08      
#define ISR_OVW 0x10      
#define ISR_CNT 0x20      
#define ISR_RDC 0x40      
#define ISR_RST 0x80      
/*
 * Interrupt mask register bits. (0x0F, Write)
 */
#define IMR_PRXE 0x01     
#define IMR_PTXE 0x02     
#define IMR_RXEE 0x04     
#define IMR_TXEE 0x08     
#define IMR_OVWE 0x10     
#define IMR_CNTE 0x20     
#define IMR_RCDE 0x40     
/*
 * Data configuration register bits. (0x0E, Write)
 */
#define DCR_WTS  0x01     
#define DCR_RDCR 0x80     
/*
 * Transmit configuration register bits. (0x0D, Write)
 */
#define TCR_CRC 0x01      
#define TCR_LB0 0x02      
#define TCR_LB1 0x04      
#define TCR_RLO 0x20      
#define TCR_PD  0x40      
#define TCR_FDU 0x80      
/*
 * Transmit status register bits. (0x04, Read)
 */
#define TSR_PTX 0x01      
#define TSR_COL 0x04      
#define TSR_ABT 0x08      
#define TSR_OWC 0x80      
/*
 * Receive configuration register bits. (0x0C, Write)
 */
#define RCR_SEP 0x01      
#define RCR_AR 0x02       
#define RCR_AB 0x04       
#define RCR_AM 0x08       
#define RCR_PRO 0x10      
#define RCR_MON 0x20      
#define RCR_INTT 0x40     
/*
 * Receive status register bits. (0x0C, Read)
 */
#define RSR_PRX 0x01      
#define RSR_CR 0x02       
#define RSR_FAE 0x04      
#define RSR_FO 0x08       
#define RSR_MPA 0x10      
#define RSR_PHY 0x20      
#define RSR_DIS 0x40      
/*
 * MII/EEPROM access regiser bits. (0x14, Read/Write)
 */
#define MII_EEP_MDC 0x01   
#define MII_EEP_MDIR 0x02  
#define MII_EEP_MDI 0x04   
#define MII_EEP_MDO 0x08   
#define MII_EEP_EECS 0x10  
#define MII_EEP_EEI 0x20   
#define MII_EEP_EEO 0x40   
#define MII_EEP_EECLK 0x80 
/*
 * TR access regiser bits. (0x15, Read/Write)
 */
#define TR_RST_B 0x02 
/*
 * The Asix Embedded PHY Registers
 */

#define PHY_MR0  0x00   
#define PHY_MR1  0x01   
#define PHY_MR2  0x02   
#define PHY_MR3  0x03   
#define PHY_MR4  0x04   
#define PHY_MR5  0x05   
#define PHY_MR6  0x06   
#define PHY_MR7  0x07   
#define PHY_MR16 0x10   
#define PHY_MR17 0x11   
#define PHY_MR18 0x12   
#define PHY_MR19 0x13   
#define PHY_MR20 0x14   
#define PHY_MR21 0x15   
#define PHY_MR22 0x16   
#define PHY_MR23 0x17   
#define PHY_MR24 0x18   
#define PHY_MR25 0x19   
#define PHY_MR26 0x1a   
#define PHY_MR27 0x1b   
#define PHY_MR28 0x1c   
#define PHY_MR29 0x1d   
#define PHY_MR30 0x1e   
#define PHY_MR31 0x1f   
/*
 * PHY MR0 (Control) access regiser bits.
 */
#define MR0_SW_RESET    0x8000  /* R/W Reset, all PHY registers will be set to default */
#define MR0_LOOPBACK    0x4000  /* R/W Loopback */
#define MR0_SPEED100    0x2000  /* R/W Speed selection, 1 = 100Mbits/s, 0 = 10Mbits/s */
#define MR0_NWAY_ENA    0x1000  /* R/W Autonegotiation Enable */
#define MR0_PWRDN               0x0800  /* R/W Powerdown */
#define MR0_ISOLATE             0x0400  /* R/W Isolate */
#define MR0_REDONWAY    0x0200  /* R/W Restart autonegotiation */
#define MR0_FULL_DUP    0x0100  /* R/W Duplex mode selection, 1 = FULL, 0 = HALF */
#define MR0_COLTST              0x0080  /* R/W Collision Test */

/*
 * PHY MR1 (Status) access regiser bits.
 */
#define MR1_T4ABLE              0x8000  /* R 100Base-T4 Ability. This bit will always be a 0 */
#define MR1_TXFULDUP    0x4000  /* R 100Base-TX Full-Duplex Ability. This bit will always be a 1 */
#define MR1_TXHAFDUP    0x2000  /* R 100Base-TX Half-Duplex Ability. This bit will always be a 1 */
#define MR1_ENFULDUP    0x1000  /* R 10Base-T Full-Duplex Ability. This bit will always be a 1 */
#define MR1_ENHAFDUP    0x0800  /* R 10Base-T Half-Duplex Ability. This bit will always be a 1 */
#define MR1_NO_PA_OK    0x0040  /* R Suppress preamble */
#define MR1_NWAYDONE    0x0020  /* R Autonegotiation complete */
#define MR1_REM_FLT             0x0010  /* R Remote fault */
#define MR1_NWAYABLE    0x0008  /* R Autonegotiation ability */
#define MR1_LSTAT_OK    0x0004  /* R Link status */
#define MR1_JABBER              0x0002  /* R Jabber detect */
#define MR1_EXT_ABLE    0x0001  /* R Extended capability */


/*
 * PHY MR31 (Quick Status) access regiser bits.
 */
#define MR31_LSTAT_OK   0x0800  /* R Link status */
#define MR31_SPEED100   0x0200  /* R Link Speed, 0=10Mbits/s, 1=100Mbits/s */
#define MR31_FULL_DUP   0x0100  /* R Duplex Mode, 0=Half, 1=Full */


/*
0x8000  15
0x4000  14
0x2000  13
0x1000  12
0x0800  11
0x0400  10
0x0200  9
0x0100  8
0x0080  7
0x0040  6
0x0020  5
0x0010  4
0x0008  3
0x0004  2
0x0002  1
0x0001  0

*/

#endif