Nut/OS  4.10.3
API Reference
usartDat91.c
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00001 /*
00002  * Copyright (C) 2005 by egnite Software GmbH. All rights reserved.
00003  *
00004  * Redistribution and use in source and binary forms, with or without
00005  * modification, are permitted provided that the following conditions
00006  * are met:
00007  *
00008  * 1. Redistributions of source code must retain the above copyright
00009  *    notice, this list of conditions and the following disclaimer.
00010  * 2. Redistributions in binary form must reproduce the above copyright
00011  *    notice, this list of conditions and the following disclaimer in the
00012  *    documentation and/or other materials provided with the distribution.
00013  * 3. Neither the name of the copyright holders nor the names of
00014  *    contributors may be used to endorse or promote products derived
00015  *    from this software without specific prior written permission.
00016  *
00017  * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
00018  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00019  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00020  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
00021  * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
00022  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
00023  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
00024  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
00025  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00026  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
00027  * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
00028  * SUCH DAMAGE.
00029  *
00030  * For additional information see http://www.ethernut.de/
00031  */
00032 
00033 /*
00034  * $Log$
00035  * Revision 0.01  2009/09/20 ulrichprinz
00036  * First checkin of using DBGU as limited standard USART.
00037  *
00038  */
00039 
00040 #define NUT_DEPRECATED
00041 
00042 #include <cfg/os.h>
00043 #include <cfg/clock.h>
00044 #include <cfg/arch.h>
00045 #include <cfg/uart.h>
00046 
00047 #include <string.h>
00048 
00049 #include <sys/atom.h>
00050 #include <sys/event.h>
00051 #include <sys/timer.h>
00052 
00053 #include <dev/irqreg.h>
00054 #include <dev/debug.h>
00055 #include <arch/arm/atmel/at91_dbgu.h>
00056 #include <dev/usartat91.h>
00057 
00058 #ifndef NUT_CPU_FREQ
00059 #ifdef NUT_PLL_CPUCLK
00060 #include <dev/cy2239x.h>
00061 #else /* !NUT_PLL_CPUCLK */
00062 #define NUT_CPU_FREQ    73728000UL
00063 #endif /* !NUT_PLL_CPUCLK */
00064 #endif /* !NUT_CPU_FREQ */
00065 
00066 /*
00067  * Local function prototypes.
00068  *
00069  * Commented functions are not supported by DBGU
00070  *
00071  */
00072 static uint32_t At91UsartGetSpeed(void);
00073 static int At91UsartSetSpeed(uint32_t rate);
00074 static uint8_t At91UsartGetDataBits(void);
00075 static int At91UsartSetDataBits( uint8_t bits);
00076 static uint8_t At91UsartGetParity(void);
00077 static int At91UsartSetParity(uint8_t mode);
00078 static uint8_t At91UsartGetStopBits(void);
00079 static int At91UsartSetStopBits(uint8_t bits);
00080 static uint32_t At91UsartGetStatus(void);
00081 static int At91UsartSetStatus(uint32_t flags);
00082 static uint8_t At91UsartGetClockMode(void);
00083 static int At91UsartSetClockMode(uint8_t mode);
00084 static void At91UsartTxStart(void);
00085 static void At91UsartRxStart(void);
00086 static int At91UsartInit(void);
00087 static int At91UsartDeinit(void);
00088 static uint32_t At91UsartGetFlowControl(void);
00089 static int At91UsartSetFlowControl(uint32_t flags);
00090 
00091 extern IRQ_HANDLER sig_DBGU;
00092 
00097 
00101 static USARTDCB dcb_dbgu = {
00102     0,                          /* dcb_modeflags */
00103     0,                          /* dcb_statusflags */
00104     0,                          /* dcb_rtimeout */
00105     0,                          /* dcb_wtimeout */
00106     {0, 0, 0, 0, 0, 0, 0, 0},   /* dcb_tx_rbf */
00107     {0, 0, 0, 0, 0, 0, 0, 0},   /* dcb_rx_rbf */
00108     0,                          /* dbc_last_eol */
00109     At91UsartInit,              /* dcb_init */
00110     At91UsartDeinit,            /* dcb_deinit */
00111     At91UsartTxStart,           /* dcb_tx_start */
00112     At91UsartRxStart,           /* dcb_rx_start */
00113     At91UsartSetFlowControl,    /* dcb_set_flow_control */
00114     At91UsartGetFlowControl,    /* dcb_get_flow_control */
00115     At91UsartSetSpeed,          /* dcb_set_speed */
00116     At91UsartGetSpeed,          /* dcb_get_speed */
00117     At91UsartSetDataBits,       /* dcb_set_data_bits */
00118     At91UsartGetDataBits,       /* dcb_get_data_bits */
00119     At91UsartSetParity,         /* dcb_set_parity */
00120     At91UsartGetParity,         /* dcb_get_parity */
00121     At91UsartSetStopBits,       /* dcb_set_stop_bits */
00122     At91UsartGetStopBits,       /* dcb_get_stop_bits */
00123     At91UsartSetStatus,         /* dcb_set_status */
00124     At91UsartGetStatus,         /* dcb_get_status */
00125     At91UsartSetClockMode,      /* dcb_set_clock_mode */
00126     At91UsartGetClockMode,      /* dcb_get_clock_mode */
00127 };
00128 
00144 NUTDEVICE devDbguAt91 = {
00145     0,                          /* Pointer to next device, dev_next. */
00146     {'u', 'a', 'r', 't', 'd', 0, 0, 0, 0},    /* Unique device name, dev_name. */
00147     IFTYP_CHAR,                 /* Type of device, dev_type. */
00148     DBGU_BASE,                  /* Base address, dev_base (not used). */
00149     0,                          /* First interrupt number, dev_irq (not used). */
00150     0,                          /* Interface control block, dev_icb (not used). */
00151     &dcb_dbgu,                  /* Driver control block, dev_dcb. */
00152     UsartInit,                  /* Driver initialization routine, dev_init. */
00153     UsartIOCtl,                 /* Driver specific control function, dev_ioctl. */
00154     UsartRead,                  /* Read from device, dev_read. */
00155     UsartWrite,                 /* Write to device, dev_write. */
00156     UsartOpen,                  /* Open a device or file, dev_open. */
00157     UsartClose,                 /* Close a device or file, dev_close. */
00158     UsartSize                   /* Request file size, dev_size. */
00159 };
00160 
00164 
00165 /* Modem control includes hardware handshake. */
00166 /*
00167  * Hardware driven control signals are not available
00168  * with the DBUG unit of most chips.
00169  */
00170 
00171 #undef UART_MODEM_CONTROL
00172 #undef UART_HARDWARE_HANDSHAKE
00173 
00174 #if defined(UART_MODEM_CONTROL)
00175 #define UART_MODEM_CONTROL
00176 #define UART_HARDWARE_HANDSHAKE
00177 #elif defined(UART_HARDWARE_HANDSHAKE)
00178 #define UART_HARDWARE_HANDSHAKE
00179 #endif
00180 
00181 /*
00182 ** SAM9260 and SAM9XE pins.
00183 */
00184 #if defined(MCU_AT91SAM9260) || defined(MCU_AT91SAM9XE)
00185 
00186 #define UART_RXTX_PINS  (_BV(PB14_DRXD_A) | _BV(PB15_DTXD_A))
00187 #undef UART_HDX_PIN
00188 #undef UART_RTS_PIN
00189 #undef UART_CTS_PIN
00190 #undef UART_MODEM_PINS
00191 
00192 #define UART_RXTX_PINS_ENABLE()     outr(PIOB_ASR, UART_RXTX_PINS); \
00193                                     outr(PIOB_PDR, UART_RXTX_PINS)
00194 
00195 #if defined(UART_HARDWARE_HANDSHAKE)
00196 #define UART_HDX_PIN_ENABLE()       outr(PIOB_ASR, UART_HDX_PIN); \
00197                                     outr(PIOB_PDR, UART_HDX_PIN)
00198 #define UART_RTS_PIN_ENABLE()       outr(PIOB_ASR, UART_RTS_PIN); \
00199                                     outr(PIOB_PDR, UART_RTS_PIN)
00200 #define UART_CTS_PIN_ENABLE()       outr(PIOB_ASR, UART_CTS_PIN); \
00201                                     outr(PIOB_PDR, UART_CTS_PIN)
00202 #endif
00203 
00204 #if defined(UART_MODEM_CONTROL)
00205 #define UART_MODEM_PINS_ENABLE()    outr(PIOB_ASR, UART_MODEM_PINS); \
00206                                     outr(PIOB_PDR, UART_MODEM_PINS)
00207 #endif
00208 
00209 /*
00210 ** SAM7S and SAM7SE pins.
00211 */
00212 #elif defined(MCU_AT91SAM7S) || defined(MCU_AT91SAM7SE)
00213 
00214 #define UART_RXTX_PINS  (_BV(PA9_DRXD_A) | _BV(PA10_DTXD_A))
00215 #undef UART_HDX_PIN
00216 #undef UART_RTS_PIN
00217 #undef UART_CTS_PIN
00218 
00219 #define UART_RXTX_PINS_ENABLE() outr(PIOA_ASR, UART_RXTX_PINS); \
00220                                 outr(PIOA_PDR, UART_RXTX_PINS)
00221 
00222 #if defined(UART_HARDWARE_HANDSHAKE)
00223 #define UART_HDX_PIN_ENABLE()   outr(PIOA_ASR, UART_HDX_PIN); \
00224                                 outr(PIOA_PDR, UART_HDX_PIN)
00225 #define UART_RTS_PIN_ENABLE()   outr(PIOA_ASR, UART_RTS_PIN); \
00226                                 outr(PIOA_PDR, UART_RTS_PIN)
00227 #define UART_CTS_PIN_ENABLE()   outr(PIOA_ASR, UART_CTS_PIN); \
00228                                 outr(PIOA_PDR, UART_CTS_PIN)
00229 #endif
00230 
00231 /*
00232 ** SAM7X pins.
00233 */
00234 #elif defined(MCU_AT91SAM7X)
00235 
00236 #define UART_RXTX_PINS  (_BV(PA27_DRXD_A) | _BV(PA28_DTXD_A))
00237 #undef UART_HDX_PIN
00238 #undef UART_RTS_PIN
00239 #undef UART_CTS_PIN
00240 
00241 #define UART_RXTX_PINS_ENABLE() outr(PIOA_ASR, UART_RXTX_PINS); \
00242                                 outr(PIOA_PDR, UART_RXTX_PINS)
00243 
00244 #if defined(UART_HARDWARE_HANDSHAKE)
00245 #define UART_HDX_PIN_ENABLE()   outr(PIOA_ASR, UART_HDX_PIN); \
00246                                 outr(PIOA_PDR, UART_HDX_PIN)
00247 #define UART_RTS_PIN_ENABLE()   outr(PIOA_ASR, UART_RTS_PIN); \
00248                                 outr(PIOA_PDR, UART_RTS_PIN)
00249 #define UART_CTS_PIN_ENABLE()   outr(PIOA_ASR, UART_CTS_PIN); \
00250                                 outr(PIOA_PDR, UART_CTS_PIN)
00251 #endif
00252 #endif
00253 
00254 /*
00255 ** CPLD logic, currently used on Ethernut 3 only.
00256 */
00257 #if defined(ETHERNUT3)
00258 #define UART_USES_NPL   1
00259 #endif
00260 
00261 /*
00262 ** Determine the CTS GPIO interrupt, based on the port ID.
00263 */
00264 #if defined(UART0_CTS_BIT) && !defined(UART0_CTS_SIGNAL)
00265 #if UART0_CTS_PIO_ID == PIOA_ID
00266 #define UART0_CTS_SIGNAL    sig_GPIO1
00267 #elif UART0_CTS_PIO_ID == PIOB_ID
00268 #define UART0_CTS_SIGNAL    sig_GPIO2
00269 #elif UART0_CTS_PIO_ID == PIOC_ID
00270 #define UART0_CTS_SIGNAL    sig_GPIO3
00271 #else
00272 #define UART0_CTS_SIGNAL    sig_GPIO
00273 #endif
00274 #endif
00275 
00276 /*
00277 ** Translate all macros for UART0 to generalized ones used by the
00278 ** source that will be included at the end of this file.
00279 */
00280 #if defined(UARTD_HDX_BIT)
00281 #define UART_HDX_BIT    UARTD_HDX_BIT
00282 #endif
00283 #if defined(UARTD_HDX_PIO_ID)
00284 #define UART_HDX_PIO_ID UARTD_HDX_PIO_ID
00285 #endif
00286 
00287 #if defined(UARTD_RTS_BIT)
00288 #define UART_RTS_BIT    UARTD_RTS_BIT
00289 #endif
00290 #if defined(UARTD_RTS_PIO_ID)
00291 #define UART_RTS_PIO_ID UARTD_RTS_PIO_ID
00292 #endif
00293 
00294 #if defined(UARTD_CTS_BIT)
00295 #define UART_CTS_BIT    UARTD_CTS_BIT
00296 #endif
00297 #if defined(UARTD_CTS_PIO_ID)
00298 #define UART_CTS_PIO_ID UARTD_CTS_PIO_ID
00299 #endif
00300 #if defined(UARTD_CTS_SIGNAL)
00301 #define UART_CTS_SIGNAL UARTD_CTS_SIGNAL
00302 #endif
00303 
00304 #if defined(UARTD_INIT_BAUDRATE)
00305 #define UART_INIT_BAUDRATE  UARTD_INIT_BAUDRATE
00306 #endif
00307 
00308 #define USARTn_BASE     DBGU_BASE
00309 #define US_ID           SYSC_ID
00310 #define SIG_UART        syssig_DBGU
00311 #define dcb_usart       dcb_dbgu
00312 
00313 #include "usartat91.c"