 |
Nut/OS
4.10.3
API Reference
|
|
|
Nut/OS
4.10.3
API Reference
|
|
#include <arch/arm/atmel/at91_tc.h>#include <arch/arm/atmel/at91_pwmc.h>#include <arch/arm/atmel/at91_us.h>#include <arch/arm/atmel/at91_dbgu.h>#include <arch/arm/atmel/at91_spi.h>#include <arch/arm/atmel/at91_aic.h>#include <arch/arm/atmel/at91_pio.h>#include <arch/arm/atmel/at91_pmc.h>#include <arch/arm/atmel/at91_rstc.h>#include <arch/arm/atmel/at91_wdt.h>#include <arch/arm/atmel/at91_pit.h>#include <arch/arm/atmel/at91_mc.h>#include <arch/arm/atmel/at91_ssc.h>#include <arch/arm/atmel/at91_twi.h>#include <arch/arm/atmel/at91_adc.h>
Go to the source code of this file.
Defines | |
| #define | FLASH_BASE 0x100000UL |
| #define | RAM_BASE 0x200000UL |
| #define | TC_BASE 0xFFFA0000 |
| Timer/counter base address. | |
| #define | UDP_BASE 0xFFFB0000 |
| USB device port base address. | |
| #define | TWI_BASE 0xFFFB8000 |
| Two-wire interface base address. | |
| #define | USART0_BASE 0xFFFC0000 |
| USART 0 base address. | |
| #define | USART1_BASE 0xFFFC4000 |
| USART 1 base address. | |
| #define | PWMC_BASE 0xFFFCC000 |
| PWM controller base address. | |
| #define | SSC_BASE 0xFFFD4000 |
| Serial synchronous controller base address. | |
| #define | ADC_BASE 0xFFFD8000 |
| ADC base address. | |
| #define | SPI0_BASE 0xFFFE0000 |
| SPI0 base address. | |
| #define | AIC_BASE 0xFFFFF000 |
| AIC base address. | |
| #define | DBGU_BASE 0xFFFFF200 |
| DBGU base address. | |
| #define | PIOA_BASE 0xFFFFF400 |
| PIO A base address. | |
| #define | PMC_BASE 0xFFFFFC00 |
| PMC base address. | |
| #define | RSTC_BASE 0xFFFFFD00 |
| Resect controller register base address. | |
| #define | RTT_BASE 0xFFFFFD20 |
| Realtime timer base address. | |
| #define | PIT_BASE 0xFFFFFD30 |
| Periodic interval timer base address. | |
| #define | WDT_BASE 0xFFFFFD40 |
| Watch Dog register base address. | |
| #define | VREG_BASE 0xFFFFFD60 |
| Voltage regulator mode controller base address. | |
| #define | MC_BASE 0xFFFFFF00 |
| Memory controller base. | |
| #define | PERIPH_RPR_OFF 0x00000100 |
| Receive pointer register offset. | |
| #define | PERIPH_RCR_OFF 0x00000104 |
| Receive counter register offset. | |
| #define | PERIPH_TPR_OFF 0x00000108 |
| Transmit pointer register offset. | |
| #define | PERIPH_TCR_OFF 0x0000010C |
| Transmit counter register offset. | |
| #define | PERIPH_RNPR_OFF 0x00000110 |
| Receive next pointer register offset. | |
| #define | PERIPH_RNCR_OFF 0x00000114 |
| Receive next counter register offset. | |
| #define | PERIPH_TNPR_OFF 0x00000118 |
| Transmit next pointer register offset. | |
| #define | PERIPH_TNCR_OFF 0x0000011C |
| Transmit next counter register offset. | |
| #define | PERIPH_PTCR_OFF 0x00000120 |
| PDC transfer control register offset. | |
| #define | PERIPH_PTSR_OFF 0x00000124 |
| PDC transfer status register offset. | |
| #define | PDC_RXTEN 0x00000001 |
| Receiver transfer enable. | |
| #define | PDC_RXTDIS 0x00000002 |
| Receiver transfer disable. | |
| #define | PDC_TXTEN 0x00000100 |
| Transmitter transfer enable. | |
| #define | PDC_TXTDIS 0x00000200 |
| Transmitter transfer disable. | |
| #define | DBGU_HAS_PDC |
| #define | SPI_HAS_PDC |
| #define | SSC_HAS_PDC |
| #define | USART_HAS_PDC |
| #define | USART_HAS_MODE |
| #define | PIO_HAS_MULTIDRIVER |
| #define | PIO_HAS_PULLUP |
| #define | PIO_HAS_PERIPHERALSELECT |
| #define | PIO_HAS_OUTPUTWRITEENABLE |
Peripheral Identifiers and Interrupts | |
| #define | FIQ_ID 0 |
| Fast interrupt ID. | |
| #define | SYSC_ID 1 |
| System interrupt ID. | |
| #define | PIOA_ID 2 |
| Parallel I/O controller ID. | |
| #define | ADC_ID 4 |
| Analog to digital converter ID. | |
| #define | SPI0_ID 5 |
| Serial peripheral interface 0 ID. | |
| #define | US0_ID 6 |
| USART 0 ID. | |
| #define | US1_ID 7 |
| USART 1 ID. | |
| #define | SSC_ID 8 |
| Synchronous serial controller ID. | |
| #define | TWI_ID 9 |
| Two-wire interface ID. | |
| #define | PWMC_ID 10 |
| PWM controller ID. | |
| #define | UDP_ID 11 |
| USB device port ID. | |
| #define | TC0_ID 12 |
| Timer 0 ID. | |
| #define | TC1_ID 13 |
| Timer 1 ID. | |
| #define | TC2_ID 14 |
| Timer 2 ID. | |
| #define | IRQ0_ID 30 |
| External interrupt 0 ID. | |
| #define | IRQ1_ID 31 |
| External interrupt 1 ID. | |
Historical SPI0 Peripheral Multiplexing Names | |
| #define | SPI0_NPCS0_PA11A 11 |
| Port bit number on PIO-A Perpheral A. | |
| #define | SPI0_NPCS1_PA09B 9 |
| Port bit number on PIO-A Perpheral B. | |
| #define | SPI0_NPCS1_PA31A 31 |
| Port bit number on PIO-A Perpheral A. | |
| #define | SPI0_NPCS2_PA10B 10 |
| Port bit number on PIO-A Perpheral B. | |
| #define | SPI0_NPCS2_PA30B 30 |
| Port bit number on PIO-A Perpheral B. | |
| #define | SPI0_NPCS3_PA03B 3 |
| Port bit number on PIO-A Perpheral B. | |
| #define | SPI0_NPCS3_PA05B 5 |
| Port bit number on PIO-A Perpheral B. | |
| #define | SPI0_NPCS3_PA22B 22 |
| Port bit number on PIO-A Perpheral B. | |
| #define | SPI0_MISO_PA12A 12 |
| Port bit number on PIO-A Perpheral A. | |
| #define | SPI0_MOSI_PA13A 13 |
| Port bit number on PIO-A Perpheral A. | |
| #define | SPI0_SPCK_PA14A 14 |
| Port bit number on PIO-A Perpheral A. | |
USART Peripheral Multiplexing | |
| #define | PA5_RXD0_A 5 |
| #define | PA6_TXD0_A 6 |
| #define | PA2_SCK0_B 2 |
| #define | PA7_RTS0_A 7 |
| #define | PA8_CTS0_A 8 |
| #define | PA21_RXD1_A 21 |
| #define | PA22_TXD1_A 22 |
| #define | PA23_SCK1_A 23 |
| #define | PA24_RTS1_A 24 |
| #define | PA25_CTS1_A 25 |
| #define | PB26_DCD1_A 26 |
| #define | PB28_DSR1_A 28 |
| #define | PB27_DTR1_A 27 |
| #define | PB29_RI1_A 29 |
SPI Peripheral Multiplexing | |
| #define | PA12_SPI0_MISO_A 12 |
| #define | PA13_SPI0_MOSI_A 13 |
| #define | PA14_SPI0_SPCK_A 14 |
| #define | PA11_SPI0_NPCS0_A 11 |
| #define | PA9_SPI0_NPCS1_B 9 |
| #define | PA31_SPI0_NPCS1_A 31 |
| #define | PA10_SPI0_NPCS2_B 10 |
| #define | PB30_SPI0_NPCS2_B 30 |
| #define | PA3_SPI0_NPCS3_B 3 |
| #define | PA5_SPI0_NPCS3_B 5 |
| #define | PA22_SPI0_NPCS3_B 22 |
| #define | SPI0_PINS _BV(PA12_SPI0_MISO_A) | _BV(PA13_SPI0_MOSI_A) | _BV(PA14_SPI0_SPCK_A) |
| #define | SPI0_PIO_BASE PIOA_BASE |
| #define | SPI0_PSR_OFF PIO_ASR_OFF |
| #define | SPI0_CS0_PIN _BV(PA11_SPI0_NPCS0_A) |
| #define | SPI0_CS0_PIO_BASE PIOA_BASE |
| #define | SPI0_CS0_PSR_OFF PIO_ASR_OFF |
| #define | SPI0_CS1_PIN _BV(PA9_SPI0_NPCS1_B) |
| #define | SPI0_CS1_PIO_BASE PIOA_BASE |
| #define | SPI0_CS1_PSR_OFF PIO_ASR_OFF |
| #define | SPI0_CS2_PIN _BV(PA10_SPI0_NPCS2_B) |
| #define | SPI0_CS2_PIO_BASE PIOA_BASE |
| #define | SPI0_CS2_PSR_OFF PIO_ASR_OFF |
| #define | SPI0_CS3_PIN _BV(PA3_SPI0_NPCS3_B) |
| #define | SPI0_CS3_PIO_BASE PIOA_BASE |
| #define | SPI0_CS3_PSR_OFF PIO_ASR_OFF |
Debug Unit Peripheral Multiplexing | |
| #define | PA9_DRXD_A 9 |
| #define | PA10_DTXD_A 10 |
Synchronous Serial Controller Peripheral Multiplexing | |
| #define | PA17_TD_A 17 |
| Transmit data pin. | |
| #define | PA18_RD_A 18 |
| Receive data pin. | |
| #define | PA16_TK_A 16 |
| Transmit clock pin. | |
| #define | PA19_RK_A 19 |
| Receive clock pin. | |
| #define | PA15_TF_A 15 |
| Transmit frame sync. pin. | |
| #define | PA20_RF_A 20 |
| Receive frame sync. pin. | |
Two Wire Interface Peripheral Multiplexing | |
| #define | PA3_TWD_A 3 |
| Two wire serial data pin. | |
| #define | PA4_TWCK_A 4 |
| Two wire serial clock pin. | |
Timer/Counter Peripheral Multiplexing | |
| #define | PA0_TIOA0_B 0 |
| #define | PA1_TIOB0_B 1 |
| #define | PA4_TCLK0_B 4 |
| #define | PA15_TIOA1_B 15 |
| #define | PA16_TIOB1_B 16 |
| #define | PA28_TCLK1_B 28 |
| #define | PA26_TIOA2_B 26 |
| #define | PA27_TIOB2_B 27 |
| #define | PA29_TCLK2_B 29 |
Clocks, Oscillators and PLLs Peripheral Multiplexing | |
| #define | PA6_PCK0_B 6 |
| #define | PA17_PCK1_B 17 |
| #define | PA21_PCK1_B 21 |
| #define | PA18_PCK2_B 18 |
| #define | PA31_PCK2_B 31 |
Advanced Interrupt Controller Peripheral Multiplexing | |
| #define | PA19_FIQ_B 19 |
| #define | PA20_IRQ0_B 20 |
| #define | PA30_IRQ1_A 30 |
ADC Interface Peripheral Multiplexing | |
| #define | PA8_ADTRG_B 8 |
| ADC trigger pin. | |
PWM Peripheral Multiplexing | |
| #define | PA0_PWM0_A 0 |
| #define | PA23_PWM0_B 23 |
| #define | PA1_PWM1_A 1 |
| #define | PA24_PWM1_B 24 |
| #define | PA2_PWM2_A 2 |
| #define | PA13_PWM2_B 13 |
| #define | PA25_PWM2_B 25 |
| #define | PA7_PWM3_B 7 |
| #define | PA14_PWM3_B 14 |
| #define FLASH_BASE 0x100000UL |
Definition at line 54 of file at91sam7s.h.
| #define RAM_BASE 0x200000UL |
Definition at line 55 of file at91sam7s.h.
| #define TC_BASE 0xFFFA0000 |
Timer/counter base address.
Definition at line 57 of file at91sam7s.h.
| #define UDP_BASE 0xFFFB0000 |
USB device port base address.
Definition at line 58 of file at91sam7s.h.
| #define TWI_BASE 0xFFFB8000 |
Two-wire interface base address.
Definition at line 59 of file at91sam7s.h.
| #define USART0_BASE 0xFFFC0000 |
USART 0 base address.
Definition at line 60 of file at91sam7s.h.
| #define USART1_BASE 0xFFFC4000 |
USART 1 base address.
Definition at line 61 of file at91sam7s.h.
Referenced by AhdlcAt91Init(), AhdlcAt91IOCtl(), and AhdlcAt91Open().
| #define PWMC_BASE 0xFFFCC000 |
PWM controller base address.
Definition at line 62 of file at91sam7s.h.
| #define SSC_BASE 0xFFFD4000 |
Serial synchronous controller base address.
Definition at line 63 of file at91sam7s.h.
| #define ADC_BASE 0xFFFD8000 |
ADC base address.
Definition at line 64 of file at91sam7s.h.
| #define SPI0_BASE 0xFFFE0000 |
SPI0 base address.
Definition at line 65 of file at91sam7s.h.
Referenced by At91Spi0Init(), At91SpiInit(), At91SpiInitChipSelects(), At91SpiTransfer2(), Avr32Spi0Init(), and ShowHardwareConfiguration().
| #define AIC_BASE 0xFFFFF000 |
AIC base address.
Definition at line 67 of file at91sam7s.h.
| #define DBGU_BASE 0xFFFFF200 |
DBGU base address.
Definition at line 68 of file at91sam7s.h.
| #define PIOA_BASE 0xFFFFF400 |
PIO A base address.
Definition at line 69 of file at91sam7s.h.
| #define PMC_BASE 0xFFFFFC00 |
PMC base address.
Definition at line 70 of file at91sam7s.h.
| #define RSTC_BASE 0xFFFFFD00 |
Resect controller register base address.
Definition at line 71 of file at91sam7s.h.
| #define RTT_BASE 0xFFFFFD20 |
Realtime timer base address.
Definition at line 72 of file at91sam7s.h.
| #define PIT_BASE 0xFFFFFD30 |
Periodic interval timer base address.
Definition at line 73 of file at91sam7s.h.
| #define WDT_BASE 0xFFFFFD40 |
Watch Dog register base address.
Definition at line 74 of file at91sam7s.h.
| #define VREG_BASE 0xFFFFFD60 |
Voltage regulator mode controller base address.
Definition at line 75 of file at91sam7s.h.
| #define MC_BASE 0xFFFFFF00 |
Memory controller base.
Definition at line 76 of file at91sam7s.h.
| #define PERIPH_RPR_OFF 0x00000100 |
Receive pointer register offset.
Definition at line 78 of file at91sam7s.h.
Referenced by AhdlcAt91Init(), and At91SpiTransfer2().
| #define PERIPH_RCR_OFF 0x00000104 |
Receive counter register offset.
Definition at line 79 of file at91sam7s.h.
Referenced by AhdlcAt91Init(), and At91SpiTransfer2().
| #define PERIPH_TPR_OFF 0x00000108 |
Transmit pointer register offset.
Definition at line 80 of file at91sam7s.h.
Referenced by At91SpiTransfer2().
| #define PERIPH_TCR_OFF 0x0000010C |
Transmit counter register offset.
Definition at line 81 of file at91sam7s.h.
Referenced by At91SpiTransfer2().
| #define PERIPH_RNPR_OFF 0x00000110 |
Receive next pointer register offset.
Definition at line 82 of file at91sam7s.h.
Referenced by AhdlcAt91Init(), and At91SpiTransfer2().
| #define PERIPH_RNCR_OFF 0x00000114 |
Receive next counter register offset.
Definition at line 83 of file at91sam7s.h.
Referenced by AhdlcAt91Init(), and At91SpiTransfer2().
| #define PERIPH_TNPR_OFF 0x00000118 |
Transmit next pointer register offset.
Definition at line 84 of file at91sam7s.h.
Referenced by At91SpiTransfer2().
| #define PERIPH_TNCR_OFF 0x0000011C |
Transmit next counter register offset.
Definition at line 85 of file at91sam7s.h.
Referenced by At91SpiTransfer2().
| #define PERIPH_PTCR_OFF 0x00000120 |
PDC transfer control register offset.
Definition at line 86 of file at91sam7s.h.
Referenced by AhdlcAt91Init(), AhdlcAt91Open(), and At91SpiTransfer2().
| #define PERIPH_PTSR_OFF 0x00000124 |
PDC transfer status register offset.
Definition at line 87 of file at91sam7s.h.
| #define PDC_RXTEN 0x00000001 |
Receiver transfer enable.
Definition at line 89 of file at91sam7s.h.
Referenced by AhdlcAt91Open(), and At91SpiTransfer2().
| #define PDC_RXTDIS 0x00000002 |
Receiver transfer disable.
Definition at line 90 of file at91sam7s.h.
Referenced by AhdlcAt91Init(), and At91SpiTransfer2().
| #define PDC_TXTEN 0x00000100 |
Transmitter transfer enable.
Definition at line 91 of file at91sam7s.h.
Referenced by At91SpiTransfer2().
| #define PDC_TXTDIS 0x00000200 |
Transmitter transfer disable.
Definition at line 92 of file at91sam7s.h.
Referenced by At91SpiTransfer2().
| #define DBGU_HAS_PDC |
Definition at line 94 of file at91sam7s.h.
| #define SPI_HAS_PDC |
Definition at line 95 of file at91sam7s.h.
| #define SSC_HAS_PDC |
Definition at line 96 of file at91sam7s.h.
| #define USART_HAS_PDC |
Definition at line 97 of file at91sam7s.h.
| #define USART_HAS_MODE |
Definition at line 98 of file at91sam7s.h.
| #define PIO_HAS_MULTIDRIVER |
Definition at line 100 of file at91sam7s.h.
| #define PIO_HAS_PULLUP |
Definition at line 101 of file at91sam7s.h.
| #define PIO_HAS_PERIPHERALSELECT |
Definition at line 102 of file at91sam7s.h.
| #define PIO_HAS_OUTPUTWRITEENABLE |
Definition at line 103 of file at91sam7s.h.