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00060 #include <cfg/arch/gpio.h>
00061 #include <cfg/audio.h>
00062
00063 #include <dev/irqreg.h>
00064 #include <dev/vs10xx.h>
00065
00066 #include <sys/atom.h>
00067 #include <sys/event.h>
00068 #include <sys/timer.h>
00069 #include <sys/heap.h>
00070 #include <sys/bankmem.h>
00071
00072 #include <stddef.h>
00073
00074 #ifndef INT0
00075 #define INT0 0
00076 #define INT1 1
00077 #define INT2 2
00078 #define INT3 3
00079 #define INT4 4
00080 #define INT5 5
00081 #define INT6 6
00082 #define INT7 7
00083 #endif
00084
00089
00090 #if !defined(AUDIO_VS1001K) && !defined(AUDIO_VS1011E) && !defined(AUDIO_VS1002D) && !defined(AUDIO_VS1003B) && !defined(AUDIO_VS1033C) && !defined(AUDIO_VS1053B)
00091 #define AUDIO_VS1001K
00092 #endif
00093
00094 #ifndef VS10XX_FREQ
00095
00096 #define VS10XX_FREQ 12288000UL
00097 #endif
00098
00099 #ifndef VS10XX_HWRST_DURATION
00100
00101 #define VS10XX_HWRST_DURATION 1
00102 #endif
00103
00104 #ifndef VS10XX_HWRST_RECOVER
00105
00106 #define VS10XX_HWRST_RECOVER 10
00107 #endif
00108
00109 #ifndef VS10XX_SWRST_RECOVER
00110
00111 #define VS10XX_SWRST_RECOVER VS10XX_HWRST_RECOVER
00112 #endif
00113
00114 #ifndef VS10XX_SCI_MODE
00115 #define VS10XX_SCI_MODE 0
00116 #endif
00117
00118 #ifndef VS10XX_SCI_RATE
00119 #define VS10XX_SCI_RATE (VS10XX_FREQ / 4)
00120 #endif
00121
00122 #ifndef VS10XX_SDI_MODE
00123 #define VS10XX_SDI_MODE 0
00124 #endif
00125
00126 #ifndef VS10XX_SDI_RATE
00127 #define VS10XX_SDI_RATE (VS10XX_FREQ / 4)
00128 #endif
00129
00130 #if defined(VS10XX_SCI_SPI0_DEVICE)
00131
00132 #include <dev/sppif0.h>
00133 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00134 #define SciReset(act) Sppi0ChipReset(VS10XX_SCI_SPI0_DEVICE, act)
00135 #else
00136 #define SciReset(act) Sppi0ChipReset(VS10XX_SCI_SPI0_DEVICE, !act)
00137 #endif
00138 #define SciSetMode() Sppi0SetMode(VS10XX_SCI_SPI0_DEVICE, VS10XX_SCI_MODE)
00139 #define SciSetSpeed() Sppi0SetSpeed(VS10XX_SCI_SPI0_DEVICE, VS10XX_SCI_RATE)
00140 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00141 #define SciSelect() Sppi0SelectDevice(VS10XX_SCI_SPI0_DEVICE)
00142 #define SciDeselect() Sppi0DeselectDevice(VS10XX_SCI_SPI0_DEVICE)
00143 #else
00144 #define SciSelect() Sppi0NegSelectDevice(VS10XX_SCI_SPI0_DEVICE)
00145 #define SciDeselect() Sppi0NegDeselectDevice(VS10XX_SCI_SPI0_DEVICE)
00146 #endif
00147 #define SciByte(b) Sppi0Byte(b)
00148
00149 #elif defined(VS10XX_SCI_SBBI0_DEVICE)
00150
00151 #include <dev/sbbif0.h>
00152 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00153 #define SciReset(act) Sbbi0ChipReset(VS10XX_SCI_SBBI0_DEVICE, act)
00154 #else
00155 #define SciReset(act) Sbbi0ChipReset(VS10XX_SCI_SBBI0_DEVICE, !act)
00156 #endif
00157 #define SciSetMode() Sbbi0SetMode(VS10XX_SCI_SBBI0_DEVICE, VS10XX_SCI_MODE)
00158 #define SciSetSpeed() Sbbi0SetSpeed(VS10XX_SCI_SBBI0_DEVICE, VS10XX_SCI_RATE)
00159 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00160 #define SciSelect() Sbbi0SelectDevice(VS10XX_SCI_SBBI0_DEVICE)
00161 #define SciDeselect() Sbbi0DeselectDevice(VS10XX_SCI_SBBI0_DEVICE)
00162 #else
00163 #define SciSelect() Sbbi0NegSelectDevice(VS10XX_SCI_SBBI0_DEVICE)
00164 #define SciDeselect() Sbbi0NegDeselectDevice(VS10XX_SCI_SBBI0_DEVICE)
00165 #endif
00166 #define SciByte(b) Sbbi0Byte(b)
00167
00168 #elif defined(VS10XX_SCI_SBBI1_DEVICE)
00169
00170 #include <dev/sbbif1.h>
00171 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00172 #define SciReset(act) Sbbi1ChipReset(VS10XX_SCI_SBBI1_DEVICE, act)
00173 #else
00174 #define SciReset(act) Sbbi1ChipReset(VS10XX_SCI_SBBI1_DEVICE, !act)
00175 #endif
00176 #define SciSetMode() Sbbi1SetMode(VS10XX_SCI_SBBI1_DEVICE, VS10XX_SCI_MODE)
00177 #define SciSetSpeed() Sbbi1SetSpeed(VS10XX_SCI_SBBI1_DEVICE, VS10XX_SCI_RATE)
00178 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00179 #define SciSelect() Sbbi1SelectDevice(VS10XX_SCI_SBBI1_DEVICE)
00180 #define SciDeselect() Sbbi1DeselectDevice(VS10XX_SCI_SBBI1_DEVICE)
00181 #else
00182 #define SciSelect() Sbbi1NegSelectDevice(VS10XX_SCI_SBBI1_DEVICE)
00183 #define SciDeselect() Sbbi1NegDeselectDevice(VS10XX_SCI_SBBI1_DEVICE)
00184 #endif
00185 #define SciByte(b) Sbbi1Byte(b)
00186
00187 #elif defined(VS10XX_SCI_SBBI2_DEVICE)
00188
00189 #include <dev/sbbif2.h>
00190 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00191 #define SciReset(act) Sbbi2ChipReset(VS10XX_SCI_SBBI2_DEVICE, act)
00192 #else
00193 #define SciReset(act) Sbbi2ChipReset(VS10XX_SCI_SBBI2_DEVICE, !act)
00194 #endif
00195 #define SciSetMode() Sbbi2SetMode(VS10XX_SCI_SBBI2_DEVICE, VS10XX_SCI_MODE)
00196 #define SciSetSpeed() Sbbi2SetSpeed(VS10XX_SCI_SBBI2_DEVICE, VS10XX_SCI_RATE)
00197 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00198 #define SciSelect() Sbbi2SelectDevice(VS10XX_SCI_SBBI2_DEVICE)
00199 #define SciDeselect() Sbbi2DeselectDevice(VS10XX_SCI_SBBI2_DEVICE)
00200 #else
00201 #define SciSelect() Sbbi2NegSelectDevice(VS10XX_SCI_SBBI2_DEVICE)
00202 #define SciDeselect() Sbbi2NegDeselectDevice(VS10XX_SCI_SBBI2_DEVICE)
00203 #endif
00204 #define SciByte(b) Sbbi2Byte(b)
00205
00206 #elif defined(VS10XX_SCI_SBBI3_DEVICE)
00207
00208 #include <dev/sbbif3.h>
00209 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00210 #define SciReset(act) Sbbi3ChipReset(VS10XX_SCI_SBBI3_DEVICE, act)
00211 #else
00212 #define SciReset(act) Sbbi3ChipReset(VS10XX_SCI_SBBI3_DEVICE, !act)
00213 #endif
00214 #define SciSetMode() Sbbi3SetMode(VS10XX_SCI_SBBI3_DEVICE, VS10XX_SCI_MODE)
00215 #define SciSetSpeed() Sbbi3SetSpeed(VS10XX_SCI_SBBI3_DEVICE, VS10XX_SCI_RATE)
00216 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00217 #define SciSelect() Sbbi3SelectDevice(VS10XX_SCI_SBBI3_DEVICE)
00218 #define SciDeselect() Sbbi3DeselectDevice(VS10XX_SCI_SBBI3_DEVICE)
00219 #else
00220 #define SciSelect() Sbbi3NegSelectDevice(VS10XX_SCI_SBBI3_DEVICE)
00221 #define SciDeselect() Sbbi3NegDeselectDevice(VS10XX_SCI_SBBI3_DEVICE)
00222 #endif
00223 #define SciByte(b) Sbbi3Byte(b)
00224
00225 #else
00226
00227 #define SciReset(act)
00228 #define SciSetMode() (-1)
00229 #define SciSetSpeed()
00230 #define SciSelect()
00231 #define SciDeselect()
00232 #define SciByte(b) 0
00233
00234 #endif
00235
00236
00237 #if defined(VS10XX_SDI_SPI0_DEVICE)
00238
00239 #include <dev/sppif0.h>
00240 #define SdiSetMode() Sppi0SetMode(VS10XX_SDI_SPI0_DEVICE, VS10XX_SDI_MODE)
00241 #define SdiSetSpeed() Sppi0SetSpeed(VS10XX_SDI_SPI0_DEVICE, VS10XX_SDI_RATE)
00242 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00243 #define SdiSelect() Sppi0SelectDevice(VS10XX_SDI_SPI0_DEVICE)
00244 #define SdiDeselect() Sppi0DeselectDevice(VS10XX_SDI_SPI0_DEVICE)
00245 #else
00246 #define SdiSelect() Sppi0NegSelectDevice(VS10XX_SDI_SPI0_DEVICE)
00247 #define SdiDeselect() Sppi0NegDeselectDevice(VS10XX_SDI_SPI0_DEVICE)
00248 #endif
00249 #define SdiByte(b) Sppi0Byte(b)
00250
00251 #elif defined(VS10XX_SDI_SBBI0_DEVICE)
00252
00253 #include <dev/sbbif0.h>
00254 #define SdiSetMode() Sbbi0SetMode(VS10XX_SDI_SBBI0_DEVICE, VS10XX_SDI_MODE)
00255 #define SdiSetSpeed() Sbbi0SetSpeed(VS10XX_SDI_SBBI0_DEVICE, VS10XX_SDI_RATE)
00256 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00257 #define SdiSelect() Sbbi0SelectDevice(VS10XX_SDI_SBBI0_DEVICE)
00258 #define SdiDeselect() Sbbi0DeselectDevice(VS10XX_SDI_SBBI0_DEVICE)
00259 #else
00260 #define SdiSelect() Sbbi0NegSelectDevice(VS10XX_SDI_SBBI0_DEVICE)
00261 #define SdiDeselect() Sbbi0NegDeselectDevice(VS10XX_SDI_SBBI0_DEVICE)
00262 #endif
00263 #define SdiByte(b) Sbbi0Byte(b)
00264
00265 #elif defined(VS10XX_SDI_SBBI1_DEVICE)
00266
00267 #include <dev/sbbif1.h>
00268 #define SdiSetMode() Sbbi1SetMode(VS10XX_SDI_SBBI1_DEVICE, VS10XX_SDI_MODE)
00269 #define SdiSetSpeed() Sbbi1SetSpeed(VS10XX_SDI_SBBI1_DEVICE, VS10XX_SDI_RATE)
00270 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00271 #define SdiSelect() Sbbi1SelectDevice(VS10XX_SDI_SBBI1_DEVICE)
00272 #define SdiDeselect() Sbbi1DeselectDevice(VS10XX_SDI_SBBI1_DEVICE)
00273 #else
00274 #define SdiSelect() Sbbi1NegSelectDevice(VS10XX_SDI_SBBI1_DEVICE)
00275 #define SdiDeselect() Sbbi1NegDeselectDevice(VS10XX_SDI_SBBI1_DEVICE)
00276 #endif
00277 #define SdiByte(b) Sbbi1Byte(b)
00278
00279 #elif defined(VS10XX_SDI_SBBI2_DEVICE)
00280
00281 #include <dev/sbbif2.h>
00282 #define SdiSetMode() Sbbi2SetMode(VS10XX_SDI_SBBI2_DEVICE, VS10XX_SDI_MODE)
00283 #define SdiSetSpeed() Sbbi2SetSpeed(VS10XX_SDI_SBBI2_DEVICE, VS10XX_SDI_RATE)
00284 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00285 #define SdiSelect() Sbbi2SelectDevice(VS10XX_SDI_SBBI2_DEVICE)
00286 #define SdiDeselect() Sbbi2DeselectDevice(VS10XX_SDI_SBBI2_DEVICE)
00287 #else
00288 #define SdiSelect() Sbbi2NegSelectDevice(VS10XX_SDI_SBBI2_DEVICE)
00289 #define SdiDeselect() Sbbi2NegDeselectDevice(VS10XX_SDI_SBBI2_DEVICE)
00290 #endif
00291 #define SdiByte(b) Sbbi2Byte(b)
00292
00293 #elif defined(VS10XX_SDI_SBBI3_DEVICE)
00294
00295 #include <dev/sbbif3.h>
00296 #define SdiSetMode() Sbbi3SetMode(VS10XX_SDI_SBBI3_DEVICE, VS10XX_SDI_MODE)
00297 #define SdiSetSpeed() Sbbi3SetSpeed(VS10XX_SDI_SBBI3_DEVICE, VS10XX_SDI_RATE)
00298 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00299 #define SdiSelect() Sbbi3SelectDevice(VS10XX_SDI_SBBI3_DEVICE)
00300 #define SdiDeselect() Sbbi3DeselectDevice(VS10XX_SDI_SBBI3_DEVICE)
00301 #else
00302 #define SdiSelect() Sbbi3NegSelectDevice(VS10XX_SDI_SBBI3_DEVICE)
00303 #define SdiDeselect() Sbbi3NegDeselectDevice(VS10XX_SDI_SBBI3_DEVICE)
00304 #endif
00305 #define SdiByte(b) Sbbi3Byte(b)
00306
00307 #else
00308
00309 #define SdiSetMode() (-1)
00310 #define SdiSetSpeed()
00311 #define SdiSelect()
00312 #define SdiDeselect()
00313 #define SdiByte(b) 0
00314
00315 #endif
00316
00317
00318
00319
00320 #if MCU_AT91 || __AVR32__
00321
00322 #if (VS10XX_SIGNAL_IRQ == INT0)
00323 #define VS10XX_SIGNAL sig_INTERRUPT0
00324 #elif (VS10XX_SIGNAL_IRQ == INT1)
00325 #define VS10XX_SIGNAL sig_INTERRUPT1
00326 #else
00327 #define VS10XX_SIGNAL sig_INTERRUPT2
00328 #endif
00329
00330 #if defined(VS10XX_XCS_BIT)
00331
00332 #if !defined(VS10XX_XCS_PORT)
00333 #define VS10XX_XCS_PE_REG PIO_PER
00334 #define VS10XX_XCS_OE_REG PIO_OER
00335 #define VS10XX_XCS_COD_REG PIO_CODR
00336 #define VS10XX_XCS_SOD_REG PIO_SODR
00337 #elif VS10XX_XCS_PORT == PIOA_ID
00338 #define VS10XX_XCS_PE_REG PIOA_PER
00339 #define VS10XX_XCS_OE_REG PIOA_OER
00340 #define VS10XX_XCS_COD_REG PIOA_CODR
00341 #define VS10XX_XCS_SOD_REG PIOA_SODR
00342 #elif VS10XX_XCS_PORT == PIOB_ID
00343 #define VS10XX_XCS_PE_REG PIOB_PER
00344 #define VS10XX_XCS_OE_REG PIOB_OER
00345 #define VS10XX_XCS_COD_REG PIOB_CODR
00346 #define VS10XX_XCS_SOD_REG PIOB_SODR
00347 #elif VS10XX_XCS_PORT == PIOC_ID
00348 #define VS10XX_XCS_PE_REG PIOC_PER
00349 #define VS10XX_XCS_OE_REG PIOC_OER
00350 #define VS10XX_XCS_COD_REG PIOC_CODR
00351 #define VS10XX_XCS_SOD_REG PIOC_SODR
00352 #endif
00353 #define VS10XX_XCS_ENA() \
00354 outr(VS10XX_XCS_PE_REG, _BV(VS10XX_XCS_BIT)); \
00355 outr(VS10XX_XCS_OE_REG, _BV(VS10XX_XCS_BIT))
00356 #define VS10XX_XCS_CLR() outr(VS10XX_XCS_COD_REG, _BV(VS10XX_XCS_BIT))
00357 #define VS10XX_XCS_SET() outr(VS10XX_XCS_SOD_REG, _BV(VS10XX_XCS_BIT))
00358
00359 #else
00360
00361 #define VS10XX_XCS_ENA()
00362 #define VS10XX_XCS_CLR()
00363 #define VS10XX_XCS_SET()
00364
00365 #endif
00366
00367 #if defined(VS10XX_XDCS_BIT)
00368
00369 #if !defined(VS10XX_XDCS_PORT)
00370 #define VS10XX_XDCS_PE_REG PIO_PER
00371 #define VS10XX_XDCS_OE_REG PIO_OER
00372 #define VS10XX_XDCS_COD_REG PIO_CODR
00373 #define VS10XX_XDCS_SOD_REG PIO_SODR
00374 #elif VS10XX_XDCS_PORT == PIOA_ID
00375 #define VS10XX_XDCS_PE_REG PIOA_PER
00376 #define VS10XX_XDCS_OE_REG PIOA_OER
00377 #define VS10XX_XDCS_COD_REG PIOA_CODR
00378 #define VS10XX_XDCS_SOD_REG PIOA_SODR
00379 #elif VS10XX_XDCS_PORT == PIOB_ID
00380 #define VS10XX_XDCS_PE_REG PIOB_PER
00381 #define VS10XX_XDCS_OE_REG PIOB_OER
00382 #define VS10XX_XDCS_COD_REG PIOB_CODR
00383 #define VS10XX_XDCS_SOD_REG PIOB_SODR
00384 #elif VS10XX_XDCS_PORT == PIOC_ID
00385 #define VS10XX_XDCS_PE_REG PIOC_PER
00386 #define VS10XX_XDCS_OE_REG PIOC_OER
00387 #define VS10XX_XDCS_COD_REG PIOC_CODR
00388 #define VS10XX_XDCS_SOD_REG PIOC_SODR
00389 #endif
00390 #define VS10XX_XDCS_ENA() \
00391 outr(VS10XX_XDCS_PE_REG, _BV(VS10XX_XDCS_BIT)); \
00392 outr(VS10XX_XDCS_OE_REG, _BV(VS10XX_XDCS_BIT))
00393 #define VS10XX_XDCS_CLR() outr(VS10XX_XDCS_COD_REG, _BV(VS10XX_XDCS_BIT))
00394 #define VS10XX_XDCS_SET() outr(VS10XX_XDCS_SOD_REG, _BV(VS10XX_XDCS_BIT))
00395
00396 #else
00397
00398 #define VS10XX_XDCS_ENA()
00399 #define VS10XX_XDCS_CLR()
00400 #define VS10XX_XDCS_SET()
00401
00402 #endif
00403
00404 #if defined(VS10XX_DREQ_BIT)
00405
00406 #if !defined(VS10XX_DREQ_PIO_ID)
00407 #define VS10XX_DREQ_PE_REG PIO_PER
00408 #define VS10XX_DREQ_OD_REG PIO_ODR
00409 #define VS10XX_DREQ_PDS_REG PIO_PDSR
00410 #elif VS10XX_DREQ_PIO_ID == PIOA_ID
00411 #define VS10XX_DREQ_PE_REG PIOA_PER
00412 #define VS10XX_DREQ_OD_REG PIOA_ODR
00413 #define VS10XX_DREQ_PDS_REG PIOA_PDSR
00414 #elif VS10XX_DREQ_PIO_ID == PIOB_ID
00415 #define VS10XX_DREQ_PE_REG PIOB_PER
00416 #define VS10XX_DREQ_OD_REG PIOB_ODR
00417 #define VS10XX_DREQ_PDS_REG PIOB_PDSR
00418 #elif VS10XX_DREQ_PIO_ID == PIOC_ID
00419 #define VS10XX_DREQ_PE_REG PIOC_PER
00420 #define VS10XX_DREQ_OD_REG PIOC_ODR
00421 #define VS10XX_DREQ_PDS_REG PIOC_PDSR
00422 #endif
00423
00424 #define VS10XX_DREQ_PD_REG PIO_PDR
00425 #define VS10XX_DREQ_OD_REG PIO_ODR
00426 #define VS10XX_DREQ_PDS_REG PIO_PDSR
00427 #define VS10XX_DREQ_ENA() \
00428 outr(VS10XX_DREQ_PD_REG, _BV(VS10XX_DREQ_BIT)); \
00429 outr(VS10XX_DREQ_OD_REG, _BV(VS10XX_DREQ_BIT))
00430 #define VS10XX_DREQ_TST() ((inr(VS10XX_DREQ_PDS_REG) & _BV(VS10XX_DREQ_BIT)) == _BV(VS10XX_DREQ_BIT))
00431
00432 #else
00433
00434 #define VS10XX_DREQ_ENA()
00435 #define VS10XX_DREQ_TST() 0
00436
00437 #endif
00438
00439 #ifdef VS10XX_BSYNC_BIT
00440
00441 #if !defined(VS10XX_BSYNC_PIO_ID)
00442 #define VS10XX_BSYNC_PE_REG PIO_PER
00443 #define VS10XX_BSYNC_OE_REG PIO_OER
00444 #define VS10XX_BSYNC_COD_REG PIO_CODR
00445 #define VS10XX_BSYNC_SOD_REG PIO_SODR
00446 #elif VS10XX_BSYNC_PIO_ID == PIOA_ID
00447 #define VS10XX_BSYNC_PE_REG PIOA_PER
00448 #define VS10XX_BSYNC_OE_REG PIOA_OER
00449 #define VS10XX_BSYNC_COD_REG PIOA_CODR
00450 #define VS10XX_BSYNC_SOD_REG PIOA_SODR
00451 #elif VS10XX_BSYNC_PIO_ID == PIOB_ID
00452 #define VS10XX_BSYNC_PE_REG PIOB_PER
00453 #define VS10XX_BSYNC_OE_REG PIOB_OER
00454 #define VS10XX_BSYNC_COD_REG PIOB_CODR
00455 #define VS10XX_BSYNC_SOD_REG PIOB_SODR
00456 #elif VS10XX_BSYNC_PIO_ID == PIOC_ID
00457 #define VS10XX_BSYNC_PE_REG PIOC_PER
00458 #define VS10XX_BSYNC_OE_REG PIOC_OER
00459 #define VS10XX_BSYNC_COD_REG PIOC_CODR
00460 #define VS10XX_BSYNC_SOD_REG PIOC_SODR
00461 #endif
00462 #define VS10XX_BSYNC_ENA() \
00463 outr(VS10XX_BSYNC_PE_REG, _BV(VS10XX_BSYNC_BIT)); \
00464 outr(VS10XX_BSYNC_OE_REG, _BV(VS10XX_BSYNC_BIT))
00465 #define VS10XX_BSYNC_CLR() outr(VS10XX_BSYNC_COD_REG, _BV(VS10XX_BSYNC_BIT))
00466 #define VS10XX_BSYNC_SET() outr(VS10XX_BSYNC_SOD_REG, _BV(VS10XX_BSYNC_BIT))
00467
00468 #else
00469
00470 #define VS10XX_BSYNC_ENA()
00471 #define VS10XX_BSYNC_CLR()
00472 #define VS10XX_BSYNC_SET()
00473
00474 #endif
00475
00476
00477
00478
00479
00480 #elif defined(__AVR__)
00481
00482 #if !defined(VS10XX_SIGNAL_IRQ)
00483 #define VS10XX_SIGNAL_IRQ INT6
00484 #endif
00485
00486 #if (VS10XX_SIGNAL_IRQ == INT0)
00487 #define VS10XX_SIGNAL sig_INTERRUPT0
00488 #define VS10XX_DREQ_BIT 0
00489 #define VS10XX_DREQ_PDS_REG PIND
00490 #define VS10XX_DREQ_PUE_REG PORTD
00491 #define VS10XX_DREQ_OE_REG DDRD
00492
00493 #elif (VS10XX_SIGNAL_IRQ == INT1)
00494 #define VS10XX_SIGNAL sig_INTERRUPT1
00495 #define VS10XX_DREQ_BIT 1
00496 #define VS10XX_DREQ_PDS_REG PIND
00497 #define VS10XX_DREQ_PUE_REG PORTD
00498 #define VS10XX_DREQ_OE_REG DDRD
00499
00500 #elif (VS10XX_SIGNAL_IRQ == INT2)
00501 #define VS10XX_SIGNAL sig_INTERRUPT2
00502 #define VS10XX_DREQ_BIT 2
00503 #define VS10XX_DREQ_PDS_REG PIND
00504 #define VS10XX_DREQ_PUE_REG PORTD
00505 #define VS10XX_DREQ_OE_REG DDRD
00506
00507 #elif (VS10XX_SIGNAL_IRQ == INT3)
00508 #define VS10XX_SIGNAL sig_INTERRUPT3
00509 #define VS10XX_DREQ_BIT 3
00510 #define VS10XX_DREQ_PDS_REG PIND
00511 #define VS10XX_DREQ_PUE_REG PORTD
00512 #define VS10XX_DREQ_OE_REG DDRD
00513
00514 #elif (VS10XX_SIGNAL_IRQ == INT4)
00515 #define VS10XX_SIGNAL sig_INTERRUPT4
00516 #define VS10XX_DREQ_BIT 4
00517 #define VS10XX_DREQ_PDS_REG PINE
00518 #define VS10XX_DREQ_PUE_REG PORTE
00519 #define VS10XX_DREQ_OE_REG DDRE
00520
00521 #elif (VS10XX_SIGNAL_IRQ == INT5)
00522 #define VS10XX_SIGNAL sig_INTERRUPT5
00523 #define VS10XX_DREQ_BIT 5
00524 #define VS10XX_DREQ_PDS_REG PINE
00525 #define VS10XX_DREQ_PUE_REG PORTE
00526 #define VS10XX_DREQ_OE_REG DDRE
00527
00528 #elif (VS10XX_SIGNAL_IRQ == INT7)
00529 #define VS10XX_SIGNAL sig_INTERRUPT7
00530 #define VS10XX_DREQ_BIT 7
00531 #define VS10XX_DREQ_PDS_REG PINE
00532 #define VS10XX_DREQ_PUE_REG PORTE
00533 #define VS10XX_DREQ_OE_REG DDRE
00534
00535 #else
00536 #define VS10XX_SIGNAL sig_INTERRUPT6
00537 #define VS10XX_DREQ_BIT 6
00538 #define VS10XX_DREQ_PDS_REG PINE
00539 #define VS10XX_DREQ_PUE_REG PORTE
00540 #define VS10XX_DREQ_OE_REG DDRE
00541
00542 #endif
00543
00544 #define VS10XX_DREQ_ENA() \
00545 cbi(VS10XX_DREQ_OE_REG, VS10XX_DREQ_BIT); \
00546 sbi(VS10XX_DREQ_PUE_REG, VS10XX_DREQ_BIT)
00547 #define VS10XX_DREQ_TST() ((inb(VS10XX_DREQ_PDS_REG) & _BV(VS10XX_DREQ_BIT)) == _BV(VS10XX_DREQ_BIT))
00548
00549
00550 #if defined(VS10XX_XCS_BIT)
00551
00552 #if (VS10XX_XCS_PORT == AVRPORTA)
00553 #define VS10XX_XCS_SOD_REG PORTA
00554 #define VS10XX_XCS_OE_REG DDRA
00555 #elif (VS10XX_XCS_PORT == AVRPORTB)
00556 #define VS10XX_XCS_SOD_REG PORTB
00557 #define VS10XX_XCS_OE_REG DDRB
00558 #elif (VS10XX_XCS_PORT == AVRPORTD)
00559 #define VS10XX_XCS_SOD_REG PORTD
00560 #define VS10XX_XCS_OE_REG DDRD
00561 #elif (VS10XX_XCS_PORT == AVRPORTE)
00562 #define VS10XX_XCS_SOD_REG PORTE
00563 #define VS10XX_XCS_OE_REG DDRE
00564 #elif (VS10XX_XCS_PORT == AVRPORTF)
00565 #define VS10XX_XCS_SOD_REG PORTF
00566 #define VS10XX_XCS_OE_REG DDRF
00567 #elif (VS10XX_XCS_PORT == AVRPORTG)
00568 #define VS10XX_XCS_SOD_REG PORTG
00569 #define VS10XX_XCS_OE_REG DDRG
00570 #elif (VS10XX_XCS_PORT == AVRPORTH)
00571 #define VS10XX_XCS_SOD_REG PORTH
00572 #define VS10XX_XCS_OE_REG DDRH
00573 #endif
00574 #define VS10XX_XCS_ENA() sbi(VS10XX_XCS_OE_REG, VS10XX_XCS_BIT)
00575 #define VS10XX_XCS_CLR() cbi(VS10XX_XCS_SOD_REG, VS10XX_XCS_BIT)
00576 #define VS10XX_XCS_SET() sbi(VS10XX_XCS_SOD_REG, VS10XX_XCS_BIT)
00577
00578 #else
00579
00580 #define VS10XX_XCS_ENA()
00581 #define VS10XX_XCS_CLR()
00582 #define VS10XX_XCS_SET()
00583
00584 #endif
00585
00586 #if defined(VS10XX_XDCS_BIT)
00587
00588 #if (VS10XX_XDCS_PORT == AVRPORTA)
00589 #define VS10XX_XDCS_SOD_REG PORTA
00590 #define VS10XX_XDCS_OE_REG DDRA
00591 #elif (VS10XX_XDCS_PORT == AVRPORTB)
00592 #define VS10XX_XDCS_SOD_REG PORTB
00593 #define VS10XX_XDCS_OE_REG DDRB
00594 #elif (VS10XX_XDCS_PORT == AVRPORTD)
00595 #define VS10XX_XDCS_SOD_REG PORTD
00596 #define VS10XX_XDCS_OE_REG DDRD
00597 #elif (VS10XX_XDCS_PORT == AVRPORTE)
00598 #define VS10XX_XDCS_SOD_REG PORTE
00599 #define VS10XX_XDCS_OE_REG DDRE
00600 #elif (VS10XX_XDCS_PORT == AVRPORTF)
00601 #define VS10XX_XDCS_SOD_REG PORTF
00602 #define VS10XX_XDCS_OE_REG DDRF
00603 #elif (VS10XX_XDCS_PORT == AVRPORTG)
00604 #define VS10XX_XDCS_SOD_REG PORTG
00605 #define VS10XX_XDCS_OE_REG DDRG
00606 #elif (VS10XX_XDCS_PORT == AVRPORTH)
00607 #define VS10XX_XDCS_SOD_REG PORTH
00608 #define VS10XX_XDCS_OE_REG DDRH
00609 #endif
00610 #define VS10XX_XDCS_ENA() sbi(VS10XX_XDCS_OE_REG, VS10XX_XDCS_BIT)
00611 #define VS10XX_XDCS_CLR() cbi(VS10XX_XDCS_SOD_REG, VS10XX_XDCS_BIT)
00612 #define VS10XX_XDCS_SET() sbi(VS10XX_XDCS_SOD_REG, VS10XX_XDCS_BIT)
00613
00614 #else
00615
00616 #define VS10XX_XDCS_ENA()
00617 #define VS10XX_XDCS_CLR()
00618 #define VS10XX_XDCS_SET()
00619
00620 #endif
00621
00622
00623 #if defined(VS10XX_BSYNC_BIT)
00624
00625 #if (VS10XX_BSYNC_PORT == AVRPORTA)
00626 #define VS10XX_BSYNC_SOD_REG PORTA
00627 #define VS10XX_BSYNC_OE_REG DDRA
00628 #elif (VS10XX_BSYNC_PORT == AVRPORTB)
00629 #define VS10XX_BSYNC_SOD_REG PORTB
00630 #define VS10XX_BSYNC_OE_REG DDRB
00631 #elif (VS10XX_BSYNC_PORT == AVRPORTD)
00632 #define VS10XX_BSYNC_SOD_REG PORTD
00633 #define VS10XX_BSYNC_OE_REG DDRD
00634 #elif (VS10XX_BSYNC_PORT == AVRPORTE)
00635 #define VS10XX_BSYNC_SOD_REG PORTE
00636 #define VS10XX_BSYNC_OE_REG DDRE
00637 #elif (VS10XX_BSYNC_PORT == AVRPORTF)
00638 #define VS10XX_BSYNC_SOD_REG PORTF
00639 #define VS10XX_BSYNC_OE_REG DDRF
00640 #elif (VS10XX_BSYNC_PORT == AVRPORTG)
00641 #define VS10XX_BSYNC_SOD_REG PORTG
00642 #define VS10XX_BSYNC_OE_REG DDRG
00643 #elif (VS10XX_BSYNC_PORT == AVRPORTH)
00644 #define VS10XX_BSYNC_SOD_REG PORTH
00645 #define VS10XX_BSYNC_OE_REG DDRH
00646 #endif
00647 #define VS10XX_BSYNC_ENA() sbi(VS10XX_BSYNC_OE_REG, VS10XX_BSYNC_BIT)
00648 #define VS10XX_BSYNC_CLR() cbi(VS10XX_BSYNC_SOD_REG, VS10XX_BSYNC_BIT)
00649 #define VS10XX_BSYNC_SET() sbi(VS10XX_BSYNC_SOD_REG, VS10XX_BSYNC_BIT)
00650
00651 #else
00652
00653 #define VS10XX_BSYNC_ENA()
00654 #define VS10XX_BSYNC_CLR()
00655 #define VS10XX_BSYNC_SET()
00656
00657 #endif
00658
00659
00660
00661
00662
00663 #endif
00664
00665
00666 static volatile ureg_t vs_status = VS_STATUS_STOPPED;
00667 static volatile unsigned int vs_flush;
00668
00669
00670
00671
00672
00673
00674
00675
00676
00677 static INLINE void VsSdiPutByte(ureg_t b)
00678 {
00679 #if defined(VS10XX_BSYNC_BIT)
00680
00681 #if defined(VS10XX_SDI_SBBI0_DEVICE)
00682 ureg_t mask;
00683
00684 VS10XX_BSYNC_SET();
00685
00686 for (mask = 0x80; mask; mask >>= 1) {
00687 SBBI0_SCK_CLR();
00688 if (b & mask) {
00689 SBBI0_MOSI_SET();
00690 }
00691 else {
00692 SBBI0_MOSI_CLR();
00693 }
00694 SBBI0_SCK_SET();
00695 if (mask & 0x40) {
00696 VS10XX_BSYNC_CLR();
00697 }
00698 }
00699 SBBI0_SCK_CLR();
00700 #elif defined(VS10XX_SDI_SBBI1_DEVICE)
00701 ureg_t mask;
00702
00703 VS10XX_BSYNC_SET();
00704
00705 for (mask = 0x80; mask; mask >>= 1) {
00706 SBBI1_SCK_CLR();
00707 if (b & mask) {
00708 SBBI1_MOSI_SET();
00709 }
00710 else {
00711 SBBI1_MOSI_CLR();
00712 }
00713 SBBI1_SCK_SET();
00714 if (mask & 0x40) {
00715 VS10XX_BSYNC_CLR();
00716 }
00717 }
00718 SBBI1_SCK_CLR();
00719 #elif defined(VS10XX_SDI_SBBI2_DEVICE)
00720 ureg_t mask;
00721
00722 VS10XX_BSYNC_SET();
00723
00724 for (mask = 0x80; mask; mask >>= 1) {
00725 SBBI2_SCK_CLR();
00726 if (b & mask) {
00727 SBBI2_MOSI_SET();
00728 }
00729 else {
00730 SBBI2_MOSI_CLR();
00731 }
00732 SBBI2_SCK_SET();
00733 if (mask & 0x40) {
00734 VS10XX_BSYNC_CLR();
00735 }
00736 }
00737 SBBI2_SCK_CLR();
00738 #elif defined(VS10XX_SDI_SBBI3_DEVICE)
00739 ureg_t mask;
00740
00741 VS10XX_BSYNC_SET();
00742
00743 for (mask = 0x80; mask; mask >>= 1) {
00744 SBBI3_SCK_CLR();
00745 if (b & mask) {
00746 SBBI3_MOSI_SET();
00747 }
00748 else {
00749 SBBI3_MOSI_CLR();
00750 }
00751 SBBI3_SCK_SET();
00752 if (mask & 0x40) {
00753 VS10XX_BSYNC_CLR();
00754 }
00755 }
00756 SBBI3_SCK_CLR();
00757 #elif defined(VS10XX_SDI_SPI0_DEVICE)
00758 VS10XX_BSYNC_SET();
00759
00760 outb(SPDR, b);
00761
00762 _NOP();
00763 _NOP();
00764 _NOP();
00765 _NOP();
00766 VS10XX_BSYNC_CLR();
00767
00768
00769 loop_until_bit_is_set(SPSR, SPIF);
00770 #endif
00771
00772 #else
00773
00774 (void)SdiByte(b);
00775
00776 #endif
00777
00778 }
00779
00791 ureg_t VsPlayerInterrupts(ureg_t enable)
00792 {
00793 static ureg_t is_enabled = 0;
00794 ureg_t rc;
00795
00796 rc = is_enabled;
00797 if(enable) {
00798 VS10XX_DREQ_ENA();
00799 NutIrqEnable(&VS10XX_SIGNAL);
00800 }
00801 else {
00802 NutIrqDisable(&VS10XX_SIGNAL);
00803 }
00804 is_enabled = enable;
00805
00806 return rc;
00807 }
00808
00833 ureg_t VsPlayerThrottle(ureg_t on)
00834 {
00835 static ureg_t is_throttled = 0;
00836 ureg_t rc;
00837
00838 rc = is_throttled;
00839 if(on) {
00840 VS10XX_XDCS_SET();
00841 SdiDeselect();
00842 }
00843 else {
00844 VS10XX_XDCS_CLR();
00845 SdiSelect();
00846 }
00847 is_throttled = on;
00848
00849 return rc;
00850 }
00851
00855 static void VsSciSelect(ureg_t on)
00856 {
00857 if (on) {
00858
00859 SdiDeselect();
00860
00861 #if defined(VS10XX_SDI_SPI0_DEVICE) && !defined(VS10XX_SCI_SPI0_DEVICE)
00862
00863
00864
00865 cbi(SPCR, SPE);
00866 #endif
00867
00868
00869 VS10XX_XDCS_SET();
00870
00871 VS10XX_XCS_CLR();
00872
00873 SciSelect();
00874 }
00875 else {
00876
00877 SciDeselect();
00878
00879 VS10XX_XCS_SET();
00880
00881 VS10XX_XDCS_CLR();
00882
00883 SdiSelect();
00884 }
00885 }
00886
00893 static int VsWaitReady(void)
00894 {
00895 int tmo;
00896
00897 for (tmo = 0; tmo < 5000; tmo++) {
00898 if (VS10XX_DREQ_TST()) {
00899 return 0;
00900 }
00901 }
00902 return -1;
00903 }
00904
00905
00906
00907
00908
00909
00910
00911 static int VsSdiWrite(CONST uint8_t * data, size_t len)
00912 {
00913 while (len--) {
00914 if (!VS10XX_DREQ_TST() && VsWaitReady()) {
00915 return -1;
00916 }
00917 VsSdiPutByte(*data);
00918 data++;
00919 }
00920 return 0;
00921 }
00922
00923
00924
00925
00926
00927
00928
00929
00930 static int VsSdiWrite_P(PGM_P data, size_t len)
00931 {
00932 while (len--) {
00933 if (!VS10XX_DREQ_TST() && VsWaitReady()) {
00934 return -1;
00935 }
00936 VsSdiPutByte(PRG_RDB(data));
00937 data++;
00938 }
00939 return 0;
00940 }
00941
00942
00943
00944
00945
00946
00947 static void VsRegWrite(ureg_t reg, uint16_t data)
00948 {
00949
00950 VsWaitReady();
00951 VsSciSelect(1);
00952
00953
00954
00955
00956
00957
00958 (void)SciByte(VS_OPCODE_WRITE);
00959 (void)SciByte((uint8_t) reg);
00960 (void)SciByte((uint8_t) (data >> 8));
00961 (void)SciByte((uint8_t) data);
00962
00963
00964 VsSciSelect(0);
00965 }
00966
00967
00968
00969
00970
00971
00972
00973
00974 static uint16_t VsRegRead(ureg_t reg)
00975 {
00976 uint16_t data;
00977
00978
00979 VsWaitReady();
00980 VsSciSelect(1);
00981
00982 (void)SciByte(VS_OPCODE_READ);
00983 (void)SciByte((uint8_t) reg);
00984 data = (uint16_t)SciByte(0) << 8;
00985 data |= SciByte(0);
00986
00987
00988 VsSciSelect(0);
00989
00990 return data;
00991 }
00992
00993
00994
00995
00996
00997
00998
00999
01000 static void VsPlayerFeed(void *arg)
01001 {
01002 ureg_t j = 32;
01003 size_t total = 0;
01004
01005 if (!VS10XX_DREQ_TST()) {
01006 return;
01007 }
01008
01009
01010
01011
01012 if (vs_status == VS_STATUS_RUNNING) {
01013 char *bp = 0;
01014 size_t consumed = 0;
01015 size_t available = 0;
01016 do {
01017 if(consumed >= available) {
01018
01019 if(consumed) {
01020 NutSegBufReadCommit(consumed);
01021 consumed = 0;
01022 }
01023
01024 bp = NutSegBufReadRequest(&available);
01025 if(available == 0) {
01026
01027 vs_status = VS_STATUS_EOF;
01028 break;
01029 }
01030 }
01031
01032 VsSdiPutByte(*bp);
01033 bp++;
01034 consumed++;
01035 total++;
01036 if (total > 4096) {
01037 vs_status = VS_STATUS_EOF;
01038 break;
01039 }
01040
01041
01042
01043 if (VS10XX_DREQ_TST()) {
01044 j = 32;
01045 }
01046 } while(j--);
01047
01048
01049 NutSegBufReadLast(consumed);
01050 }
01051
01052
01053
01054
01055 if(vs_status != VS_STATUS_RUNNING && vs_flush) {
01056 do {
01057 VsSdiPutByte(0);
01058 if (--vs_flush == 0) {
01059
01060 vs_status = VS_STATUS_EMPTY;
01061 break;
01062 }
01063
01064
01065 if (VS10XX_DREQ_TST()) {
01066 j = 32;
01067 }
01068 } while(j--);
01069 }
01070 }
01071
01083 int VsPlayerKick(void)
01084 {
01085
01086
01087
01088 VsPlayerInterrupts(0);
01089 vs_status = VS_STATUS_RUNNING;
01090 VsPlayerFeed(NULL);
01091 VsPlayerInterrupts(1);
01092
01093 return 0;
01094 }
01095
01104 int VsPlayerStop(void)
01105 {
01106 ureg_t ief;
01107
01108 ief = VsPlayerInterrupts(0);
01109
01110 if (vs_status == VS_STATUS_RUNNING) {
01111 vs_status = VS_STATUS_STOPPED;
01112 }
01113 VsPlayerInterrupts(ief);
01114
01115 return 0;
01116 }
01117
01118
01131 int VsPlayerFlush(void)
01132 {
01133 VsPlayerInterrupts(0);
01134
01135 if (vs_status != VS_STATUS_EMPTY || NutSegBufUsed()) {
01136 if (vs_flush == 0) {
01137 vs_flush = VS_FLUSH_BYTES;
01138 }
01139
01140 if (vs_status != VS_STATUS_RUNNING) {
01141 VsPlayerKick();
01142 }
01143 }
01144 VsPlayerInterrupts(1);
01145
01146 return 0;
01147 }
01148
01154 int VsPlayerInit(void)
01155 {
01156
01157 VsPlayerInterrupts(0);
01158
01159
01160 SciReset(1);
01161
01162
01163 if (SciSetMode()) {
01164 return -1;
01165 }
01166 SciSetSpeed();
01167 SciDeselect();
01168
01169
01170 if (SdiSetMode()) {
01171 return -1;
01172 }
01173 SdiSetSpeed();
01174 SdiDeselect();
01175
01176
01177 VS10XX_BSYNC_CLR();
01178 VS10XX_BSYNC_ENA();
01179
01180
01181 VS10XX_XDCS_SET();
01182 VS10XX_XDCS_ENA();
01183
01184
01185 VS10XX_XCS_SET();
01186 VS10XX_XCS_ENA();
01187
01188
01189 VS10XX_DREQ_ENA();
01190
01191
01192 if (NutRegisterIrqHandler(&VS10XX_SIGNAL, VsPlayerFeed, NULL)) {
01193 return -1;
01194 }
01195
01196
01197 NutIrqSetMode(&VS10XX_SIGNAL, NUT_IRQMODE_RISINGEDGE);
01198
01199
01200 SciReset(0);
01201 NutDelay(VS10XX_HWRST_RECOVER);
01202
01203 return VsPlayerReset(0);
01204 }
01205
01232 int VsPlayerReset(uint16_t mode)
01233 {
01234
01235 VsPlayerInterrupts(0);
01236 vs_status = VS_STATUS_STOPPED;
01237
01238
01239 VsRegWrite(VS_MODE_REG, VS_SM_RESET);
01240
01241 NutDelay(VS10XX_SWRST_RECOVER);
01242
01243
01244
01245
01246 if ((mode & VS_SM_RESET) != 0 || !VS10XX_DREQ_TST()) {
01247
01248 SciReset(1);
01249
01250 NutDelay(VS10XX_HWRST_DURATION);
01251 SciReset(0);
01252
01253 NutDelay(VS10XX_HWRST_RECOVER);
01254 if (!VS10XX_DREQ_TST()) {
01255 return -1;
01256 }
01257 }
01258
01259
01260 #if defined(VS10XX_BSYNC_BIT)
01261 VsRegWrite(VS_MODE_REG, mode);
01262 #else
01263 VsRegWrite(VS_MODE_REG, VS_SM_SDINEW | mode);
01264 #endif
01265
01266 #if VS10XX_FREQ < 20000000UL
01267 VsRegWrite(VS_CLOCKF_REG, (uint16_t)(VS_CF_DOUBLER | (VS10XX_FREQ / 2000UL)));
01268 #else
01269 VsRegWrite(VS_CLOCKF_REG, (uint16_t)(VS10XX_FREQ / 2000UL));
01270 #endif
01271 #if defined(AUDIO_VS1001K)
01272
01273 VsRegWrite(VS_INT_FCTLH_REG, 0x8008);
01274 #endif
01275 NutDelay(1);
01276
01277 #if defined(VS10XX_SDI_SPI0_DEVICE) || defined(VS10XX_SCI_SPI0_DEVICE)
01278
01279 outb(EIFR, BV(VS10XX_DREQ_BIT));
01280 #endif
01281
01282 return 0;
01283 }
01284
01308 int VsPlayerSetMode(uint16_t mode)
01309 {
01310 ureg_t ief;
01311
01312 ief = VsPlayerInterrupts(0);
01313 #if defined(VS10XX_BSYNC_BIT)
01314 VsRegWrite(VS_MODE_REG, mode);
01315 #else
01316 VsRegWrite(VS_MODE_REG, VS_SM_SDINEW | mode);
01317 #endif
01318 VsPlayerInterrupts(ief);
01319
01320 return 0;
01321 }
01322
01328 uint16_t VsPlayTime(void)
01329 {
01330 uint16_t rc;
01331 ureg_t ief;
01332
01333 ief = VsPlayerInterrupts(0);
01334 rc = VsRegRead(VS_DECODE_TIME_REG);
01335 VsPlayerInterrupts(ief);
01336
01337 return rc;
01338 }
01339
01349 unsigned int VsGetStatus(void)
01350 {
01351 return vs_status;
01352 }
01353
01354 #ifdef __GNUC__
01355
01363 int VsGetHeaderInfo(VS_HEADERINFO * vshi)
01364 {
01365 uint16_t *usp = (uint16_t *) vshi;
01366 ureg_t ief;
01367
01368 ief = VsPlayerInterrupts(0);
01369 *usp = VsRegRead(VS_HDAT1_REG);
01370 *++usp = VsRegRead(VS_HDAT0_REG);
01371 VsPlayerInterrupts(ief);
01372
01373 return 0;
01374 }
01375 #endif
01376
01389 uint16_t VsMemoryTest(void)
01390 {
01391 uint16_t rc;
01392 ureg_t ief;
01393 static prog_char mtcmd[] = { 0x4D, 0xEA, 0x6D, 0x54, 0x00, 0x00, 0x00, 0x00 };
01394
01395 ief = VsPlayerInterrupts(0);
01396 #if defined(VS10XX_BSYNC_BIT)
01397 VsRegWrite(VS_MODE_REG, VS_SM_TESTS);
01398 #else
01399 VsRegWrite(VS_MODE_REG, VS_SM_TESTS | VS_SM_SDINEW);
01400 #endif
01401 VsSdiWrite_P(mtcmd, sizeof(mtcmd));
01402 while(((rc = VsRegRead(VS_HDAT0_REG)) & 0x8000) == 0) {
01403 NutDelay(1);
01404 }
01405 #if defined(VS10XX_BSYNC_BIT)
01406 VsRegWrite(VS_MODE_REG, 0);
01407 #else
01408 VsRegWrite(VS_MODE_REG, VS_SM_SDINEW);
01409 #endif
01410 VsPlayerInterrupts(ief);
01411
01412 return rc;
01413 }
01414
01424 int VsSetVolume(ureg_t left, ureg_t right)
01425 {
01426 ureg_t ief;
01427
01428 ief = VsPlayerInterrupts(0);
01429 VsRegWrite(VS_VOL_REG, ((uint16_t)left << VS_VOL_LEFT_LSB) | ((uint16_t)right << VS_VOL_RIGHT_LSB));
01430 VsPlayerInterrupts(ief);
01431
01432 return 0;
01433 }
01434
01443 int VsBeep(uint8_t fsin, uint8_t ms)
01444 {
01445 ureg_t ief;
01446 static prog_char on[] = { 0x53, 0xEF, 0x6E };
01447 static prog_char off[] = { 0x45, 0x78, 0x69, 0x74 };
01448 static prog_char end[] = { 0x00, 0x00, 0x00, 0x00 };
01449
01450
01451 ief = VsPlayerInterrupts(0);
01452
01453 #if defined(VS10XX_BSYNC_BIT)
01454 VsRegWrite(VS_MODE_REG, VS_SM_TESTS);
01455 #else
01456 VsRegWrite(VS_MODE_REG, VS_SM_TESTS | VS_SM_SDINEW);
01457 #endif
01458
01459 fsin = 56 + (fsin & 7) * 9;
01460 VsSdiWrite_P(on, sizeof(on));
01461 VsSdiWrite(&fsin, 1);
01462 VsSdiWrite_P(end, sizeof(end));
01463 NutDelay(ms);
01464 VsSdiWrite_P(off, sizeof(off));
01465 VsSdiWrite_P(end, sizeof(end));
01466
01467 #if defined(VS10XX_BSYNC_BIT)
01468 VsRegWrite(VS_MODE_REG, 0);
01469 #else
01470 VsRegWrite(VS_MODE_REG, VS_SM_SDINEW);
01471 #endif
01472
01473
01474 VsPlayerInterrupts(ief);
01475
01476 return 0;
01477 }
01478
01479