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Nut/OS
5.0.5
API Reference
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Nut/OS
5.0.5
API Reference
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Type definitions for the System Control Block Registers. More...
Data Structures | |
| struct | SCB_Type |
| Structure type to access the System Control Block (SCB). More... | |
Defines | |
| #define | SCB_CPUID_IMPLEMENTER_Pos 24 |
| #define | SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
| #define | SCB_CPUID_VARIANT_Pos 20 |
| #define | SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
| #define | SCB_CPUID_ARCHITECTURE_Pos 16 |
| #define | SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
| #define | SCB_CPUID_PARTNO_Pos 4 |
| #define | SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
| #define | SCB_CPUID_REVISION_Pos 0 |
| #define | SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) |
| #define | SCB_ICSR_NMIPENDSET_Pos 31 |
| #define | SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) |
| #define | SCB_ICSR_PENDSVSET_Pos 28 |
| #define | SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
| #define | SCB_ICSR_PENDSVCLR_Pos 27 |
| #define | SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
| #define | SCB_ICSR_PENDSTSET_Pos 26 |
| #define | SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
| #define | SCB_ICSR_PENDSTCLR_Pos 25 |
| #define | SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
| #define | SCB_ICSR_ISRPREEMPT_Pos 23 |
| #define | SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
| #define | SCB_ICSR_ISRPENDING_Pos 22 |
| #define | SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
| #define | SCB_ICSR_VECTPENDING_Pos 12 |
| #define | SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
| #define | SCB_ICSR_RETTOBASE_Pos 11 |
| #define | SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) |
| #define | SCB_ICSR_VECTACTIVE_Pos 0 |
| #define | SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) |
| #define | SCB_VTOR_TBLBASE_Pos 29 |
| #define | SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) |
| #define | SCB_VTOR_TBLOFF_Pos 7 |
| #define | SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) |
| #define | SCB_AIRCR_VECTKEY_Pos 16 |
| #define | SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
| #define | SCB_AIRCR_VECTKEYSTAT_Pos 16 |
| #define | SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
| #define | SCB_AIRCR_ENDIANESS_Pos 15 |
| #define | SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
| #define | SCB_AIRCR_PRIGROUP_Pos 8 |
| #define | SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) |
| #define | SCB_AIRCR_SYSRESETREQ_Pos 2 |
| #define | SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
| #define | SCB_AIRCR_VECTCLRACTIVE_Pos 1 |
| #define | SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
| #define | SCB_AIRCR_VECTRESET_Pos 0 |
| #define | SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) |
| #define | SCB_SCR_SEVONPEND_Pos 4 |
| #define | SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
| #define | SCB_SCR_SLEEPDEEP_Pos 2 |
| #define | SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
| #define | SCB_SCR_SLEEPONEXIT_Pos 1 |
| #define | SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
| #define | SCB_CCR_STKALIGN_Pos 9 |
| #define | SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) |
| #define | SCB_CCR_BFHFNMIGN_Pos 8 |
| #define | SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) |
| #define | SCB_CCR_DIV_0_TRP_Pos 4 |
| #define | SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) |
| #define | SCB_CCR_UNALIGN_TRP_Pos 3 |
| #define | SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
| #define | SCB_CCR_USERSETMPEND_Pos 1 |
| #define | SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) |
| #define | SCB_CCR_NONBASETHRDENA_Pos 0 |
| #define | SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) |
| #define | SCB_SHCSR_USGFAULTENA_Pos 18 |
| #define | SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) |
| #define | SCB_SHCSR_BUSFAULTENA_Pos 17 |
| #define | SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) |
| #define | SCB_SHCSR_MEMFAULTENA_Pos 16 |
| #define | SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) |
| #define | SCB_SHCSR_SVCALLPENDED_Pos 15 |
| #define | SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
| #define | SCB_SHCSR_BUSFAULTPENDED_Pos 14 |
| #define | SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) |
| #define | SCB_SHCSR_MEMFAULTPENDED_Pos 13 |
| #define | SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) |
| #define | SCB_SHCSR_USGFAULTPENDED_Pos 12 |
| #define | SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) |
| #define | SCB_SHCSR_SYSTICKACT_Pos 11 |
| #define | SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) |
| #define | SCB_SHCSR_PENDSVACT_Pos 10 |
| #define | SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) |
| #define | SCB_SHCSR_MONITORACT_Pos 8 |
| #define | SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) |
| #define | SCB_SHCSR_SVCALLACT_Pos 7 |
| #define | SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) |
| #define | SCB_SHCSR_USGFAULTACT_Pos 3 |
| #define | SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) |
| #define | SCB_SHCSR_BUSFAULTACT_Pos 1 |
| #define | SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) |
| #define | SCB_SHCSR_MEMFAULTACT_Pos 0 |
| #define | SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) |
| #define | SCB_CFSR_USGFAULTSR_Pos 16 |
| #define | SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) |
| #define | SCB_CFSR_BUSFAULTSR_Pos 8 |
| #define | SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) |
| #define | SCB_CFSR_MEMFAULTSR_Pos 0 |
| #define | SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) |
| #define | SCB_HFSR_DEBUGEVT_Pos 31 |
| #define | SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) |
| #define | SCB_HFSR_FORCED_Pos 30 |
| #define | SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) |
| #define | SCB_HFSR_VECTTBL_Pos 1 |
| #define | SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) |
| #define | SCB_DFSR_EXTERNAL_Pos 4 |
| #define | SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) |
| #define | SCB_DFSR_VCATCH_Pos 3 |
| #define | SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) |
| #define | SCB_DFSR_DWTTRAP_Pos 2 |
| #define | SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) |
| #define | SCB_DFSR_BKPT_Pos 1 |
| #define | SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) |
| #define | SCB_DFSR_HALTED_Pos 0 |
| #define | SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) |
| #define | SCB_CPUID_IMPLEMENTER_Pos 24 |
| #define | SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
| #define | SCB_CPUID_VARIANT_Pos 20 |
| #define | SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
| #define | SCB_CPUID_ARCHITECTURE_Pos 16 |
| #define | SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
| #define | SCB_CPUID_PARTNO_Pos 4 |
| #define | SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
| #define | SCB_CPUID_REVISION_Pos 0 |
| #define | SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) |
| #define | SCB_ICSR_NMIPENDSET_Pos 31 |
| #define | SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) |
| #define | SCB_ICSR_PENDSVSET_Pos 28 |
| #define | SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
| #define | SCB_ICSR_PENDSVCLR_Pos 27 |
| #define | SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
| #define | SCB_ICSR_PENDSTSET_Pos 26 |
| #define | SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
| #define | SCB_ICSR_PENDSTCLR_Pos 25 |
| #define | SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
| #define | SCB_ICSR_ISRPREEMPT_Pos 23 |
| #define | SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
| #define | SCB_ICSR_ISRPENDING_Pos 22 |
| #define | SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
| #define | SCB_ICSR_VECTPENDING_Pos 12 |
| #define | SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
| #define | SCB_ICSR_RETTOBASE_Pos 11 |
| #define | SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) |
| #define | SCB_ICSR_VECTACTIVE_Pos 0 |
| #define | SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) |
| #define | SCB_VTOR_TBLOFF_Pos 7 |
| #define | SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) |
| #define | SCB_AIRCR_VECTKEY_Pos 16 |
| #define | SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
| #define | SCB_AIRCR_VECTKEYSTAT_Pos 16 |
| #define | SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
| #define | SCB_AIRCR_ENDIANESS_Pos 15 |
| #define | SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
| #define | SCB_AIRCR_PRIGROUP_Pos 8 |
| #define | SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) |
| #define | SCB_AIRCR_SYSRESETREQ_Pos 2 |
| #define | SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
| #define | SCB_AIRCR_VECTCLRACTIVE_Pos 1 |
| #define | SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
| #define | SCB_AIRCR_VECTRESET_Pos 0 |
| #define | SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) |
| #define | SCB_SCR_SEVONPEND_Pos 4 |
| #define | SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
| #define | SCB_SCR_SLEEPDEEP_Pos 2 |
| #define | SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
| #define | SCB_SCR_SLEEPONEXIT_Pos 1 |
| #define | SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
| #define | SCB_CCR_STKALIGN_Pos 9 |
| #define | SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) |
| #define | SCB_CCR_BFHFNMIGN_Pos 8 |
| #define | SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) |
| #define | SCB_CCR_DIV_0_TRP_Pos 4 |
| #define | SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) |
| #define | SCB_CCR_UNALIGN_TRP_Pos 3 |
| #define | SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
| #define | SCB_CCR_USERSETMPEND_Pos 1 |
| #define | SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) |
| #define | SCB_CCR_NONBASETHRDENA_Pos 0 |
| #define | SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) |
| #define | SCB_SHCSR_USGFAULTENA_Pos 18 |
| #define | SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) |
| #define | SCB_SHCSR_BUSFAULTENA_Pos 17 |
| #define | SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) |
| #define | SCB_SHCSR_MEMFAULTENA_Pos 16 |
| #define | SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) |
| #define | SCB_SHCSR_SVCALLPENDED_Pos 15 |
| #define | SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
| #define | SCB_SHCSR_BUSFAULTPENDED_Pos 14 |
| #define | SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) |
| #define | SCB_SHCSR_MEMFAULTPENDED_Pos 13 |
| #define | SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) |
| #define | SCB_SHCSR_USGFAULTPENDED_Pos 12 |
| #define | SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) |
| #define | SCB_SHCSR_SYSTICKACT_Pos 11 |
| #define | SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) |
| #define | SCB_SHCSR_PENDSVACT_Pos 10 |
| #define | SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) |
| #define | SCB_SHCSR_MONITORACT_Pos 8 |
| #define | SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) |
| #define | SCB_SHCSR_SVCALLACT_Pos 7 |
| #define | SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) |
| #define | SCB_SHCSR_USGFAULTACT_Pos 3 |
| #define | SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) |
| #define | SCB_SHCSR_BUSFAULTACT_Pos 1 |
| #define | SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) |
| #define | SCB_SHCSR_MEMFAULTACT_Pos 0 |
| #define | SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) |
| #define | SCB_CFSR_USGFAULTSR_Pos 16 |
| #define | SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) |
| #define | SCB_CFSR_BUSFAULTSR_Pos 8 |
| #define | SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) |
| #define | SCB_CFSR_MEMFAULTSR_Pos 0 |
| #define | SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) |
| #define | SCB_HFSR_DEBUGEVT_Pos 31 |
| #define | SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) |
| #define | SCB_HFSR_FORCED_Pos 30 |
| #define | SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) |
| #define | SCB_HFSR_VECTTBL_Pos 1 |
| #define | SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) |
| #define | SCB_DFSR_EXTERNAL_Pos 4 |
| #define | SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) |
| #define | SCB_DFSR_VCATCH_Pos 3 |
| #define | SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) |
| #define | SCB_DFSR_DWTTRAP_Pos 2 |
| #define | SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) |
| #define | SCB_DFSR_BKPT_Pos 1 |
| #define | SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) |
| #define | SCB_DFSR_HALTED_Pos 0 |
| #define | SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) |
Type definitions for the System Control Block Registers.
| #define SCB_CPUID_IMPLEMENTER_Pos 24 |
SCB CPUID: IMPLEMENTER Position
| #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
SCB CPUID: IMPLEMENTER Mask
| #define SCB_CPUID_VARIANT_Pos 20 |
SCB CPUID: VARIANT Position
| #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
SCB CPUID: VARIANT Mask
| #define SCB_CPUID_ARCHITECTURE_Pos 16 |
SCB CPUID: ARCHITECTURE Position
| #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
SCB CPUID: ARCHITECTURE Mask
| #define SCB_CPUID_PARTNO_Pos 4 |
SCB CPUID: PARTNO Position
| #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
SCB CPUID: PARTNO Mask
| #define SCB_CPUID_REVISION_Pos 0 |
SCB CPUID: REVISION Position
| #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) |
SCB CPUID: REVISION Mask
| #define SCB_ICSR_NMIPENDSET_Pos 31 |
SCB ICSR: NMIPENDSET Position
| #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) |
SCB ICSR: NMIPENDSET Mask
| #define SCB_ICSR_PENDSVSET_Pos 28 |
SCB ICSR: PENDSVSET Position
| #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
SCB ICSR: PENDSVSET Mask
| #define SCB_ICSR_PENDSVCLR_Pos 27 |
SCB ICSR: PENDSVCLR Position
| #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
SCB ICSR: PENDSVCLR Mask
Referenced by Cortex_IntInit().
| #define SCB_ICSR_PENDSTSET_Pos 26 |
SCB ICSR: PENDSTSET Position
| #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
SCB ICSR: PENDSTSET Mask
| #define SCB_ICSR_PENDSTCLR_Pos 25 |
SCB ICSR: PENDSTCLR Position
| #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
SCB ICSR: PENDSTCLR Mask
Referenced by Cortex_IntInit().
| #define SCB_ICSR_ISRPREEMPT_Pos 23 |
SCB ICSR: ISRPREEMPT Position
| #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
SCB ICSR: ISRPREEMPT Mask
| #define SCB_ICSR_ISRPENDING_Pos 22 |
SCB ICSR: ISRPENDING Position
| #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
SCB ICSR: ISRPENDING Mask
Referenced by Cortex_IntInit().
| #define SCB_ICSR_VECTPENDING_Pos 12 |
SCB ICSR: VECTPENDING Position
| #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
SCB ICSR: VECTPENDING Mask
| #define SCB_ICSR_RETTOBASE_Pos 11 |
SCB ICSR: RETTOBASE Position
| #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) |
SCB ICSR: RETTOBASE Mask
| #define SCB_ICSR_VECTACTIVE_Pos 0 |
SCB ICSR: VECTACTIVE Position
| #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) |
SCB ICSR: VECTACTIVE Mask
| #define SCB_VTOR_TBLBASE_Pos 29 |
SCB VTOR: TBLBASE Position
| #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) |
SCB VTOR: TBLBASE Mask
| #define SCB_VTOR_TBLOFF_Pos 7 |
SCB VTOR: TBLOFF Position
| #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) |
SCB VTOR: TBLOFF Mask
| #define SCB_AIRCR_VECTKEY_Pos 16 |
SCB AIRCR: VECTKEY Position
Referenced by NVIC_SetPriorityGrouping(), and NVIC_SystemReset().
| #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
SCB AIRCR: VECTKEY Mask
Referenced by NVIC_SetPriorityGrouping().
| #define SCB_AIRCR_VECTKEYSTAT_Pos 16 |
SCB AIRCR: VECTKEYSTAT Position
| #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
SCB AIRCR: VECTKEYSTAT Mask
| #define SCB_AIRCR_ENDIANESS_Pos 15 |
SCB AIRCR: ENDIANESS Position
| #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
SCB AIRCR: ENDIANESS Mask
| #define SCB_AIRCR_PRIGROUP_Pos 8 |
SCB AIRCR: PRIGROUP Position
Referenced by NVIC_GetPriorityGrouping().
| #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) |
SCB AIRCR: PRIGROUP Mask
Referenced by NVIC_GetPriorityGrouping(), NVIC_SetPriorityGrouping(), and NVIC_SystemReset().
| #define SCB_AIRCR_SYSRESETREQ_Pos 2 |
SCB AIRCR: SYSRESETREQ Position
| #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
SCB AIRCR: SYSRESETREQ Mask
Referenced by NVIC_SystemReset().
| #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 |
SCB AIRCR: VECTCLRACTIVE Position
| #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
SCB AIRCR: VECTCLRACTIVE Mask
| #define SCB_AIRCR_VECTRESET_Pos 0 |
SCB AIRCR: VECTRESET Position
| #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) |
SCB AIRCR: VECTRESET Mask
| #define SCB_SCR_SEVONPEND_Pos 4 |
SCB SCR: SEVONPEND Position
| #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
SCB SCR: SEVONPEND Mask
| #define SCB_SCR_SLEEPDEEP_Pos 2 |
SCB SCR: SLEEPDEEP Position
| #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
SCB SCR: SLEEPDEEP Mask
| #define SCB_SCR_SLEEPONEXIT_Pos 1 |
SCB SCR: SLEEPONEXIT Position
| #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
SCB SCR: SLEEPONEXIT Mask
| #define SCB_CCR_STKALIGN_Pos 9 |
SCB CCR: STKALIGN Position
| #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) |
SCB CCR: STKALIGN Mask
| #define SCB_CCR_BFHFNMIGN_Pos 8 |
SCB CCR: BFHFNMIGN Position
| #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) |
SCB CCR: BFHFNMIGN Mask
| #define SCB_CCR_DIV_0_TRP_Pos 4 |
SCB CCR: DIV_0_TRP Position
| #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) |
SCB CCR: DIV_0_TRP Mask
| #define SCB_CCR_UNALIGN_TRP_Pos 3 |
SCB CCR: UNALIGN_TRP Position
| #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
SCB CCR: UNALIGN_TRP Mask
| #define SCB_CCR_USERSETMPEND_Pos 1 |
SCB CCR: USERSETMPEND Position
| #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) |
SCB CCR: USERSETMPEND Mask
| #define SCB_CCR_NONBASETHRDENA_Pos 0 |
SCB CCR: NONBASETHRDENA Position
| #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) |
SCB CCR: NONBASETHRDENA Mask
| #define SCB_SHCSR_USGFAULTENA_Pos 18 |
SCB SHCSR: USGFAULTENA Position
| #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) |
SCB SHCSR: USGFAULTENA Mask
Referenced by IntDisable(), IntEnable(), and IntIsEnabled().
| #define SCB_SHCSR_BUSFAULTENA_Pos 17 |
SCB SHCSR: BUSFAULTENA Position
| #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) |
SCB SHCSR: BUSFAULTENA Mask
Referenced by IntDisable(), IntEnable(), and IntIsEnabled().
| #define SCB_SHCSR_MEMFAULTENA_Pos 16 |
SCB SHCSR: MEMFAULTENA Position
| #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) |
SCB SHCSR: MEMFAULTENA Mask
Referenced by IntDisable(), IntEnable(), and IntIsEnabled().
| #define SCB_SHCSR_SVCALLPENDED_Pos 15 |
SCB SHCSR: SVCALLPENDED Position
| #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
SCB SHCSR: SVCALLPENDED Mask
| #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 |
SCB SHCSR: BUSFAULTPENDED Position
| #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) |
SCB SHCSR: BUSFAULTPENDED Mask
| #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 |
SCB SHCSR: MEMFAULTPENDED Position
| #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) |
SCB SHCSR: MEMFAULTPENDED Mask
| #define SCB_SHCSR_USGFAULTPENDED_Pos 12 |
SCB SHCSR: USGFAULTPENDED Position
| #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) |
SCB SHCSR: USGFAULTPENDED Mask
| #define SCB_SHCSR_SYSTICKACT_Pos 11 |
SCB SHCSR: SYSTICKACT Position
| #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) |
SCB SHCSR: SYSTICKACT Mask
| #define SCB_SHCSR_PENDSVACT_Pos 10 |
SCB SHCSR: PENDSVACT Position
| #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) |
SCB SHCSR: PENDSVACT Mask
| #define SCB_SHCSR_MONITORACT_Pos 8 |
SCB SHCSR: MONITORACT Position
| #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) |
SCB SHCSR: MONITORACT Mask
| #define SCB_SHCSR_SVCALLACT_Pos 7 |
SCB SHCSR: SVCALLACT Position
| #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) |
SCB SHCSR: SVCALLACT Mask
| #define SCB_SHCSR_USGFAULTACT_Pos 3 |
SCB SHCSR: USGFAULTACT Position
| #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) |
SCB SHCSR: USGFAULTACT Mask
| #define SCB_SHCSR_BUSFAULTACT_Pos 1 |
SCB SHCSR: BUSFAULTACT Position
| #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) |
SCB SHCSR: BUSFAULTACT Mask
| #define SCB_SHCSR_MEMFAULTACT_Pos 0 |
SCB SHCSR: MEMFAULTACT Position
| #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) |
SCB SHCSR: MEMFAULTACT Mask
| #define SCB_CFSR_USGFAULTSR_Pos 16 |
SCB CFSR: Usage Fault Status Register Position
| #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) |
SCB CFSR: Usage Fault Status Register Mask
| #define SCB_CFSR_BUSFAULTSR_Pos 8 |
SCB CFSR: Bus Fault Status Register Position
| #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) |
SCB CFSR: Bus Fault Status Register Mask
| #define SCB_CFSR_MEMFAULTSR_Pos 0 |
SCB CFSR: Memory Manage Fault Status Register Position
| #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) |
SCB CFSR: Memory Manage Fault Status Register Mask
| #define SCB_HFSR_DEBUGEVT_Pos 31 |
SCB HFSR: DEBUGEVT Position
| #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) |
SCB HFSR: DEBUGEVT Mask
| #define SCB_HFSR_FORCED_Pos 30 |
SCB HFSR: FORCED Position
| #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) |
SCB HFSR: FORCED Mask
| #define SCB_HFSR_VECTTBL_Pos 1 |
SCB HFSR: VECTTBL Position
| #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) |
SCB HFSR: VECTTBL Mask
| #define SCB_DFSR_EXTERNAL_Pos 4 |
SCB DFSR: EXTERNAL Position
| #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) |
SCB DFSR: EXTERNAL Mask
| #define SCB_DFSR_VCATCH_Pos 3 |
SCB DFSR: VCATCH Position
| #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) |
SCB DFSR: VCATCH Mask
| #define SCB_DFSR_DWTTRAP_Pos 2 |
SCB DFSR: DWTTRAP Position
| #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) |
SCB DFSR: DWTTRAP Mask
| #define SCB_DFSR_BKPT_Pos 1 |
SCB DFSR: BKPT Position
| #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) |
SCB DFSR: BKPT Mask
| #define SCB_DFSR_HALTED_Pos 0 |
SCB DFSR: HALTED Position
| #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) |
SCB DFSR: HALTED Mask
| #define SCB_CPUID_IMPLEMENTER_Pos 24 |
SCB CPUID: IMPLEMENTER Position
| #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) |
SCB CPUID: IMPLEMENTER Mask
| #define SCB_CPUID_VARIANT_Pos 20 |
SCB CPUID: VARIANT Position
| #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) |
SCB CPUID: VARIANT Mask
| #define SCB_CPUID_ARCHITECTURE_Pos 16 |
SCB CPUID: ARCHITECTURE Position
| #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) |
SCB CPUID: ARCHITECTURE Mask
| #define SCB_CPUID_PARTNO_Pos 4 |
SCB CPUID: PARTNO Position
| #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) |
SCB CPUID: PARTNO Mask
| #define SCB_CPUID_REVISION_Pos 0 |
SCB CPUID: REVISION Position
| #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) |
SCB CPUID: REVISION Mask
| #define SCB_ICSR_NMIPENDSET_Pos 31 |
SCB ICSR: NMIPENDSET Position
| #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) |
SCB ICSR: NMIPENDSET Mask
| #define SCB_ICSR_PENDSVSET_Pos 28 |
SCB ICSR: PENDSVSET Position
| #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) |
SCB ICSR: PENDSVSET Mask
| #define SCB_ICSR_PENDSVCLR_Pos 27 |
SCB ICSR: PENDSVCLR Position
| #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) |
SCB ICSR: PENDSVCLR Mask
| #define SCB_ICSR_PENDSTSET_Pos 26 |
SCB ICSR: PENDSTSET Position
| #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) |
SCB ICSR: PENDSTSET Mask
| #define SCB_ICSR_PENDSTCLR_Pos 25 |
SCB ICSR: PENDSTCLR Position
| #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) |
SCB ICSR: PENDSTCLR Mask
| #define SCB_ICSR_ISRPREEMPT_Pos 23 |
SCB ICSR: ISRPREEMPT Position
| #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) |
SCB ICSR: ISRPREEMPT Mask
| #define SCB_ICSR_ISRPENDING_Pos 22 |
SCB ICSR: ISRPENDING Position
| #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) |
SCB ICSR: ISRPENDING Mask
| #define SCB_ICSR_VECTPENDING_Pos 12 |
SCB ICSR: VECTPENDING Position
| #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) |
SCB ICSR: VECTPENDING Mask
| #define SCB_ICSR_RETTOBASE_Pos 11 |
SCB ICSR: RETTOBASE Position
| #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) |
SCB ICSR: RETTOBASE Mask
| #define SCB_ICSR_VECTACTIVE_Pos 0 |
SCB ICSR: VECTACTIVE Position
| #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) |
SCB ICSR: VECTACTIVE Mask
| #define SCB_VTOR_TBLOFF_Pos 7 |
SCB VTOR: TBLOFF Position
| #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) |
SCB VTOR: TBLOFF Mask
| #define SCB_AIRCR_VECTKEY_Pos 16 |
SCB AIRCR: VECTKEY Position
| #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) |
SCB AIRCR: VECTKEY Mask
| #define SCB_AIRCR_VECTKEYSTAT_Pos 16 |
SCB AIRCR: VECTKEYSTAT Position
| #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) |
SCB AIRCR: VECTKEYSTAT Mask
| #define SCB_AIRCR_ENDIANESS_Pos 15 |
SCB AIRCR: ENDIANESS Position
| #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) |
SCB AIRCR: ENDIANESS Mask
| #define SCB_AIRCR_PRIGROUP_Pos 8 |
SCB AIRCR: PRIGROUP Position
| #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) |
SCB AIRCR: PRIGROUP Mask
| #define SCB_AIRCR_SYSRESETREQ_Pos 2 |
SCB AIRCR: SYSRESETREQ Position
| #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) |
SCB AIRCR: SYSRESETREQ Mask
| #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 |
SCB AIRCR: VECTCLRACTIVE Position
| #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) |
SCB AIRCR: VECTCLRACTIVE Mask
| #define SCB_AIRCR_VECTRESET_Pos 0 |
SCB AIRCR: VECTRESET Position
| #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) |
SCB AIRCR: VECTRESET Mask
| #define SCB_SCR_SEVONPEND_Pos 4 |
SCB SCR: SEVONPEND Position
| #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) |
SCB SCR: SEVONPEND Mask
| #define SCB_SCR_SLEEPDEEP_Pos 2 |
SCB SCR: SLEEPDEEP Position
| #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) |
SCB SCR: SLEEPDEEP Mask
| #define SCB_SCR_SLEEPONEXIT_Pos 1 |
SCB SCR: SLEEPONEXIT Position
| #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) |
SCB SCR: SLEEPONEXIT Mask
| #define SCB_CCR_STKALIGN_Pos 9 |
SCB CCR: STKALIGN Position
| #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) |
SCB CCR: STKALIGN Mask
| #define SCB_CCR_BFHFNMIGN_Pos 8 |
SCB CCR: BFHFNMIGN Position
| #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) |
SCB CCR: BFHFNMIGN Mask
| #define SCB_CCR_DIV_0_TRP_Pos 4 |
SCB CCR: DIV_0_TRP Position
| #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) |
SCB CCR: DIV_0_TRP Mask
| #define SCB_CCR_UNALIGN_TRP_Pos 3 |
SCB CCR: UNALIGN_TRP Position
| #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) |
SCB CCR: UNALIGN_TRP Mask
| #define SCB_CCR_USERSETMPEND_Pos 1 |
SCB CCR: USERSETMPEND Position
| #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) |
SCB CCR: USERSETMPEND Mask
| #define SCB_CCR_NONBASETHRDENA_Pos 0 |
SCB CCR: NONBASETHRDENA Position
| #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) |
SCB CCR: NONBASETHRDENA Mask
| #define SCB_SHCSR_USGFAULTENA_Pos 18 |
SCB SHCSR: USGFAULTENA Position
| #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) |
SCB SHCSR: USGFAULTENA Mask
| #define SCB_SHCSR_BUSFAULTENA_Pos 17 |
SCB SHCSR: BUSFAULTENA Position
| #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) |
SCB SHCSR: BUSFAULTENA Mask
| #define SCB_SHCSR_MEMFAULTENA_Pos 16 |
SCB SHCSR: MEMFAULTENA Position
| #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) |
SCB SHCSR: MEMFAULTENA Mask
| #define SCB_SHCSR_SVCALLPENDED_Pos 15 |
SCB SHCSR: SVCALLPENDED Position
| #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) |
SCB SHCSR: SVCALLPENDED Mask
| #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 |
SCB SHCSR: BUSFAULTPENDED Position
| #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) |
SCB SHCSR: BUSFAULTPENDED Mask
| #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 |
SCB SHCSR: MEMFAULTPENDED Position
| #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) |
SCB SHCSR: MEMFAULTPENDED Mask
| #define SCB_SHCSR_USGFAULTPENDED_Pos 12 |
SCB SHCSR: USGFAULTPENDED Position
| #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) |
SCB SHCSR: USGFAULTPENDED Mask
| #define SCB_SHCSR_SYSTICKACT_Pos 11 |
SCB SHCSR: SYSTICKACT Position
| #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) |
SCB SHCSR: SYSTICKACT Mask
| #define SCB_SHCSR_PENDSVACT_Pos 10 |
SCB SHCSR: PENDSVACT Position
| #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) |
SCB SHCSR: PENDSVACT Mask
| #define SCB_SHCSR_MONITORACT_Pos 8 |
SCB SHCSR: MONITORACT Position
| #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) |
SCB SHCSR: MONITORACT Mask
| #define SCB_SHCSR_SVCALLACT_Pos 7 |
SCB SHCSR: SVCALLACT Position
| #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) |
SCB SHCSR: SVCALLACT Mask
| #define SCB_SHCSR_USGFAULTACT_Pos 3 |
SCB SHCSR: USGFAULTACT Position
| #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) |
SCB SHCSR: USGFAULTACT Mask
| #define SCB_SHCSR_BUSFAULTACT_Pos 1 |
SCB SHCSR: BUSFAULTACT Position
| #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) |
SCB SHCSR: BUSFAULTACT Mask
| #define SCB_SHCSR_MEMFAULTACT_Pos 0 |
SCB SHCSR: MEMFAULTACT Position
| #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) |
SCB SHCSR: MEMFAULTACT Mask
| #define SCB_CFSR_USGFAULTSR_Pos 16 |
SCB CFSR: Usage Fault Status Register Position
| #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) |
SCB CFSR: Usage Fault Status Register Mask
| #define SCB_CFSR_BUSFAULTSR_Pos 8 |
SCB CFSR: Bus Fault Status Register Position
| #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) |
SCB CFSR: Bus Fault Status Register Mask
| #define SCB_CFSR_MEMFAULTSR_Pos 0 |
SCB CFSR: Memory Manage Fault Status Register Position
| #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) |
SCB CFSR: Memory Manage Fault Status Register Mask
| #define SCB_HFSR_DEBUGEVT_Pos 31 |
SCB HFSR: DEBUGEVT Position
| #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) |
SCB HFSR: DEBUGEVT Mask
| #define SCB_HFSR_FORCED_Pos 30 |
SCB HFSR: FORCED Position
| #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) |
SCB HFSR: FORCED Mask
| #define SCB_HFSR_VECTTBL_Pos 1 |
SCB HFSR: VECTTBL Position
| #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) |
SCB HFSR: VECTTBL Mask
| #define SCB_DFSR_EXTERNAL_Pos 4 |
SCB DFSR: EXTERNAL Position
| #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) |
SCB DFSR: EXTERNAL Mask
| #define SCB_DFSR_VCATCH_Pos 3 |
SCB DFSR: VCATCH Position
| #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) |
SCB DFSR: VCATCH Mask
| #define SCB_DFSR_DWTTRAP_Pos 2 |
SCB DFSR: DWTTRAP Position
| #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) |
SCB DFSR: DWTTRAP Mask
| #define SCB_DFSR_BKPT_Pos 1 |
SCB DFSR: BKPT Position
| #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) |
SCB DFSR: BKPT Mask
| #define SCB_DFSR_HALTED_Pos 0 |
SCB DFSR: HALTED Position
| #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) |
SCB DFSR: HALTED Mask