Type definitions for the Trace Port Interface (TPI) More...

Collaboration diagram for Trace Port Interface (TPI):

Data Structures
struct	TPI_Type
	Structure type to access the Trace Port Interface Register (TPI). More...
Defines
#define	TPI_ACPR_PRESCALER_Pos 0
#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)
#define	TPI_SPPR_TXMODE_Pos 0
#define	TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos)
#define	TPI_FFSR_FtNonStop_Pos 3
#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
#define	TPI_FFSR_TCPresent_Pos 2
#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
#define	TPI_FFSR_FtStopped_Pos 1
#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
#define	TPI_FFSR_FlInProg_Pos 0
#define	TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos)
#define	TPI_FFCR_TrigIn_Pos 8
#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
#define	TPI_FFCR_EnFCont_Pos 1
#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)
#define	TPI_TRIGGER_TRIGGER_Pos 0
#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos)
#define	TPI_FIFO0_ITM_ATVALID_Pos 29
#define	TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)
#define	TPI_FIFO0_ITM_bytecount_Pos 27
#define	TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)
#define	TPI_FIFO0_ETM_ATVALID_Pos 26
#define	TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)
#define	TPI_FIFO0_ETM_bytecount_Pos 24
#define	TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)
#define	TPI_FIFO0_ETM2_Pos 16
#define	TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)
#define	TPI_FIFO0_ETM1_Pos 8
#define	TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)
#define	TPI_FIFO0_ETM0_Pos 0
#define	TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos)
#define	TPI_ITATBCTR2_ATREADY_Pos 0
#define	TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)
#define	TPI_FIFO1_ITM_ATVALID_Pos 29
#define	TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)
#define	TPI_FIFO1_ITM_bytecount_Pos 27
#define	TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)
#define	TPI_FIFO1_ETM_ATVALID_Pos 26
#define	TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)
#define	TPI_FIFO1_ETM_bytecount_Pos 24
#define	TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)
#define	TPI_FIFO1_ITM2_Pos 16
#define	TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)
#define	TPI_FIFO1_ITM1_Pos 8
#define	TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)
#define	TPI_FIFO1_ITM0_Pos 0
#define	TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos)
#define	TPI_ITATBCTR0_ATREADY_Pos 0
#define	TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)
#define	TPI_ITCTRL_Mode_Pos 0
#define	TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos)
#define	TPI_DEVID_NRZVALID_Pos 11
#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
#define	TPI_DEVID_MANCVALID_Pos 10
#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
#define	TPI_DEVID_PTINVALID_Pos 9
#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
#define	TPI_DEVID_MinBufSz_Pos 6
#define	TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)
#define	TPI_DEVID_AsynClkIn_Pos 5
#define	TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)
#define	TPI_DEVID_NrTraceInput_Pos 0
#define	TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos)
#define	TPI_DEVTYPE_SubType_Pos 0
#define	TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos)
#define	TPI_DEVTYPE_MajorType_Pos 4
#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)
#define	TPI_ACPR_PRESCALER_Pos 0
#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)
#define	TPI_SPPR_TXMODE_Pos 0
#define	TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos)
#define	TPI_FFSR_FtNonStop_Pos 3
#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
#define	TPI_FFSR_TCPresent_Pos 2
#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
#define	TPI_FFSR_FtStopped_Pos 1
#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
#define	TPI_FFSR_FlInProg_Pos 0
#define	TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos)
#define	TPI_FFCR_TrigIn_Pos 8
#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
#define	TPI_FFCR_EnFCont_Pos 1
#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)
#define	TPI_TRIGGER_TRIGGER_Pos 0
#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos)
#define	TPI_FIFO0_ITM_ATVALID_Pos 29
#define	TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)
#define	TPI_FIFO0_ITM_bytecount_Pos 27
#define	TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)
#define	TPI_FIFO0_ETM_ATVALID_Pos 26
#define	TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)
#define	TPI_FIFO0_ETM_bytecount_Pos 24
#define	TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)
#define	TPI_FIFO0_ETM2_Pos 16
#define	TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)
#define	TPI_FIFO0_ETM1_Pos 8
#define	TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)
#define	TPI_FIFO0_ETM0_Pos 0
#define	TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos)
#define	TPI_ITATBCTR2_ATREADY_Pos 0
#define	TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)
#define	TPI_FIFO1_ITM_ATVALID_Pos 29
#define	TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)
#define	TPI_FIFO1_ITM_bytecount_Pos 27
#define	TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)
#define	TPI_FIFO1_ETM_ATVALID_Pos 26
#define	TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)
#define	TPI_FIFO1_ETM_bytecount_Pos 24
#define	TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)
#define	TPI_FIFO1_ITM2_Pos 16
#define	TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)
#define	TPI_FIFO1_ITM1_Pos 8
#define	TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)
#define	TPI_FIFO1_ITM0_Pos 0
#define	TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos)
#define	TPI_ITATBCTR0_ATREADY_Pos 0
#define	TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)
#define	TPI_ITCTRL_Mode_Pos 0
#define	TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos)
#define	TPI_DEVID_NRZVALID_Pos 11
#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
#define	TPI_DEVID_MANCVALID_Pos 10
#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
#define	TPI_DEVID_PTINVALID_Pos 9
#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
#define	TPI_DEVID_MinBufSz_Pos 6
#define	TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)
#define	TPI_DEVID_AsynClkIn_Pos 5
#define	TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)
#define	TPI_DEVID_NrTraceInput_Pos 0
#define	TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos)
#define	TPI_DEVTYPE_SubType_Pos 0
#define	TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos)
#define	TPI_DEVTYPE_MajorType_Pos 4
#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

Detailed Description

Type definitions for the Trace Port Interface (TPI)

Define Documentation

#define TPI_ACPR_PRESCALER_Pos 0

TPI ACPR: PRESCALER Position

#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)

TPI ACPR: PRESCALER Mask

#define TPI_SPPR_TXMODE_Pos 0

TPI SPPR: TXMODE Position

#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos)

TPI SPPR: TXMODE Mask

#define TPI_FFSR_FtNonStop_Pos 3

TPI FFSR: FtNonStop Position

#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

TPI FFSR: FtNonStop Mask

#define TPI_FFSR_TCPresent_Pos 2

TPI FFSR: TCPresent Position

#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

TPI FFSR: TCPresent Mask

#define TPI_FFSR_FtStopped_Pos 1

TPI FFSR: FtStopped Position

#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

TPI FFSR: FtStopped Mask

#define TPI_FFSR_FlInProg_Pos 0

TPI FFSR: FlInProg Position

#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos)

TPI FFSR: FlInProg Mask

#define TPI_FFCR_TrigIn_Pos 8

TPI FFCR: TrigIn Position

#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

TPI FFCR: TrigIn Mask

#define TPI_FFCR_EnFCont_Pos 1

TPI FFCR: EnFCont Position

#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

TPI FFCR: EnFCont Mask

#define TPI_TRIGGER_TRIGGER_Pos 0

TPI TRIGGER: TRIGGER Position

#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos)

TPI TRIGGER: TRIGGER Mask

#define TPI_FIFO0_ITM_ATVALID_Pos 29

TPI FIFO0: ITM_ATVALID Position

#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)

TPI FIFO0: ITM_ATVALID Mask

#define TPI_FIFO0_ITM_bytecount_Pos 27

TPI FIFO0: ITM_bytecount Position

#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)

TPI FIFO0: ITM_bytecount Mask

#define TPI_FIFO0_ETM_ATVALID_Pos 26

TPI FIFO0: ETM_ATVALID Position

#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)

TPI FIFO0: ETM_ATVALID Mask

#define TPI_FIFO0_ETM_bytecount_Pos 24

TPI FIFO0: ETM_bytecount Position

#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)

TPI FIFO0: ETM_bytecount Mask

#define TPI_FIFO0_ETM2_Pos 16

TPI FIFO0: ETM2 Position

#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)

TPI FIFO0: ETM2 Mask

#define TPI_FIFO0_ETM1_Pos 8

TPI FIFO0: ETM1 Position

#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)

TPI FIFO0: ETM1 Mask

#define TPI_FIFO0_ETM0_Pos 0

TPI FIFO0: ETM0 Position

#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos)

TPI FIFO0: ETM0 Mask

#define TPI_ITATBCTR2_ATREADY_Pos 0

TPI ITATBCTR2: ATREADY Position

#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)

TPI ITATBCTR2: ATREADY Mask

#define TPI_FIFO1_ITM_ATVALID_Pos 29

TPI FIFO1: ITM_ATVALID Position

#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)

TPI FIFO1: ITM_ATVALID Mask

#define TPI_FIFO1_ITM_bytecount_Pos 27

TPI FIFO1: ITM_bytecount Position

#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)

TPI FIFO1: ITM_bytecount Mask

#define TPI_FIFO1_ETM_ATVALID_Pos 26

TPI FIFO1: ETM_ATVALID Position

#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)

TPI FIFO1: ETM_ATVALID Mask

#define TPI_FIFO1_ETM_bytecount_Pos 24

TPI FIFO1: ETM_bytecount Position

#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)

TPI FIFO1: ETM_bytecount Mask

#define TPI_FIFO1_ITM2_Pos 16

TPI FIFO1: ITM2 Position

#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)

TPI FIFO1: ITM2 Mask

#define TPI_FIFO1_ITM1_Pos 8

TPI FIFO1: ITM1 Position

#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)

TPI FIFO1: ITM1 Mask

#define TPI_FIFO1_ITM0_Pos 0

TPI FIFO1: ITM0 Position

#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos)

TPI FIFO1: ITM0 Mask

#define TPI_ITATBCTR0_ATREADY_Pos 0

TPI ITATBCTR0: ATREADY Position

#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)

TPI ITATBCTR0: ATREADY Mask

#define TPI_ITCTRL_Mode_Pos 0

TPI ITCTRL: Mode Position

#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos)

TPI ITCTRL: Mode Mask

#define TPI_DEVID_NRZVALID_Pos 11

TPI DEVID: NRZVALID Position

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

#define TPI_DEVID_MANCVALID_Pos 10

TPI DEVID: MANCVALID Position

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

#define TPI_DEVID_PTINVALID_Pos 9

TPI DEVID: PTINVALID Position

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

#define TPI_DEVID_MinBufSz_Pos 6

TPI DEVID: MinBufSz Position

#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

TPI DEVID: MinBufSz Mask

#define TPI_DEVID_AsynClkIn_Pos 5

TPI DEVID: AsynClkIn Position

#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

TPI DEVID: AsynClkIn Mask

#define TPI_DEVID_NrTraceInput_Pos 0

TPI DEVID: NrTraceInput Position

#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos)

TPI DEVID: NrTraceInput Mask

#define TPI_DEVTYPE_SubType_Pos 0

TPI DEVTYPE: SubType Position

#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos)

TPI DEVTYPE: SubType Mask

#define TPI_DEVTYPE_MajorType_Pos 4

TPI DEVTYPE: MajorType Position

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask